bbracker
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2203590f9f
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get current privilege level from GDB for checkpoints
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2021-11-15 14:49:00 -08:00 |
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Skylar Litz
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3dd83b3113
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fix timing of delayed interrupt
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2021-11-11 09:35:51 -08:00 |
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bbracker
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c92d41a597
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checkpoint MIDELEG support
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2021-11-06 03:44:23 -07:00 |
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bbracker
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bc6332a780
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fix merge conflict
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2021-11-05 23:42:15 -07:00 |
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bbracker
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17e776f853
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checkpoints now use binary ram files
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2021-11-05 22:37:05 -07:00 |
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bbracker
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0c7681b942
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fix testbench interrupt timing
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2021-11-02 21:19:12 -07:00 |
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David Harris
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d7f0abca5a
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Add3d wally32i test
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2021-11-01 13:17:49 -07:00 |
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David Harris
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dda035891a
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PIPELINE test running
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2021-11-01 12:44:35 -07:00 |
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David Harris
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60573b92b2
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Adding custom Wally test infrastructure
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2021-11-01 08:48:46 -07:00 |
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David Harris
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360930fe8b
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Fixed exe2memfile parsing of weird line in arch64d test
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2021-10-30 07:26:18 -07:00 |
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David Harris
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247f247ad3
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tesgen cleanup, added riscv-arch-test D tests
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2021-10-29 22:31:48 -07:00 |
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David Harris
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7df4b0c8e7
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commented out some failing FPU tests
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2021-10-27 11:27:34 -07:00 |
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David Harris
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582c2bf37b
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Fixed FResultSelM to select proper flags
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2021-10-27 11:02:42 -07:00 |
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David Harris
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5783e47e1a
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Changes for floating point sims
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2021-10-27 10:37:35 -07:00 |
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David Harris
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90cf37b881
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commented out nonworking tests
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2021-10-26 08:56:49 -07:00 |
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David Harris
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67adc1d7d5
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removed referenc outputs
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2021-10-26 08:51:49 -07:00 |
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bbracker
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66e53929ce
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adapt testbench linux to use reset_ext
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2021-10-25 13:26:44 -07:00 |
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bbracker
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39efadf2cf
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-10-25 12:25:37 -07:00 |
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bbracker
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8c4e6baf48
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change CHECKPOINT to be a parameter (not a macro) so that do scripts can control it; clean up checkpoint initialization macros
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2021-10-25 12:25:32 -07:00 |
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David Harris
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2bf51362e2
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Added synchronizer to reset
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2021-10-25 10:05:41 -07:00 |
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bbracker
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9b98a499d7
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some linux testbench cleanup
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2021-10-25 10:04:30 -07:00 |
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bbracker
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046a78a8fc
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manually resolved git merge conflicts in testbench linux after checkpointing
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2021-10-24 15:02:19 -07:00 |
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bbracker
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36b39358c6
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add checkpointing to linux testbench
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2021-10-24 06:47:35 -07:00 |
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bbracker
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26eead1c77
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add W stage signals to linux testbench
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2021-10-23 14:00:53 -07:00 |
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bbracker
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de6a52f6eb
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-10-23 13:17:37 -07:00 |
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bbracker
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3c0b0987d2
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add option for regression to do a partial execution of buildroot
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2021-10-23 13:17:30 -07:00 |
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David Harris
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2cfbd888fd
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more lsu/ifu lint cleanup
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2021-10-23 12:00:32 -07:00 |
|
David Harris
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e2e950ac0f
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Cleaned up LINT erors
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2021-10-23 06:28:49 -07:00 |
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David Harris
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4c480a40f6
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-10-23 06:15:49 -07:00 |
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David Harris
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3249d65209
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Added -lint flag to vsim. Cleaned some lint errors. Moved lint-wally to regression directory for convenience.
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2021-10-23 06:15:26 -07:00 |
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Katherine Parry
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7c7c0f538a
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put the FMA priority encoders into their own module
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2021-10-22 10:03:12 -07:00 |
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David Harris
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47e19d4caa
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moved coemark and testsBP to tests
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2021-10-20 09:10:06 -07:00 |
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David Harris
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00d8035836
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Fixed multiplier and pointed arch tests to new path in addins
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2021-10-18 15:43:59 -07:00 |
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James E. Stine
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c5b99300e7
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Clean up some signals - beautification onging
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2021-10-14 17:12:00 -05:00 |
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Kip Macsai-Goren
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869c35ba1c
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Fixed typo in imperas64mmu tests causing PMP tests not to run.
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2021-10-14 13:42:24 -07:00 |
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James E. Stine
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1dba57dce7
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Update to fpdivsqrt to go on posedge as it should. Also an update to
individual regression test for TestFloat (still needs some tweaking)
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2021-10-13 17:14:42 -05:00 |
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bbracker
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4abc6fc915
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change infrastructure to expect only 6.3 million from buildroot
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2021-10-12 10:41:15 -07:00 |
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David Harris
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75c17dc372
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Major reorganization of regression and simulation and testbenches
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2021-10-10 15:07:51 -07:00 |
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James E. Stine
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2b66615812
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Update to missing vectors :P and also run_all script. Also made all scripts .sh as technically run using SH
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2021-10-10 15:44:01 -05:00 |
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bbracker
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a88ae5aaff
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use correct string formatting function
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2021-10-10 10:09:59 -07:00 |
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bbracker
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6fce53d146
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make testbench-linux halt on some discrepancies with QEMUw
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2021-10-09 17:22:30 -07:00 |
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Kip Macsai-Goren
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303beaa083
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updated pmp output to correspond to test changes, commented out execute tests until cache/fence interaction works fully.
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2021-10-08 15:40:18 -07:00 |
|
David Harris
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3d0383c154
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moved fp vectors into vectors subdirectory
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2021-10-07 23:28:06 -04:00 |
|
David Harris
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6dd85b80a2
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Included TestFloat and SoftFloat
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2021-10-07 23:03:45 -04:00 |
|
James E. Stine
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28e147bb19
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update scripts
|
2021-10-07 15:14:54 -05:00 |
|
James E. Stine
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8429078d4f
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TV for conversion and compare
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2021-10-06 14:38:32 -05:00 |
|
James E. Stine
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93668b5185
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Update to testbench for FP stuff
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2021-10-06 13:16:38 -05:00 |
|
James E. Stine
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2afa6e7a6e
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Add TV for testbenches (to be added shortly) however had to leave off fma due to size. The TV were slightly modified within TestFloat to add underscores for readability. The scripts I created to create these TV were also included
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2021-10-06 08:56:01 -05:00 |
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Skylar Litz
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5bcae393c9
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added delayed MIP signal
|
2021-10-04 18:23:31 -04:00 |
|
David Harris
|
48e33c79a9
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Reduced cycle count for DIVW/DIVUW by two
|
2021-10-03 09:42:22 -04:00 |
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