418 Commits

Author	SHA1	Message	Date
David Harris	21a65f45cd	Partial work on Unpacking exponents to larger word size. FCVT and FMA are presently broken.	2021-07-22 14:18:27 -04:00
bbracker	cca16cc5b4	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-21 20:07:03 -04:00
bbracker	6e460c5032	replace physical address checking with virtual address checking because address translator is broken	2021-07-21 19:47:13 -04:00
Katherine Parry	01f0b4e5df	FDIV and FSQRT work	2021-07-21 14:08:14 -04:00
Katherine Parry	b9081e514c	FMA parameterized	2021-07-20 22:04:21 -04:00
bbracker	f9b6bd91f5	fix PC checking during InstrPageFault; fix order of S-mode CSR checking; rename peripheral scopes to not be genblk	2021-07-20 17:55:44 -04:00
bbracker	a02694a529	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-20 15:04:13 -04:00
bbracker	a3823ce3a9	commented out old hack that used hardcoded addresses	2021-07-20 15:03:55 -04:00
David Harris	e5e3f5abe6	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-20 14:46:58 -04:00
David Harris	1f3dfa20f6	flag for optional boottim	2021-07-20 14:46:37 -04:00
bbracker	6b72b1f859	ignore mhpmcounters because QEMU doesn't implement them	2021-07-20 13:37:52 -04:00
bbracker	a1ea654b11	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-20 12:08:46 -04:00
David Harris	e1a1a8395e	Parameterized I$/D$ configurations and added sanity check assertions in testbench	2021-07-20 08:57:13 -04:00
bbracker	9e658466e6	testbench hack to ignore MTVAL for illegal instr faults; testbench upgrade to not check PCW for illegal instr faults; testbench hack to not check speculative instrs following an MRET (it seems MRET has 1 stage more latency than a branch instr)	2021-07-20 05:40:39 -04:00
bbracker	3b10ea9785	major fixes to CSR checking	2021-07-20 00:22:07 -04:00
bbracker	c1d63fe77c	MemRWM shouldn't factor into PCD checking	2021-07-19 18:03:30 -04:00
bbracker	f7d040af1e	make testbench ignore MIP because of timing imprecision and because QEMU maybe isn't getting MTIP right anyways	2021-07-19 17:11:42 -04:00
bbracker	65df5c087b	adapt testbench to removal of ReadDataWEn signal	2021-07-19 15:42:14 -04:00
bbracker	ae5663a244	adapt testbench to removal of signal	2021-07-19 15:41:50 -04:00
bbracker	cd469035be	make testbench check the same CSRs that QEMU logs; change CLINT to reset MTIMECMP to -1 so that we don't instantly get a timer interrupt upon reset	2021-07-19 15:13:03 -04:00
Katherine Parry	c9180f4ebd	FDIV and FSQRT passes when simulating in modelsim	2021-07-18 23:00:04 -04:00
bbracker	5e9dcb3f1c	linux testbench progress	2021-07-18 18:47:40 -04:00
Katherine Parry	60dabb9094	fdivsqrt inegrated, but not completley working	2021-07-18 14:03:37 -04:00
Ross Thompson	14220684b6	Fixed bug with rv32a/WALLY-LRSC test in imperas. Minor issue.	2021-07-17 21:02:24 -05:00
David Harris	8d348dacce	Started atomics	2021-07-17 21:11:41 -04:00
bbracker	82fc766819	swapped out linux testbench signal names	2021-07-17 14:48:12 -04:00
David Harris	87aa527de7	hptw: minor cleanup	2021-07-17 13:40:12 -04:00
David Harris	ef63e1ab52	hptw: factored pregen	2021-07-17 11:11:10 -04:00
David Harris	dac22d5016	Removed more unused signals from ahblite	2021-07-17 02:21:54 -04:00
Kip Macsai-Goren	d10fd25c33	included virtual memory tests in testbench	2021-07-16 17:57:24 -04:00
Ross Thompson	5e18a15a4c	Added guide for Ben to do linux conversion.	2021-07-16 15:04:30 -05:00
Ross Thompson	6521d2b468	Also changed the shadow ram's dcache copy widths. ... Merge branch 'dcache' into main	2021-07-16 14:21:09 -05:00
Ross Thompson	e5d624c1fa	Found bug in the PMA such that invalid addresses were sent to the tim. Once addressing this issue the sv48 test fails early with a pma access fault.	2021-07-15 11:56:35 -05:00
Ross Thompson	fa26aec588	Merge branch 'main' into dcache	2021-07-15 11:55:20 -05:00
Ross Thompson	b9902b0560	Fixed how the dcache and page table walker stall cpu so that once a tlb miss occurs the CPU is always stalled until the walk is complete, the tlb updated, and the dcache fetched and hits.	2021-07-15 11:00:42 -05:00
Ross Thompson	704f4f724e	dcache STATE_CPU_BUSY needs to assert CommittedM. This is required to ensure a completed memory operation is not bound to an interrupt. ie. MEPC should not be PCM when committed.	2021-07-14 23:08:07 -05:00
Ross Thompson	ba1e1ec231	Finally have the ptw correctly walking through the dcache to update the itlb. ... Still not working fully.	2021-07-14 22:26:07 -05:00
Katherine Parry	c74d26eea4	Fixed lint warning	2021-07-14 21:24:48 -04:00
Ross Thompson	2c946a282f	Fixed d cache not honoring StallW for uncache writes and reads.	2021-07-14 17:23:28 -05:00
Ross Thompson	e91501985c	Routed CommittedM and PendingInterruptM through the lsu arb.	2021-07-14 16:18:09 -05:00
Ross Thompson	3e57c899a2	Partially working changes to support uncached memory access. Not sure what CommitedM is.	2021-07-13 17:24:59 -05:00
Katherine Parry	efdec72df1	Fixed writting MStatus FS bits	2021-07-13 13:20:30 -04:00
Ross Thompson	3951eb56f5	Modularized the shadow memory to reduce performance hit.	2021-07-13 10:55:57 -05:00
Ross Thompson	e594eb540d	Got the shadow ram cache flush working.	2021-07-13 10:03:47 -05:00
Ross Thompson	49f6eec579	Team work on solving the dcache data inconsistency problem.	2021-07-12 23:46:32 -05:00
Ross Thompson	ecc9b5006e	Now updates the dtim with the dirty data in the dcache. ... Simulation is showing issues. It lookslike the cache is not evicting the correct data.	2021-07-12 15:13:27 -05:00
Ross Thompson	1cc258ade1	Progress towards the test bench flush.	2021-07-12 14:22:13 -05:00
Katherine Parry	36f59f3c99	Almost all convert instructions pass Imperas tests	2021-07-11 18:06:33 -04:00
bbracker	d3dd70e3e6	more completely uncomment MMU tests to make sim wally work	2021-07-06 14:33:52 -04:00
Kip Macsai-Goren	20cd0e208b	added new mmu tests to makefrag and commented out in the testbench	2021-07-05 10:54:30 -04:00