Ross Thompson
fed7042fd9
Loads are working.
...
There is a bug when the icache stalls 1 cycle before the d cache.
2021-07-10 22:15:44 -05:00
Ross Thompson
60ed023734
Actually writes the correct data now on stores.
2021-07-10 17:48:47 -05:00
Ross Thompson
efe37ea079
Write miss with eviction works.
2021-07-10 15:17:40 -05:00
Ross Thompson
d65c01bc29
Write Hits and Write Misses without eviction are working correctly! The next
...
step is to add eviction of dirty lines.
2021-07-10 10:56:25 -05:00
bbracker
feaeeaf6ac
greatly stripped down unused stuff in linux config
2021-07-10 11:53:35 -04:00
David Harris
20f2a4e47c
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-09 19:18:35 -04:00
David Harris
d3ab6b192a
added missing tlbmixer.sv
2021-07-09 19:18:23 -04:00
bbracker
3be73695e3
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-09 18:56:28 -04:00
bbracker
2a54f6f242
fix_mem.py bugfix
2021-07-09 18:56:17 -04:00
Ross Thompson
b1ceeb40df
Loads in modelsim, but the first store double does not function correctly. The write address is wrong so the cache is updated using the wrong address.
...
I think this is do to the cycle latency of stores. We probably need extra muxes to select between MemPAdrM and MemPAdrW depending on if the write is a
full cache block or a word write from the CPU.
2021-07-09 17:14:54 -05:00
bbracker
1f52a2f938
organize/update buildroot scripts for new image
2021-07-09 17:03:47 -04:00
Ross Thompson
4c0cee1c19
Design loads in modelsim, but trap is an X.
2021-07-09 15:37:16 -05:00
Ross Thompson
ec80cc1820
Lint passes, but I only hope to have loads working. Stores, lr/sc, atomic, are not fully implemented.
...
Also faults and the dcache ptw interlock are not implemented.
2021-07-09 15:16:38 -05:00
Kip Macsai-Goren
0dff489de2
comment clean up to match textbook chapter
2021-07-09 12:54:09 -04:00
David Harris
39bd7e7edc
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-09 07:53:30 -04:00
David Harris
5c2f774c35
Simplified tlbmixer mux to and-or
2021-07-08 23:34:24 -04:00
David Harris
74b6d13195
Fixed missing stall in InstrRet counter
2021-07-08 20:08:04 -04:00
bbracker
44a48cf28d
organize linux-testgen folder, add readme to describe Buildroot process, add Buildroot config source files
2021-07-08 19:18:11 -04:00
Ross Thompson
94c3fde724
Renamed signal in LSU toLSU and fromLSU to toDCache and fromDCache.
2021-07-08 18:03:52 -05:00
Ross Thompson
93aa39ca31
completed read miss branch through dcache fsm.
...
The challenge now is to connect to ahb and lsu.
2021-07-08 17:53:08 -05:00
David Harris
4f1a85ca7c
Eliminate reserved bits from TLB RAM
2021-07-08 17:35:00 -04:00
David Harris
38772de21f
Array of muxes in tlbmixer; abbreviated PPN and VPN to match diagram
2021-07-08 16:58:11 -04:00
David Harris
1190729896
TLB cleanup to match diagrams
2021-07-08 16:52:06 -04:00
Ross Thompson
910ddb83ae
This d cache fsm is getting complex.
2021-07-08 15:26:16 -05:00
Ross Thompson
1fe06bc670
Partial implementation of the data cache. Missing the fsm.
2021-07-07 17:52:16 -05:00
David Harris
5d5274ec73
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-07 06:32:29 -04:00
David Harris
2bab3f769b
Renamed tlb ReadLines to Matches
2021-07-07 06:32:26 -04:00
Abe
84711fbdc8
Updated MISA defining as well as porting sizes for peripherals (34 to 56)
2021-07-07 02:37:09 -04:00
Abe
c721341691
Commented out printf statements for quicker simulation time. Also added function minstretDiff, which calculates the number of machine instructions retired during the coremark benchmark's runtime, excluding setup time.
2021-07-07 02:28:11 -04:00
Abe
b536065ee8
Removed debugging loop to test timers for clarity
2021-07-06 23:37:43 -04:00
Abe
8dc40e988e
Updated portme file to include counters MTIME and MINSTRET. Timer currently set to read milliseconds running at 100MHZ, but this can be changed by setting a different clock speed in the testbench sv file and manipulating TIMER_RES_DIVIDER on line 120
2021-07-06 23:35:47 -04:00
Abe
b757c96b2d
Changed SvMode to SVMode on line 76
2021-07-06 23:28:58 -04:00
David Harris
af619dcd75
Added ASID matching for CAM
2021-07-06 18:56:25 -04:00
Kip Macsai-Goren
8350622f65
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-06 18:54:41 -04:00
David Harris
7d857cf4bd
more TLB name touchups
2021-07-06 18:39:30 -04:00
Kip Macsai-Goren
e08a578908
fixed upper bits page fault signal
2021-07-06 18:32:47 -04:00
David Harris
2e2aa2a972
connected signals in tlb by name instead of .*
2021-07-06 17:22:10 -04:00
David Harris
ee3a321002
changed tlbphysicalpagemask to structural
2021-07-06 17:16:58 -04:00
David Harris
f960561cbb
changed tlbphysicalpagemask to structural
2021-07-06 17:08:04 -04:00
David Harris
fd0cd930a7
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-06 15:29:49 -04:00
David Harris
032c38b7e7
MMU produces page fault when upper bits aren't equal. Renamed input to MMU to be 'Address' and moved translation mux into MMU out of TLB
2021-07-06 15:29:42 -04:00
Kip Macsai-Goren
757e4f3b54
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-06 15:05:51 -04:00
Ross Thompson
412691df2d
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-06 13:45:20 -05:00
Ross Thompson
3345ed7ff4
Merged several of the load/store/instruction access faults inside the mmu.
...
Still need to figure out what is wrong with the generation of load page fault when dtlb hit.
2021-07-06 13:43:53 -05:00
bbracker
d3dd70e3e6
more completely uncomment MMU tests to make sim wally work
2021-07-06 14:33:52 -04:00
Kip Macsai-Goren
137145144f
edited tests so regression would pass with float enabled. this IS NOT a comprehensive test for fs yet
2021-07-06 14:28:26 -04:00
Abe
8854532a79
Disabled MCOUNTINHIBIT to enable csr counters (changed to 32'h0 on line 140)
2021-07-06 12:37:58 -04:00
Ross Thompson
7af8cfba18
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-06 10:41:45 -05:00
Ross Thompson
6e7e318396
Fixed bug in the LSU pagetable walker interlock.
2021-07-06 10:41:36 -05:00
David Harris
b4082ba776
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-06 10:44:17 -04:00
