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Configurable RISC-V Processor
1,240 Commits 14 Branches 1 Tag 31 MiB
Assembly 55.4%
C 27.2%
SystemVerilog 8.2%
Python 2.7%
Stata 2.3%
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Kip Macsai-Goren 0dff489de2 comment clean up to match textbook chapter
2021-07-09 12:54:09 -04:00
riscv-coremark Commented out printf statements for quicker simulation time. Also added function minstretDiff, which calculates the number of machine instructions retired during the coremark benchmark's runtime, excluding setup time. 2021-07-07 02:28:11 -04:00
testsBP Added special tests for checking the accuracy of global and gshare branch 2021-06-04 11:01:54 -05:00
wally-pipelined Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-09 07:53:30 -04:00
.gitattributes moved shared constants to a shared directory 2021-06-03 22:41:30 -04:00
.gitignore organize linux-testgen folder, add readme to describe Buildroot process, add Buildroot config source files 2021-07-08 19:18:11 -04:00
.gitmodules Flow updated for 90nm 2021-07-01 13:32:42 -05:00
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README.md

README.md

riscv-wally

Configurable RISC-V Processor