Ross Thompson
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698afb0e79
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-07-16 15:04:38 -05:00 |
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Ross Thompson
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5e18a15a4c
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Added guide for Ben to do linux conversion.
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2021-07-16 15:04:30 -05:00 |
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Kip Macsai-Goren
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70fa6bca8e
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removed exectution tests that intentionally fail as well until fences are implemented.
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2021-07-16 15:47:08 -04:00 |
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Kip Macsai-Goren
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6c21c7903a
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removed execution tests that are supposed to pass until fences are implemented.
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2021-07-16 15:32:13 -04:00 |
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Ross Thompson
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6521d2b468
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Also changed the shadow ram's dcache copy widths.
Merge branch 'dcache' into main
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2021-07-16 14:21:09 -05:00 |
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Ross Thompson
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1aabee0478
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Updated the config so the tim has a bigger range.
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2021-07-16 12:35:00 -05:00 |
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Ross Thompson
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b3bf04d474
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Updated wave file.
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2021-07-16 12:34:37 -05:00 |
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Ross Thompson
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46bce70e42
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Fixed walker fault interaction with dcache.
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2021-07-16 12:22:13 -05:00 |
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bbracker
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b0fcfc2773
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reduce number of UART ports to 1
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2021-07-16 12:42:29 -04:00 |
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bbracker
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f9d9d348d6
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-16 12:27:25 -04:00 |
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bbracker
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01ca22af49
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changed stop of linux boot from arch_cpu_idle to do_idle
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2021-07-16 12:27:15 -04:00 |
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Ross Thompson
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e0f719d513
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Updated the ptw, lsuarb and dcache to hopefully solve the interlock issues.
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2021-07-16 11:12:57 -05:00 |
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bbracker
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ae7d48c326
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incremental linux config de-bloating
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2021-07-16 12:08:58 -04:00 |
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bbracker
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40352ab7e4
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incremental linux config de-bloating
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2021-07-16 11:33:11 -04:00 |
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bbracker
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b1fe4ff295
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incremental linux config de-bloating
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2021-07-16 11:15:25 -04:00 |
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bbracker
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f34e28d187
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incremental linux config de-bloating
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2021-07-16 01:58:21 -04:00 |
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bbracker
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3bcc5808d4
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incremental linux config de-bloating
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2021-07-16 01:54:36 -04:00 |
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bbracker
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ff90e6744c
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incremental linux config de-bloating
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2021-07-16 01:43:16 -04:00 |
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bbracker
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ca5a1755f3
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incremental linux config de-bloating
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2021-07-16 01:33:51 -04:00 |
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bbracker
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b003c651be
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incremental linux config de-bloating
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2021-07-16 01:25:41 -04:00 |
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bbracker
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ae886b015d
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incremental linux config de-bloating
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2021-07-16 01:00:12 -04:00 |
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bbracker
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7340e089f7
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incremental linux config de-bloating
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2021-07-16 00:46:22 -04:00 |
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bbracker
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c4716af4d6
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incremental linux config de-bloating
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2021-07-16 00:41:18 -04:00 |
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bbracker
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0238b869fb
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incremental linux config de-bloating
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2021-07-16 00:34:41 -04:00 |
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bbracker
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3273b030e1
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incremental linux config de-bloating
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2021-07-16 00:16:12 -04:00 |
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bbracker
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66bf2005fe
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incremental linux config de-bloating
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2021-07-16 00:10:31 -04:00 |
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bbracker
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4734f0eee5
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incremental linux config de-bloating
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2021-07-15 23:53:15 -04:00 |
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bbracker
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e565adfece
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incremental linux config de-bloating
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2021-07-15 23:30:24 -04:00 |
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bbracker
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3ff723493f
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incremental linux config de-bloating
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2021-07-15 23:12:21 -04:00 |
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bbracker
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8586462ee5
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incremental linux config de-bloating
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2021-07-15 23:00:20 -04:00 |
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bbracker
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03e0bdaa5a
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incremental linux config de-bloating
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2021-07-15 21:33:52 -04:00 |
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bbracker
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e922732fc5
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incremental linux config de-bloating
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2021-07-15 20:54:36 -04:00 |
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Kip Macsai-Goren
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ca63f6bc48
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fixed output file to match sv48 test again
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2021-07-15 18:55:00 -04:00 |
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bbracker
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c2535308fd
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working linux config
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2021-07-15 18:49:54 -04:00 |
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Kip Macsai-Goren
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473ed689a2
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fixed another address to be in tim range
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2021-07-15 18:31:53 -04:00 |
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Kip Macsai-Goren
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abd5b1c02d
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Still broken, midway through fixing understanding of how ptw and datacache interact in time especially wrt adrE, adrM, faults, and tlb interaction.
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2021-07-15 18:30:29 -04:00 |
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bbracker
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3b6291b734
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stripped down busybox a bit
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2021-07-15 16:07:56 -04:00 |
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Kip Macsai-Goren
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9aedfafb3c
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modified sv48 test to only read or write from physical addresses located in the dtim range from 0x80000000 to 0x87FFFFFF
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2021-07-15 14:01:29 -04:00 |
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Ross Thompson
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e5d624c1fa
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Found bug in the PMA such that invalid addresses were sent to the tim. Once addressing this issue the sv48 test fails early with a pma access fault.
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2021-07-15 11:56:35 -05:00 |
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Ross Thompson
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fa26aec588
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Merge branch 'main' into dcache
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2021-07-15 11:55:20 -05:00 |
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Ross Thompson
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fd1de6b047
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Updated wave file.
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2021-07-15 11:04:49 -05:00 |
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Ross Thompson
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b9902b0560
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Fixed how the dcache and page table walker stall cpu so that once a tlb miss occurs the CPU is always stalled until the walk is complete, the tlb updated, and the dcache fetched and hits.
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2021-07-15 11:00:42 -05:00 |
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Ross Thompson
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8610ef204c
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Renamed DCacheStall to LSUStall in hart and hazard.
Added missing logic in lsu.
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2021-07-15 10:16:16 -05:00 |
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Kip Macsai-Goren
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74e67df080
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-15 10:52:39 -04:00 |
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Ross Thompson
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704f4f724e
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dcache STATE_CPU_BUSY needs to assert CommittedM. This is required to ensure a completed memory operation is not bound to an interrupt. ie. MEPC should not be PCM when committed.
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2021-07-14 23:08:07 -05:00 |
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Ross Thompson
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ba1e1ec231
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Finally have the ptw correctly walking through the dcache to update the itlb.
Still not working fully.
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2021-07-14 22:26:07 -05:00 |
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Katherine Parry
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c74d26eea4
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Fixed lint warning
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2021-07-14 21:24:48 -04:00 |
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Ross Thompson
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c79650b508
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Added d cache StallW checks for any time the cache wants to go to STATE_READY.
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2021-07-14 17:25:50 -05:00 |
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Ross Thompson
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2c946a282f
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Fixed d cache not honoring StallW for uncache writes and reads.
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2021-07-14 17:23:28 -05:00 |
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Katherine Parry
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f5bfdf46db
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fpu unpacking unit created
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2021-07-14 17:56:49 -04:00 |
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