David Harris
654abcde61
Replaced MDUE with IntDivE in FDIVSQRT
2023-01-11 11:06:37 -08:00
David Harris
446b5fa83f
Division constant cleanup
2023-01-10 11:14:59 -08:00
David Harris
4a34007b49
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2023-01-09 13:04:37 -08:00
David Harris
b2ec52c94d
Changed DIVN from NF+3 to NF+2, cleanup
2023-01-09 13:04:34 -08:00
Ross Thompson
f330d877ac
Added folded gshare predictor with k=16 and depth=10.
2023-01-09 14:41:03 -06:00
David Harris
48f31d4b24
Divider constant cleanup, made CORRSHIFTSZ consistent
2023-01-09 12:34:19 -08:00
Ross Thompson
302a2e0116
Added better branch predictor to fpga config.
2023-01-09 13:46:30 -06:00
Ross Thompson
ca55bd8444
Fixed branch predictor.
2023-01-09 13:45:49 -06:00
Ross Thompson
6a616617d1
Restored to default configuration.
2023-01-09 00:21:45 -06:00
Ross Thompson
6326e6984c
Might have actually solved the gshare bug.
2023-01-09 00:11:25 -06:00
Ross Thompson
0eda4b1ab3
core part of global history works now. forwarding is still broken.
2023-01-08 23:35:02 -06:00
Ross Thompson
475becb414
Removed unused rv64BP config.
2023-01-07 12:17:40 -06:00
David Harris
c260354817
Removed unused UARCH configuration entries
2023-01-06 05:11:14 -08:00
Ross Thompson
78e441fb38
More branch predictor cleanup.
2023-01-05 17:19:27 -06:00
Ross Thompson
65dd86b726
Keep around the old gshare.
2023-01-05 15:55:46 -06:00
Ross Thompson
2224679694
Added speculative gshare.
2023-01-05 14:18:00 -06:00
Ross Thompson
9d03109f34
Officially added global history with speculation to types of branch predictors.
2023-01-05 14:04:09 -06:00
Ross Thompson
14ebf2360d
Simplified gshare.
2023-01-04 23:51:09 -06:00
Ross Thompson
0eceeeeeaa
Simiplified global history branch predictor.
2023-01-04 23:41:55 -06:00
David Harris
f8af51e07b
Handle special case Int Div/Rem of |A| < |B| in a single cycle
2023-01-01 13:54:01 -08:00
David Harris
7c7d40ad63
Broken commit starting to address radix 2 issues
2022-12-31 06:19:15 -08:00
David Harris
50af122909
Moved shared config so wally-shared only has values a user would alter
2022-12-31 05:51:42 -08:00
David Harris
6832b9d9f6
config file, comment, postproc cleanup
2022-12-31 05:20:56 -08:00
Cedar Turek
0836d4d4f0
removed unnecessary values from shared config. unbroke division
2022-12-30 21:26:55 -08:00
Katherine Parry
aca6f0d4e6
removed ethe second bit from fma alignment shift
2022-12-30 12:07:44 -06:00
Katherine Parry
5844a596a3
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-12-30 09:56:35 -06:00
David Harris
ba976d66e4
Radix 4 divsqrt
2022-12-30 07:01:44 -08:00
Ross Thompson
c725b5534a
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
2022-12-29 17:07:53 -06:00
Ross Thompson
654b10894c
Re-enabled the branch predictor in rv64gc.
2022-12-29 17:07:50 -06:00
Katherine Parry
1b4fa38510
one bitt removed from inital lignment shift
2022-12-28 17:46:53 -06:00
Cedar Turek
4ed2c6255c
idiv passing radix 2, four copies
2022-12-27 22:10:48 -08:00
Cedar Turek
f48b7d7ef9
fpu idiv working on all configs with 1 copy of radix 2!
2022-12-26 23:18:28 -08:00
David Harris
2de66e9eef
Moved fdivsqrtexpcalc to its own file
2022-12-26 08:45:43 -08:00
cturek
ccbad67497
Added negative-result int diviison support in U and UM registers. 13 tests pass!
2022-12-22 16:25:37 +00:00
David Harris
e4579f3e9b
Removed CSR support from rv32i
2022-12-19 16:15:12 -08:00
Alessandro Maiuolo
2989782fe6
fixed LOGRK. FIxed Xs in WC and WS from muxes reliant on SqrtE. note not linting on 4 copies radix 4 because IntBits only 7 bits wide (need 8)
2022-12-18 19:04:36 -08:00
David Harris
2457448e29
Renamed DIV_BITSPERCYCLE to IDIV_BITSPERCYCLE
2022-12-15 08:23:34 -08:00
David Harris
33aca5d35e
Added IDIV_ON_FPU flag to control whether integer division uses FPU
2022-12-15 06:37:55 -08:00
Ross Thompson
f9ffcf377b
Reverted the IROM/DTIM address range modelsim assignment.
2022-11-30 17:13:33 -06:00
cturek
9c70ab917c
Added A<B signal to fdivsqrt, started postprocessing merge
2022-11-13 22:40:26 +00:00
cturek
1e927df1a0
Added conditional OTFC swap for simplified int postprocessing
2022-11-06 23:09:09 +00:00
cturek
7567f388c2
Changed lzc names, started int/fp size merge in preproc
2022-11-06 22:21:35 +00:00
cturek
b893d9249d
Added new macros for int div preprocessing, added p, n, and rightshiftx logic
2022-11-06 21:53:48 +00:00
cturek
2ae0a9bb5d
Config Cleanup
2022-10-27 22:38:56 +00:00
cturek
a8a89f8dfc
unbroke DIVb
2022-10-26 16:11:51 +00:00
cturek
8475de128b
Config cleanup
2022-10-25 21:04:09 +00:00
Ross Thompson
403daecc8e
Modified the do scripts to change the DTIM_RANGE and IROM_RANGE to large values from the defaults.
...
The defaults are used for synthesis.
rv64i and rv32i: DTIM 2KiB, IROM 2KiB
rv32ic: DTIM 4KiB, IROM 16KiB
Regression tests require 8MiB or larger so modelsim overrides.
2022-10-11 10:47:13 -05:00
David Harris
e4c5754b3a
Made simple RV64 configuration be RV64i. Eliminated rv64ic and rv64fp. Fixed some bugs related to new width
2022-10-10 09:10:55 -07:00
Ross Thompson
b52f593ecb
Reorganized the configs.
2022-10-09 16:46:48 -05:00
David Harris
f318daa605
Changed RV32i config to use DTIM and bus. Don't use this commit - it will break rv32i tests.
2022-10-05 11:46:52 -07:00
