2022-09-07 13:12:23 +00:00
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///////////////////////////////////////////
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// fdivsqrtpostproc.sv
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//
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2022-09-19 21:26:32 +00:00
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// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
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2022-09-07 13:12:23 +00:00
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// Modified:13 January 2022
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//
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// Purpose: Combined Divide and Square Root Floating Point and Integer Unit
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module fdivsqrtpostproc(
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input logic clk, reset,
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input logic StallM,
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input logic [`DIVb+3:0] WS, WC,
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input logic [`DIVb-1:0] D,
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input logic [`DIVb:0] FirstU, FirstUM,
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input logic [`DIVb+1:0] FirstC,
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2022-12-27 18:42:40 +00:00
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input logic SqrtE,
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input logic Firstun, SqrtM, SpecialCaseM, NegQuotM,
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input logic [`XLEN-1:0] AM,
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input logic RemOpM, ALTBM, BZeroM, AsM, W64M,
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input logic [`DIVBLEN:0] nM, mM,
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output logic [`DIVb:0] QmM,
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output logic WZeroE,
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output logic DivSM,
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output logic [`XLEN-1:0] FPIntDivResultM
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);
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2022-12-24 06:46:52 +00:00
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logic [`DIVb+3:0] W, Sum, DM;
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logic [`DIVb:0] PreQmM;
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logic NegStickyM;
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logic weq0E, weq0M, WZeroM;
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logic signed [`DIVb+3:0] PreResultM, PreFPIntDivResultM;
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logic [`XLEN-1:0] SpecialFPIntDivResultM;
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//////////////////////////
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// Execute Stage: Detect early termination for an exact result
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//////////////////////////
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// check for early termination on an exact result.
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aplusbeq0 #(`DIVb+4) wspluswceq0(WS, WC, weq0E);
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if (`RADIX == 2) begin: R2EarlyTerm
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logic [`DIVb+3:0] FZeroE, FZeroSqrtE, FZeroDivE;
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logic [`DIVb+2:0] FirstK;
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logic wfeq0E;
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logic [`DIVb+3:0] WCF, WSF;
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assign FirstK = ({1'b1, FirstC} & ~({1'b1, FirstC} << 1));
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assign FZeroSqrtE = {FirstUM[`DIVb], FirstUM, 2'b0} | {FirstK,1'b0}; // F for square root
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assign FZeroDivE = {3'b001,D,1'b0}; // F for divide
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mux2 #(`DIVb+4) fzeromux(FZeroDivE, FZeroSqrtE, SqrtE, FZeroE);
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csa #(`DIVb+4) fadd(WS, WC, FZeroE, 1'b0, WSF, WCF); // compute {WCF, WSF} = {WS + WC + FZero};
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aplusbeq0 #(`DIVb+4) wcfpluswsfeq0(WCF, WSF, wfeq0E);
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assign WZeroE = weq0E|(wfeq0E & Firstun);
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end else begin
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assign WZeroE = weq0E;
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end
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//////////////////////////
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// E/M Pipeline register
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//////////////////////////
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flopenr #(1) WZeroMReg(clk, reset, ~StallM, WZeroE, WZeroM);
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flopenr #(1) WeqZeroMReg(clk, reset, ~StallM, weq0E, weq0M);
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//////////////////////////
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// Memory Stage: Postprocessing
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//////////////////////////
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// If the result is not exact, the sticky should be set
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assign DivSM = ~WZeroM & ~(SpecialCaseM & SqrtM); // ***unsure why SpecialCaseM has to be gated by SqrtM, but otherwise fails regression on divide
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2022-12-27 18:27:07 +00:00
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// Determine if sticky bit is negative // *** look for ways to optimize this. Shift shouldn't be needed.
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assign Sum = WC + WS;
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assign NegStickyM = Sum[`DIVb+3];
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mux2 #(`DIVb+1) preqmmux(FirstU, FirstUM, NegStickyM, PreQmM);// Select U or U-1 depending on negative sticky bit
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mux2 #(`DIVb+1) qmmux(PreQmM, (PreQmM << 1), SqrtM, QmM);
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2022-12-30 22:31:23 +00:00
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if (`IDIV_ON_FPU) begin // Int supported
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logic [`DIVBLEN:0] NormShiftM;
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logic [`DIVb+3:0] IntQuotM, IntRemM, NormRemM, NormRemDM;
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2022-12-28 06:02:14 +00:00
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assign W = $signed(Sum) >>> `LOGR;
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assign DM = {4'b0001, D};
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2022-12-30 15:17:38 +00:00
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// Integer remainder: sticky and sign correction muxes
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mux2 #(`DIVb+4) normremdmux(W, W+DM, NegStickyM, NormRemDM);
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mux2 #(`DIVb+4) normremsmux(NormRemDM, -NormRemDM, AsM, NormRemM);
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// special case logic
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always_comb
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if (BZeroM) begin // Divide by zero
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if (RemOpM) SpecialFPIntDivResultM = AM;
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else SpecialFPIntDivResultM = {(`XLEN){1'b1}};
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end else if (ALTBM) begin // Numerator is zero
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if (RemOpM) SpecialFPIntDivResultM = AM;
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else SpecialFPIntDivResultM = '0;
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end else begin
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logic [`DIVb+3:0] PreIntQuotM;
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if (WZeroM) begin
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if (weq0M) begin
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PreIntQuotM = {3'b000, FirstU};
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IntRemM = '0;
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end else begin
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PreIntQuotM = {3'b000, FirstUM};
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IntRemM = '0;
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end
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end else begin
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PreIntQuotM = {3'b000, PreQmM};
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IntRemM = NormRemM;
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end
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// flip sign if necessary
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if (NegQuotM) IntQuotM = -PreIntQuotM;
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else IntQuotM = PreIntQuotM;
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if (RemOpM) begin
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NormShiftM = ALTBM ? 0 : (mM + (`DIVBLEN+1)'(`DIVa)); // no postshift if forwarding input A to remainder
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PreResultM = IntRemM;
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end else begin
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NormShiftM = ((`DIVBLEN+1)'(`DIVb) - (nM * (`DIVBLEN+1)'(`LOGR)));
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PreResultM = IntQuotM;
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end
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PreFPIntDivResultM = $signed(PreResultM >>> NormShiftM);
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SpecialFPIntDivResultM = PreFPIntDivResultM[`XLEN-1:0];
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end
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2022-12-30 14:40:25 +00:00
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// sign extend result for W64
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if (`XLEN==64) begin
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mux2 #(64) resmux(SpecialFPIntDivResultM[`XLEN-1:0],
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{{(`XLEN-32){SpecialFPIntDivResultM[31]}}, SpecialFPIntDivResultM[31:0]}, // Sign extending in case of W64
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W64M, FPIntDivResultM);
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end else
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assign FPIntDivResultM = SpecialFPIntDivResultM[`XLEN-1:0];
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end
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endmodule
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