forked from Github_Repos/cvw
62 lines
2.4 KiB
Systemverilog
62 lines
2.4 KiB
Systemverilog
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///////////////////////////////////////////
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// fdivsqrtpostproc.sv
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//
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// Written: David_Harris@hmc.edu, me@KatherineParry.com, Cedar Turek
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// Modified:13 January 2022
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//
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// Purpose: Combined Divide and Square Root Floating Point and Integer Unit
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module fdivsqrtpostproc(
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input logic clk,
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input logic reset,
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input logic DivStart,
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input logic [`DIVb+3:0] NextWSN, NextWCN, WS, WC,
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/* input logic XInfE, YInfE,
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input logic XZeroE, YZeroE,
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input logic XNaNE, YNaNE,
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input logic XsE,
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input logic SqrtE,
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input logic SqrtM,
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input logic StallE,
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input logic StallM,*/
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input logic [`DIVN-2:0] D, // U0.N-1
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input logic [`DIVb+3:0] StickyWSA,
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input logic [`DURLEN-1:0] Dur,
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input logic [`DIVb:0] LastSM,
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input logic [`DIVb:0] FirstSM,
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input logic [`DIVb-1:0] LastC,
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input logic [`DIVb-1:0] FirstC,
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input logic [`DIVCOPIES-1:0] qn,
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// output logic [`DURLEN-1:0] EarlyTermShiftE,
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output logic DivSE,
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// output logic DivDone,
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output logic NegSticky,
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output logic DivBusy
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);
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endmodule
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