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///////////////////////////////////////////
// fdivsqrtpostproc.sv
//
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// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
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// Modified:13 January 2022
//
// Purpose: Combined Divide and Square Root Floating Point and Integer Unit
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// MIT LICENSE
// Permission is hereby granted, free of charge, to any person obtaining a copy of this
// software and associated documentation files (the "Software"), to deal in the Software
// without restriction, including without limitation the rights to use, copy, modify, merge,
// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
// to whom the Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or
// substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
// OR OTHER DEALINGS IN THE SOFTWARE.
////////////////////////////////////////////////////////////////////////////////////////////////
`include " wally-config.vh "
module fdivsqrtpostproc (
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input logic clk , reset ,
input logic StallM ,
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input logic [ `DIVb + 3 : 0 ] WS , WC ,
input logic [ `DIVb - 1 : 0 ] D ,
input logic [ `DIVb : 0 ] FirstU , FirstUM ,
input logic [ `DIVb + 1 : 0 ] FirstC ,
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input logic SqrtE , MDUE ,
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input logic Firstun , SqrtM , SpecialCaseM , NegQuotM ,
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input logic [ `XLEN - 1 : 0 ] ForwardedSrcAM ,
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input logic RemOpM , ALTBM , BZeroM , AsM , W64M ,
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input logic [ `DIVBLEN : 0 ] nM , mM ,
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output logic [ `DIVb : 0 ] QmM ,
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output logic WZeroE ,
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output logic DivSM ,
output logic [ `XLEN - 1 : 0 ] FPIntDivResultM
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) ;
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logic [ `DIVb + 3 : 0 ] W , Sum , DM ;
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logic [ `DIVb : 0 ] PreQmM ;
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logic NegStickyM ;
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logic weq0E , weq0M , WZeroM ;
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logic [ `DIVBLEN : 0 ] NormShiftM ;
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logic [ `DIVb : 0 ] NormQuotM ;
logic [ `DIVb + 3 : 0 ] IntQuotM , IntRemM , NormRemM ;
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logic signed [ `DIVb + 3 : 0 ] PreResultM , PreFPIntDivResultM ;
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logic [ `XLEN - 1 : 0 ] SpecialFPIntDivResultM ;
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//////////////////////////
// Execute Stage: Detect early termination for an exact result
//////////////////////////
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// check for early termination on an exact result.
aplusbeq0 # ( `DIVb + 4 ) wspluswceq0 ( WS , WC , weq0E ) ;
if ( `RADIX = = 2 ) begin : R2EarlyTerm
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logic [ `DIVb + 3 : 0 ] FZeroE , FZeroSqrtE , FZeroDivE ;
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logic [ `DIVb + 2 : 0 ] FirstK ;
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logic wfeq0E ;
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logic [ `DIVb + 3 : 0 ] WCF , WSF ;
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assign FirstK = ( { 1 'b1 , FirstC } & ~ ( { 1 'b1 , FirstC } < < 1 ) ) ;
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assign FZeroSqrtE = { FirstUM [ `DIVb ] , FirstUM , 2 'b0 } | { FirstK , 1 'b0 } ; // F for square root
assign FZeroDivE = { 3 'b001 , D , 1 'b0 } ; // F for divide
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mux2 # ( `DIVb + 4 ) fzeromux ( FZeroDivE , FZeroSqrtE , SqrtE , FZeroE ) ;
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csa # ( `DIVb + 4 ) fadd ( WS , WC , FZeroE , 1 'b0 , WSF , WCF ) ; // compute {WCF, WSF} = {WS + WC + FZero};
aplusbeq0 # ( `DIVb + 4 ) wcfpluswsfeq0 ( WCF , WSF , wfeq0E ) ;
assign WZeroE = weq0E | ( wfeq0E & Firstun ) ;
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end else begin
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assign WZeroE = weq0E ;
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end
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//////////////////////////
// E/M Pipeline register
//////////////////////////
flopenr # ( 1 ) WZeroMReg ( clk , reset , ~ StallM , WZeroE , WZeroM ) ;
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flopenr # ( 1 ) WeqZeroMReg ( clk , reset , ~ StallM , weq0E , weq0M ) ;
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//////////////////////////
// Memory Stage: Postprocessing
//////////////////////////
// If the result is not exact, the sticky should be set
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assign DivSM = ~ WZeroM & ~ ( SpecialCaseM & SqrtM ) ; // ***unsure why SpecialCaseM has to be gated by SqrtM, but otherwise fails regression on divide
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// Determine if sticky bit is negative // *** look for ways to optimize this. Shift shouldn't be needed.
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assign Sum = WC + WS ;
assign W = $signed ( Sum ) > > > `LOGR ;
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assign NegStickyM = W [ `DIVb + 3 ] ;
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assign DM = { 4 'b0001 , D } ;
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// *** put conditionals on integer division hardware, move to its own module
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// Integer division: sign handling for div and rem
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always_comb
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if ( ~ AsM )
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if ( NegStickyM ) begin
NormQuotM = FirstUM ;
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NormRemM = W + DM ;
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end else begin
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NormQuotM = FirstU ;
NormRemM = W ;
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end
else
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if ( NegStickyM ) begin
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NormQuotM = FirstUM ;
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NormRemM = - ( W + DM ) ;
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end else begin
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NormQuotM = FirstU ;
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NormRemM = - W ;
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end
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// Integer division: Special cases
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always_comb
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if ( ALTBM ) begin
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IntQuotM = '0 ;
IntRemM = { { ( `DIVb - `XLEN + 4 ) { 1 'b0 } } , ForwardedSrcAM } ;
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end else begin
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logic [ `DIVb + 3 : 0 ] PreIntQuotM ;
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if ( WZeroM ) begin
if ( weq0M ) begin
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PreIntQuotM = { 3 'b000 , FirstU } ;
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IntRemM = '0 ;
end else begin
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PreIntQuotM = { 3 'b000 , FirstUM } ;
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IntRemM = '0 ;
end
end else begin
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PreIntQuotM = { 3 'b000 , NormQuotM } ;
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IntRemM = NormRemM ;
end
// flip sign if necessary
if ( NegQuotM ) IntQuotM = - PreIntQuotM ;
else IntQuotM = PreIntQuotM ;
end
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always_comb
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if ( RemOpM ) begin
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NormShiftM = ALTBM ? '0 : ( mM + ( `DIVBLEN + 1 ) ' ( `DIVa ) ) ; // no postshift if forwarding input A to remainder
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PreResultM = IntRemM ;
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end else begin
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NormShiftM = ( ( `DIVBLEN + 1 ) ' ( `DIVb ) - ( nM * ( `DIVBLEN + 1 ) ' ( `LOGR ) ) ) ;
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PreResultM = IntQuotM ;
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/ *
if ( ~ ALTBM & NegQuotM ) begin
PreResultM = { 3 'b111 , - IntQuotM } ;
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end else begin
PreResultM = { 3 'b000 , IntQuotM } ;
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end */
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//PreResultM = {IntQuotM[`DIVb], IntQuotM[`DIVb], IntQuotM[`DIVb], IntQuotM}; // Suspicious Sign Extender
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end
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// division takes the result from the next cycle, which is shifted to the left one more time so the square root also needs to be shifted
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assign PreFPIntDivResultM = $signed ( PreResultM > > > NormShiftM ) ;
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assign SpecialFPIntDivResultM = BZeroM ? ( RemOpM ? ForwardedSrcAM : { ( `XLEN ) { 1 'b1 } } ) : PreFPIntDivResultM [ `XLEN - 1 : 0 ] ; // special cases
// *** conditional on RV64
assign FPIntDivResultM = ( W64M ? { { ( `XLEN - 32 ) { SpecialFPIntDivResultM [ 31 ] } } , SpecialFPIntDivResultM [ 31 : 0 ] } : SpecialFPIntDivResultM [ `XLEN - 1 : 0 ] ) ; // Sign extending in case of W64
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assign PreQmM = NegStickyM ? FirstUM : FirstU ; // Select U or U-1 depending on negative sticky bit
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assign QmM = SqrtM ? ( PreQmM < < 1 ) : PreQmM ;
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endmodule