Jarred Allen
2269879459
Merge branch 'main' into cache
2021-03-22 13:47:48 -04:00
bbracker
eea7e2e47e
first pass at PLIC interface
2021-03-22 10:14:21 -04:00
Katherine Parry
9af0ad815c
fixed various bugs in the FMA
2021-03-21 22:53:04 +00:00
Jarred Allen
bab0e3b90f
Change busybear testbench to reflect new location of InstrF
2021-03-20 18:20:27 -04:00
Jarred Allen
e32291bcc2
Put Imperas testbench back
2021-03-20 18:19:51 -04:00
Jarred Allen
066dc2caac
Fix bug with PC incrementing
2021-03-20 18:06:03 -04:00
Jarred Allen
e531a1b5ee
Merge branch 'main' into cache
2021-03-20 17:56:25 -04:00
Jarred Allen
665c244ba1
Fix another bug in the icache (why so many of them?)
2021-03-20 17:54:40 -04:00
Jarred Allen
43a8cb0354
Revert "Change flop to listen to StallF"
...
This reverts commit f069b759be
2021-03-20 17:34:19 -04:00
Jarred Allen
639a718312
Fix conflicts in ahb-waves that snuck through manual merging
2021-03-20 17:16:50 -04:00
Jarred Allen
f069b759be
Change flop to listen to StallF
2021-03-20 17:04:13 -04:00
Katherine Parry
fd381e60d7
messy FMA rewrite using section 7.5.4 in The Handbook of Floating-Point Arithmetic
2021-03-20 02:05:16 +00:00
Jarred Allen
50c961bbe4
Merge changes from main
2021-03-18 18:58:10 -04:00
Jarred Allen
bf2fbf49ee
Add icache's read request to ahb wavs
2021-03-18 18:52:03 -04:00
bbracker
df51d9908d
AHB bugfixes and sim waveview refactoring
2021-03-18 18:25:12 -04:00
bbracker
11ba96f2e3
maybe AHB works now
2021-03-18 17:47:00 -04:00
Shreya Sanghai
804407eab7
fixed minor bugs in testbench
2021-03-18 17:37:10 -04:00
Shreya Sanghai
dfc86539cc
Merge branch 'gshare' into main
...
Conflicts:
wally-pipelined/regression/wave.do
2021-03-18 17:25:48 -04:00
Ross Thompson
9386e6a524
Switched to gshare from global history.
...
Fixed a few minor bugs.
2021-03-18 16:05:59 -05:00
Ross Thompson
181a28e875
Fixed minor bug with the size of gshare.
2021-03-18 16:00:09 -05:00
Shreya Sanghai
f35d3b39c8
removed unnecesary PC registers in ifu
2021-03-18 16:31:21 -04:00
Thomas Fleming
859d242d81
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-03-18 14:36:42 -04:00
Thomas Fleming
062c4d40da
Connect tlb, pagetablewalker, and memory
2021-03-18 14:35:46 -04:00
Thomas Fleming
f04e554e35
Improve page table creation in python file
2021-03-18 14:27:09 -04:00
Noah Boorstin
847bf0b9a6
change ifndef to generate/if
2021-03-18 12:50:19 -04:00
Noah Boorstin
fa1407f6e3
everyone gets a bootram
2021-03-18 12:35:37 -04:00
Noah Boorstin
a226e24ed3
busybear: update memory map, add GPIO
2021-03-18 12:17:35 -04:00
Teo Ene
0ff785549e
Switched coremark to RV64IM
2021-03-17 22:39:56 -05:00
Teo Ene
db164462ed
adapted coremark bare testbench to new dtim RAM HDL
2021-03-17 16:59:02 -05:00
Jarred Allen
e39ead0460
Merge branch 'main' into cache
...
Conflicts:
wally-pipelined/testbench/testbench-imperas.sv
2021-03-17 16:40:52 -04:00
Teo Ene
29634f1475
Temporarily reverted my last few commits
2021-03-17 15:16:01 -05:00
Teo Ene
e6661ea26a
fix to last commit
2021-03-17 15:07:02 -05:00
Teo Ene
90946d61c5
fix to last commit
2021-03-17 15:02:15 -05:00
Teo Ene
083a24c06b
addition to last commit
2021-03-17 14:52:31 -05:00
Teo Ene
ca901513c8
Added Ross's addr lab stuff to coremark stuff
2021-03-17 14:50:54 -05:00
Elizabeth Hedenberg
bccd37d778
fixing coremark branch prediction
2021-03-17 15:15:55 -04:00
Elizabeth Hedenberg
74ebe0bef2
replicating coremark changes into coremark bare
2021-03-17 14:36:34 -04:00
Elizabeth Hedenberg
a3b2ffb2c9
Merge branch '3_3_2021' into main
...
Making sure coremark works with spring break changes
2021-03-17 14:11:37 -04:00
Ross Thompson
7bc95ba073
Fixed issue with sim-wally-batch. Are people still using this script?
2021-03-17 11:17:52 -05:00
Ross Thompson
0e2352a6de
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-17 11:07:57 -05:00
Ross Thompson
31ad619a21
Added possibly working OSU test bench as a precursor to running a bp benchmark.
...
Fixed a few bugs with the function radix.
2021-03-17 11:06:32 -05:00
Domenico Ottolia
150faf8dd8
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-03-16 23:27:09 -04:00
Domenico Ottolia
0b880110c9
Add test runner for privileged
2021-03-16 23:26:59 -04:00
Noah Boorstin
45ed2742cf
busybear: add seperate message on bad memory access becasue its confusing
2021-03-16 21:42:26 -04:00
Noah Boorstin
162955de69
busybear: add COUNTERS define
2021-03-16 21:08:47 -04:00
Domenico Ottolia
c9d70a1778
Add privileged testbench
2021-03-16 20:28:38 -04:00
Domenico Ottolia
a40b0c6392
Add privileged tests for mcause
2021-03-16 19:22:36 -04:00
Domenico Ottolia
e44a265b9e
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-03-16 19:12:21 -04:00
Jarred Allen
ed68d8240b
Undo accidental change
2021-03-16 18:16:00 -04:00
Jarred Allen
ba7bfa9056
Condense the parallel and non-parallel wally-pipelined-batch.do files into one
2021-03-16 18:15:13 -04:00
Jarred Allen
6e7fc07fcf
Change busybear to only check that first 100k instructions load
2021-03-16 17:43:39 -04:00
Shreya Sanghai
d9b1e7d67f
added gshare and global history predictor
2021-03-16 17:03:01 -04:00
Jarred Allen
3fc36b978d
Fix icache for jumping into misaligned instructions
2021-03-16 16:57:51 -04:00
Domenico Ottolia
4330e6614b
Add privileged tests folder
2021-03-16 16:11:20 -04:00
Shreya Sanghai
a79e26f9d8
added global history branch predictor
2021-03-16 16:06:40 -04:00
Jarred Allen
98db312574
Merge remote-tracking branch 'origin/main' into cache
2021-03-16 14:17:39 -04:00
Shreya Sanghai
23a7c8cd92
made performance counters count branch misprediction
2021-03-16 11:24:17 -04:00
Shreya Sanghai
518618ad38
Merge branch 'counters' into main
...
added a configurable number of performance counters
2021-03-16 11:01:30 -04:00
Jarred Allen
662ab53746
Merge remote-tracking branch 'origin/main' into cache
2021-03-15 19:08:25 -04:00
Noah Boorstin
cd58f8a12d
remove regression-wally.sh
2021-03-15 19:03:57 -04:00
Noah Boorstin
6d8bcfe6bf
copy Ross's branch predictor preload change into busybear
2021-03-15 18:27:27 -04:00
Ross Thompson
8e51935082
Converted branch predictor preloads to use system verilog rather than modelsim's load command.
2021-03-15 12:39:44 -05:00
Ross Thompson
69aacbad4f
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
...
The last commit message about rv32ic having issues is now invalid. Looks like the issue was resolved.
2021-03-15 12:06:18 -05:00
Ross Thompson
d341e2d5cb
Fixed the parallel script so the rv64ic passes.
...
rv32ic and busybear still have issues.
2021-03-15 12:04:59 -05:00
Jarred Allen
5b174adc2a
Fix BEQZ tests
2021-03-14 15:42:27 -04:00
Jarred Allen
003242ae8a
Merge upstream changes
2021-03-14 14:57:53 -04:00
Jarred Allen
c2f2caa3f6
Get non-jump case working
2021-03-14 14:46:21 -04:00
bbracker
b30ea396b8
slightly smarter dtim HREADY
2021-03-13 07:03:33 -05:00
bbracker
63bfd79009
slightly smarter dtim HREADY
2021-03-13 06:55:34 -05:00
bbracker
12721837f0
imem rd2 adrbits bugfix
2021-03-13 00:10:41 -05:00
Ross Thompson
1f37d9d2db
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-12 20:18:35 -06:00
Ross Thompson
0edaa625e3
Fixed the issue with the batch mode not working after adding the function radix.
2021-03-12 20:16:03 -06:00
bbracker
0f49108ee6
clint HREADY signal update
2021-03-12 20:23:55 -05:00
Ross Thompson
2b9044b9aa
Cleaned up the function radix exractFunctionRadix script. I should change the name as this is no longer a modelsim radix.
2021-03-12 15:29:02 -06:00
Ross Thompson
ccaaa829ce
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-12 14:58:04 -06:00
Ross Thompson
0637874cac
Cleanup of the branch predictor flush and stall controls.
2021-03-12 14:57:53 -06:00
David Harris
4465854423
Drafted rv32a tests
2021-03-12 00:06:23 -05:00
David Harris
d4e84c58ed
64-bit AMO debugged
2021-03-11 23:18:33 -05:00
Ross Thompson
b1d1f3995c
Improve version of the function radix which does not cause the wave file rendering to slow down.
2021-03-11 17:12:21 -06:00
Noah Boorstin
be0bd317e9
test regression script: add commented out rv32ic tests
2021-03-11 12:57:54 -05:00
Noah Boorstin
641a320894
add rv32ic regression test
2021-03-11 12:40:29 -05:00
Noah Boorstin
2dfb944d15
test regression script: parallalize better
2021-03-11 12:25:20 -05:00
Noah Boorstin
b13365365b
test regression script: try adding verilator checking also
2021-03-11 07:32:31 +00:00
Noah Boorstin
8717f3604b
try adding delays to test regression script
2021-03-11 06:59:50 +00:00
Noah Boorstin
c5b6ca4cc6
this is just a test for now, try to reimplement regression-wally in bash
2021-03-11 06:45:45 +00:00
Noah Boorstin
f31d7a7f5c
busybear: account for CSR moving
2021-03-11 06:45:14 +00:00
Thomas Fleming
e57b6cf18c
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
...
Conflicts:
wally-pipelined/src/ebu/ahblite.sv
2021-03-11 00:15:58 -05:00
David Harris
fe4d288589
Initial untested implementation of AMO instructions
2021-03-11 00:11:31 -05:00
Jarred Allen
ff48a9e992
Return testbench to normal
2021-03-10 22:58:41 -05:00
Ross Thompson
f1f7884e10
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-10 15:37:02 -06:00
Ross Thompson
149c9aa0f2
Added debug option to disable the function radix if not needed.
...
Function radix slows the simulation by 70 to 76 s (8.5%) for the rv64i tests.
2021-03-10 15:17:02 -06:00
Ross Thompson
4d7e926dbb
I finally think I got the function radix debugger working across both 32 and 64 bit applications.
2021-03-10 14:43:44 -06:00
Noah Boorstin
2d1f63b590
change flop in ahb controller to use normal flop module
2021-03-10 19:14:02 +00:00
Ross Thompson
7b7cacbaf0
Finally I think I have the function radix mapping across all applications correctly. I still need to clean up the code a bit so it is easier to understand.
2021-03-10 11:00:51 -06:00
Jarred Allen
c0ee17b6ac
Merge upstream changes
2021-03-09 21:20:34 -05:00
Jarred Allen
81b29a3891
More progress
2021-03-09 21:16:07 -05:00
David Harris
0baa004bb4
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-09 09:28:32 -05:00
David Harris
bea8ac6d59
WALLY-LRSC atomic test passing
2021-03-09 09:28:25 -05:00
Noah Boorstin
87e2a9b920
busybear: better NOPing out of float instructions
2021-03-08 21:24:19 +00:00
Noah Boorstin
9274d09ae2
busybear: better instrF checking
...
So this now checks instrF only when StallD is low. @kaveh I'd love your
opinion on this. I don't know if this is a good idea or not. Ideally we
should probably be checking InstrRawD instead, but I kind of want to stay
checking the instr in the F stage instead of D for now. Idk if this is worth
staying in F, I can't really see any big downsides to checking the instruction in
D except that PCD isn't an external signal, but neither is StallD, so.....
Anyway I'd love others' thoughts on this
2021-03-08 19:48:12 +00:00
