Ross Thompson
7aecd72c35
Fpga does not correctly boot linux. I think the solution here is to revert out all substantive changes except for parameterization and then add them back in one at a time. This is necessary because the parameterization is not completed in one contiguous group of commits.
2023-06-22 12:55:49 -05:00
Ross Thompson
a8f11dcad0
FPGA updates.
2023-06-20 11:11:34 -05:00
Ross Thompson
0423d7df82
I think the fpga is building again, but the debugger script needs to be updated. For some reason the nets are not present despite being marked debug.
2023-06-16 17:00:27 -05:00
Jacob Pease
40f81d5da6
The Vivado-RISC-V SDC works. Wally is now booting through it.
2023-05-26 15:42:33 -05:00
Ross Thompson
b13fe870cf
Yeah We boot linux on the arty a7!
2023-04-19 11:17:33 -05:00
Ross Thompson
1fec535b32
Fixed the reset for Arty A7 and now partially boots. Copies flash card to dram.
...
but the data is wrong.
2023-04-19 10:35:18 -05:00
Ross Thompson
367bd0f8dc
More debug stuff.
2023-04-18 16:00:10 -05:00
Ross Thompson
668e69fdc9
Added more signals to debugger in hopes I can figure out why the mig is not responding.
2023-04-18 15:51:52 -05:00
Jacob Pease
2839f4f41a
AHB triggers write, but AXI side doesn't update.
2023-04-18 15:23:22 -05:00
Ross Thompson
3588c53e66
It's almost working.
2023-04-18 14:24:59 -05:00
Ross Thompson
deb0bfc24d
Improved constraints and set ddr3 voltage to correct 1.35V. This voltage is only for synthesis. However I'm concerned because the gui did not let me select 1.35V.
2023-04-17 20:05:59 -05:00
Ross Thompson
777bec2e24
Fixed timing constraint issue.
2023-04-17 19:53:43 -05:00
Ross Thompson
b2b30936be
Found the DDR3 memory is not ready when issuing the first store.
2023-04-17 19:33:13 -05:00
Ross Thompson
fbbba0e5c2
Finally we are building the fpga and can view the ila. we are getting out of reset, but we are stuck at PCM = 10b8.
2023-04-17 18:39:25 -05:00
Ross Thompson
2cbaa5c27b
Dang. Looks like the reset button on the arty a7 is actually resetn. I wish they'd named it that way.
2023-04-17 16:37:18 -05:00
Ross Thompson
480562e53e
Yay! We now have a functional ila and the uart connection on the pc side works. However the CPU is stuck in reset. Not really sure what's going on there.
2023-04-17 16:00:02 -05:00
Ross Thompson
b0f0fb1da7
Adding in the ILA to the arty a7.
2023-04-17 14:54:10 -05:00
Ross Thompson
5591b447d6
Fixed more issues with arty a7 constarints.
2023-04-16 13:25:02 -05:00
Ross Thompson
f4734c0d1b
Found and fixed the major architecture issue with the mig 7 used in the arty a7 board.
...
mig 7 is completely different from the ddr4 mig in that the internal pll does not general the required clocks. An external mmcm is required to general two inputs clocks and the required user clock.
2023-04-15 11:13:28 -05:00
Ross Thompson
2f8359e6cc
Realized we need a separate mmcm when using the mig 7 for ddr3 rather than the ddr4 mig. Go figure.
2023-04-14 18:02:16 -05:00
Ross Thompson
4563b650bf
Fixed more bugs in the ila debug constraints.
2023-04-11 14:32:53 -05:00
Ross Thompson
e490ab09cf
Updated to help debut Jacob's crossbar woes.
2023-04-11 14:22:42 -05:00
Ross Thompson
6c07a2e595
Fixed sum bugs with arty a7 ila script.
2023-04-11 10:00:06 -05:00
Ross Thompson
c4e5b8db49
Updates for arty a7.
2023-04-10 17:02:19 -05:00
Ross Thompson
5bcb0f6ace
Fixed syntax errors in arty7 top level.
2023-04-10 16:08:40 -05:00
Ross Thompson
0700202001
Added more support for Arty A7 board.
2023-04-10 16:01:17 -05:00
Ross Thompson
e7f494ef95
Started putting together the arty a7 board package files.
2023-04-10 13:15:55 -05:00
Jacob Pease
b796b1b492
Build doesn't work. AXI Crossbar has problems.
2023-04-06 16:01:58 -05:00
Ross Thompson
1986ef0625
Started constrains file for arty a7 fpga.
2023-03-24 20:38:13 -05:00
Ross Thompson
576d37eb8c
Updated fpga constraints to remove critical warning.
2023-03-24 19:09:36 -05:00
Jacob Pease
2d0199a354
Added sdio_cd to vcu108 constraints. Removed SDC signals from uncore
2023-03-24 17:01:27 -05:00
Ross Thompson
be0318209e
Updated fpga ila script.
2023-03-06 13:14:48 -06:00
Jacob Pease
85d789a7e0
AXI Crossbar is working. Fixed address width in generator script.
2023-02-22 15:13:16 -06:00
Jacob Pease
f2e4274c9c
Fixed debug signal names. Builds on the fpga. Bug in the crossbar.
2023-02-16 17:33:21 -06:00
Ross Thompson
ff7dc4f34a
fpga constraints updates
2023-02-07 15:22:14 -06:00
Jacob Pease
293cc88bd9
Added extra core signal to mark_debug.txt. Modified wally.tcl
2023-01-23 17:00:24 -06:00
Ross Thompson
2fc47bab9c
More fixes for the debug2.xdc constraints.
2023-01-20 20:48:19 -06:00
Ross Thompson
61efb22db1
More fixes to fpga ila debugger.
2023-01-20 20:28:21 -06:00
Ross Thompson
e28ea2d630
Fixed fpga constraints.
2023-01-20 20:18:04 -06:00
Ross Thompson
0ed9811e31
Updated fpga constraints.
2023-01-20 20:16:33 -06:00
Ross Thompson
25bd2e4670
Removed mark_debug vivado directive from source code.
...
Created script to add mark_debug directive to source code based on a file which contains locations and signal which need them for the FPGA debugger.
Files output to temporary directory.
2023-01-20 19:43:18 -06:00
Ross Thompson
6ccb3a0147
Test commit.
2023-01-20 17:27:09 -06:00
Ross Thompson
11c6106022
Repaired fpga debugger.
2023-01-20 15:26:52 -06:00
Ross Thompson
e0ec45489a
Updated constraints to remove DivBusyE.
2022-12-30 10:51:35 -06:00
Ross Thompson
138c3542db
Updated fpga constraints.
2022-12-24 10:21:16 -06:00
Ross Thompson
b5a85b55f1
Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage.
...
Generate WFIStallM in the privileged unit rather than generate in hazard.
Cleaned up the hazard cause logic to be consistent across all causes.
2022-12-23 15:10:37 -06:00
Ross Thompson
6b105bd217
Renamed IFU and LSU stalls.
2022-12-22 21:56:33 -06:00
Ross Thompson
15042fc856
Updated fpga constraints.
2022-12-21 14:50:01 -06:00
Ross Thompson
13beda7d0c
Updated vcu118 piniout.
2022-12-18 14:00:10 -06:00
Ross Thompson
3ee6ed8542
Updated fpga constraints
2022-12-15 16:45:55 -06:00
rachanaerra
10ff69efc1
updated constraints file
2022-12-05 15:05:21 -06:00
Ross Thompson
30b2bd263c
Updates to fpga constraints.
2022-11-09 13:52:36 -06:00
Jacob Pease
160ca366c8
Added PLIC signals for debugging on FPGA.
2022-10-25 13:57:09 -05:00
Ross Thompson
9ba487c323
Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile.
2022-10-24 15:38:39 -05:00
Ross Thompson
92ace4d8f7
Forget to include updated xdc file.
2022-10-24 13:51:21 -05:00
Ross Thompson
a008c61939
Updated debug2.xdc for interlock fsm changes.
2022-10-19 17:34:47 -05:00
Ross Thompson
2d063bbb2d
Updated constraints file to work with alternate uart.
2022-10-04 17:35:44 -05:00
Ross Thompson
16e10a4c5b
added new constraints for fpga.
2022-09-17 22:20:06 -05:00
Ross Thompson
787f5bcccb
Fixed fpga debug constraints.
2022-09-03 17:36:29 -05:00
Ross Thompson
4d60d9a840
Fixed up FPGA constraints.
...
Added back in the fpga boot rom preload.
2022-09-02 13:54:35 -05:00
Ross Thompson
01a7718471
Added generate around ebu.
2022-08-25 09:24:13 -05:00
Ross Thompson
701324eeb8
Updated ila signals.
...
Improve fpga wave config.
added back in the fpga preload.
2022-08-25 09:03:29 -05:00
Ross Thompson
8180d1ade4
Updated fpga debugger to latest RTL version.
2022-08-19 17:13:36 -05:00
Ross Thompson
8b2491c169
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-08-19 16:39:28 -05:00
Ross Thompson
83bca570ae
Modified debugger for updated rtl.
2022-06-04 14:39:55 -05:00
Ross Thompson
1318f702cf
Added more debug signals to uart.
2022-05-21 19:47:40 -05:00
Ross Thompson
db85afcd2d
Added more plic debugging signals.
2022-05-21 14:04:08 -05:00
Ross Thompson
6cae5aa88f
Updated the fpga constraints.
2022-05-21 13:32:03 -05:00
Ross Thompson
9079e67aae
Updated fpga debugger.
2022-05-17 23:04:01 -05:00
Ross Thompson
51add16def
Updated debugger constraints.
2022-05-09 10:19:25 -05:00
Ross Thompson
c045e3afd8
Added back the instret counter to ILA.
2022-04-17 18:44:07 -05:00
Ross Thompson
82356342f0
Added another GPR to debugger.
2022-04-17 18:12:05 -05:00
Ross Thompson
c16dec88de
Increased uart baud rate to 230400.
...
Added uart signals to debugger.
2022-04-17 15:23:39 -05:00
Ross Thompson
43a294dc88
Added signals to ila.
2022-04-07 21:09:50 -05:00
Ross Thompson
9db8471bf2
Added sp to ila.
2022-04-07 16:29:41 -05:00
Ross Thompson
64846c800e
Constraint changes for 40Mhz wally.
2022-04-04 10:50:48 -05:00
Ross Thompson
5ef6cde52e
Added more ILA signals.
2022-04-02 16:39:45 -05:00
Ross Thompson
0340c0fd44
Added wave config
...
added new signals to ILA.
2022-04-01 12:44:14 -05:00
Ross Thompson
cb945a6a6a
Added PLIC to ILA.
2022-03-31 16:44:49 -05:00
Ross Thompson
4f1258043d
Updated constraints file.
2022-03-30 17:48:44 -05:00
Ross Thompson
f818b2a428
Updated debug2.xdc ila constraints to match rtl.
2022-03-28 10:52:26 -05:00
Ross Thompson
111e02677d
Fixed ila's config.
2022-02-11 13:58:45 -06:00
Ross Thompson
6a82ee0579
Fixed debug2.xdc to match wally changes.
2022-02-08 15:23:44 -06:00
Ross Thompson
b621eb78fb
Updated debug2 ila signal names.
2022-01-28 11:43:49 -06:00
Ross Thompson
1bb8d36308
Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.
2022-01-27 17:11:27 -06:00
Ross Thompson
728e46a794
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-25 19:21:04 -06:00
Ross Thompson
db197b6491
Added pin location for reset on VCU118 board. Somehow this was missing and still worked.
2022-01-25 17:48:42 -06:00
David Harris
ca1f7ce5d3
Renamed wallypipelinedhart to wallypipelinedcore
2022-01-20 16:02:08 +00:00
Ross Thompson
05ebadacad
Added PCNextF and PostSpillInstrRawF to ila.
2022-01-19 14:05:14 -06:00
Ross Thompson
305fccfe7a
Fixed fpga ila debug to match lsu changes.
2022-01-18 21:13:18 -06:00
Ross Thompson
5cf686429d
Merged in the debug ila updates.
2022-01-18 17:29:21 -06:00
David Harris
f7f3882cb8
Moved Dcache into bus block
2022-01-15 00:39:07 +00:00
David Harris
d9e8d16bbe
Renamed LSUStall to LSUStallM
2022-01-15 00:24:16 +00:00
Ross Thompson
26fb09c868
Added additional fsm to ILA.
2022-01-12 14:17:16 -06:00
Ross Thompson
6eb2f37ce4
Possible fix for the TrapM DTLBMiss suppression.
2022-01-12 14:17:16 -06:00
Ross Thompson
09d605ac6a
Updated debug constraints again to match changes in verilog.
2022-01-08 13:28:51 -06:00
Ross Thompson
3625fc3bed
Patched the ILA's debug2.xdc constraint file to work with the wally memory design.
2022-01-06 15:18:18 -06:00
Ross Thompson
c19b910f6e
Updated fpga ILA constraints to match the new changes to the rtl.
2022-01-06 11:56:09 -06:00
Ross Thompson
1ab3a17ff7
Updates to support fpga.
2022-01-05 18:07:23 -06:00
Ross Thompson
53736096a6
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-20 10:03:19 -06:00
