cvw/fpga/constraints
2023-06-16 17:00:27 -05:00
..
artyddr3.ucf
constraints-ArtyA7.xdc
constraints-vcu108.xdc
constraints-vcu118.xdc
debug2.xdc
debug4.xdc I think the fpga is building again, but the debugger script needs to be updated. For some reason the nets are not present despite being marked debug. 2023-06-16 17:00:27 -05:00
marked_debug.txt
small-debug.xdc
test.file