cvw/fpga/constraints
Ross Thompson f4734c0d1b Found and fixed the major architecture issue with the mig 7 used in the arty a7 board.
mig 7 is completely different from the ddr4 mig in that the internal pll does not general the required clocks. An external mmcm is required to general two inputs clocks and the required user clock.
2023-04-15 11:13:28 -05:00
..
artyddr3.ucf Added more support for Arty A7 board. 2023-04-10 16:01:17 -05:00
constraints-ArtyA7.xdc Found and fixed the major architecture issue with the mig 7 used in the arty a7 board. 2023-04-15 11:13:28 -05:00
constraints-vcu108.xdc Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile. 2022-10-24 15:38:39 -05:00
constraints-vcu118.xdc Updated vcu118 piniout. 2022-12-18 14:00:10 -06:00
debug2.xdc Updated to help debut Jacob's crossbar woes. 2023-04-11 14:22:42 -05:00
debug4.xdc Fixed more bugs in the ila debug constraints. 2023-04-11 14:32:53 -05:00
marked_debug.txt Updated fpga constraints to remove critical warning. 2023-03-24 19:09:36 -05:00
small-debug.xdc Fixed sum bugs with arty a7 ila script. 2023-04-11 10:00:06 -05:00
test.file Test commit. 2023-01-20 17:27:09 -06:00