David Harris
f3c7025ade
Started make allsynth to try many experiments
2022-02-17 17:57:02 +00:00
Ross Thompson
2fc7dc3e57
Fixed a bunch of the virtual memory changes. Now supports atomic update of PTE in memory concurrent with TLB.
2022-02-17 10:04:18 -06:00
Ross Thompson
62f5f1e622
Broken state. address translation not working after changes to hptw to support atomic updates to PT.
2022-02-16 23:37:36 -06:00
Ross Thompson
eafd52e2bc
Added additional suppresses to vsim command incase buildroot files are missing.
2022-02-16 17:05:54 -06:00
Ross Thompson
c9e33208e3
Moved a few muxes around after sww changes.
2022-02-16 15:43:03 -06:00
Ross Thompson
71ed49bf2b
cleanup of signal names.
2022-02-16 15:29:08 -06:00
Ross Thompson
6dc12b4968
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-16 15:22:35 -06:00
Ross Thompson
27042f028e
Modified lsu and uncore so only 1 sww is present. The sww is in the LSU if there is a cache or dtim. uncore.sv contains the sww if there is no local memory in the LSU. This is necessary as the subword write needs the read data to be valid and that read data is not aviable in the correct cycle in the LSU if there is no dtim or cache. Muxing could be done to provide the correct read data, but it adds muxes to the critical path.
2022-02-16 15:22:19 -06:00
David Harris
c23db6a31e
Cleaned warning on HPTW default state
2022-02-16 17:40:13 +00:00
David Harris
01fa5c94bd
Register file comments about reset
2022-02-16 17:21:05 +00:00
Ross Thompson
c56c4db47f
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-16 09:48:16 -06:00
Skylar Litz
0c69d3291d
update bugfinder script to new file organization
2022-02-15 22:58:18 +00:00
Kip Macsai-Goren
6c1383e2a0
added CSR permission and minfor to 32 bit tests
2022-02-15 20:19:14 +00:00
Kip Macsai-Goren
5df0a9531f
merged test macros in with 32 bit tests
2022-02-15 20:19:14 +00:00
David Harris
aa990be959
removed csrn and all of its outputs because depricated
2022-02-15 19:59:29 +00:00
David Harris
d8170e9dd3
Mostly removed N_SUPPORTED
2022-02-15 19:50:44 +00:00
David Harris
ed8ac3d881
Just needed to recompile - all good. Now removed uretM because N-mode is depricated
2022-02-15 19:48:49 +00:00
David Harris
5ef8f6bc7e
Removed depricated N-mode support and SI/EDELEG registers. rv64gc_wally64priv tests are failing, but seem to be failing before this change.
2022-02-15 19:20:41 +00:00
Kip Macsai-Goren
9266bc382e
light cleanup for privileged tests
2022-02-15 17:06:16 +00:00
Ross Thompson
fcbb577f31
Cache mods to be consistant with diagrams.
2022-02-14 12:40:51 -06:00
David Harris
143eb0ae65
srt fixes
2022-02-14 18:40:27 +00:00
David Harris
3598e05998
srt batch files
2022-02-14 18:37:46 +00:00
ushakya22
3e2e9bc6a0
bring branch back into main
...
Merge branch 'srt_division_with_unpacker' into main
2022-02-14 18:25:34 +00:00
ushakya22
df561f8550
work in progress exponent handling
2022-02-14 18:24:29 +00:00
David Harris
caa4d83e57
t push
...
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-02-14 01:22:22 +00:00
Ross Thompson
86e117ea77
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-13 18:21:15 -06:00
Ross Thompson
6e1a0af5d0
Eliminated more ports in cacheway.
2022-02-13 15:53:46 -06:00
Ross Thompson
a440bc2ac5
More cache cleanup.
2022-02-13 15:47:27 -06:00
Ross Thompson
1e7e59bdbd
Changed names of signals in cache.
2022-02-13 15:06:18 -06:00
Ross Thompson
f87a6f2c63
More cache cleanup.
2022-02-13 12:38:39 -06:00
ushakya22
a996a5e16c
Added unpacker into testbench for srt
2022-02-12 22:05:18 +00:00
David Harris
f5678e25db
Synthesis cleanup
2022-02-12 06:25:12 +00:00
David Harris
b537df2651
Synthesis script cleanup, eliminated privileged instructiosn from controller when ZICSR_SUPPORTED = 0
2022-02-12 05:50:34 +00:00
Ross Thompson
f5c4bca47e
Formating improvements to cache.
2022-02-11 23:10:58 -06:00
Ross Thompson
6fa9490d0b
More cache simplifications.
2022-02-11 22:54:05 -06:00
Ross Thompson
ae2011eb07
Reduced seladr to 1 bit as second bit is same as selflush.
2022-02-11 22:41:36 -06:00
Ross Thompson
cb3d71a63d
Reduced complexity of the address selection during flush.
2022-02-11 22:27:27 -06:00
Ross Thompson
a0ee2f3d99
Removed redundant signals from cache.
2022-02-11 22:23:47 -06:00
Ross Thompson
aa04778d0b
Cache fsm simplifications.
2022-02-11 15:16:45 -06:00
Ross Thompson
e6c8cfd49b
Removed STATE_CPU_BUSY_FINISH_AMO from cache. This is redundant with STATE_CPU_BUSY.
2022-02-11 15:09:00 -06:00
Ross Thompson
83adacbee3
Simplified cache fsm.
2022-02-11 14:54:57 -06:00
Ross Thompson
c8e6884926
Fixed bug.
...
It was possible for DTLBMissM to prevent a dcache flush.
2022-02-11 14:00:01 -06:00
Ross Thompson
b1cba4be2b
Updates to linux wave.
2022-02-11 13:28:18 -06:00
Ross Thompson
9145a96b53
Updated linux wave.
2022-02-11 13:15:42 -06:00
Ross Thompson
3f4ae91468
linux wave cleanup.
2022-02-11 10:48:45 -06:00
Ross Thompson
20456097cd
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-11 10:47:21 -06:00
Ross Thompson
2f2a4f4500
Fixed subtle and infrequenct bug.
...
Loading buildroot at 483M instructions started with a spill + ITLBMiss. The spillsupport logic allowed transition to the second access only after the bus/cache completed the first operation. However the BusStall was suppressed if ITLBMissF occurs resulting in the spillfsm advancing to the second operation. Now the spill logic also takes in ITLBMissF and prevents the early transition to the second access.
2022-02-11 10:46:06 -06:00
David Harris
15fb7fee60
Cleaned up synthesis warnings
2022-02-11 01:15:16 +00:00
Ross Thompson
fc6dc52618
Fixed bugs in ifu spills and missing reset on bus data register.
2022-02-10 18:11:57 -06:00
Ross Thompson
9ad4523b9d
Updated wave files to reflect recent changes.
2022-02-10 17:52:19 -06:00
Ross Thompson
f23817bf69
Replacement policy cleanup.
2022-02-10 11:42:40 -06:00
Ross Thompson
411997010b
Replacement policy cleanup.
2022-02-10 11:40:10 -06:00
Ross Thompson
382d5fab0f
Cleanup.
2022-02-10 11:27:15 -06:00
Ross Thompson
3a0af5d9e9
Cleanup + critical path optimizations.
2022-02-10 11:11:16 -06:00
Ross Thompson
fc68c2f09a
Cache name clarifications.
2022-02-10 10:50:17 -06:00
Ross Thompson
e00d404154
More cache cleanup.
2022-02-10 10:43:37 -06:00
Ross Thompson
65803ebe98
structural muxes.
2022-02-09 19:36:21 -06:00
Ross Thompson
2a989e6d05
More cache cleanup.
2022-02-09 19:29:15 -06:00
Ross Thompson
3b8ad3f7c7
Cleaned up comments.
2022-02-09 19:21:35 -06:00
Ross Thompson
911ee36b22
Removed all possilbe paths to PreSelAdr from TrapM.
2022-02-09 19:20:10 -06:00
Ross Thompson
327a05c9d8
Added commented out commands to generate saif file from vsim.
2022-02-09 18:40:45 -06:00
Ross Thompson
01126535db
Annotated the final changes required to move sram address off the critial path.
2022-02-08 18:17:31 -06:00
Ross Thompson
7133e790ea
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-08 17:52:15 -06:00
Ross Thompson
498388c636
Cache cleanup write enables.
2022-02-08 17:52:09 -06:00
Ross Thompson
8a49ec90d0
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-08 15:43:18 -06:00
Ross Thompson
e0a605e95d
Cleanup IFU.
2022-02-08 14:54:53 -06:00
Ross Thompson
d1d014bf1d
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-08 14:47:15 -06:00
Ross Thompson
13561c67bd
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-08 14:22:19 -06:00
Ross Thompson
cecbb3362d
rv32e works for now. Still need to optimize.
2022-02-08 14:21:55 -06:00
Ross Thompson
39149c618f
Moved some muxes back into the bp.
2022-02-08 14:17:44 -06:00
David Harris
3e16730226
RAM simplification
2022-02-08 20:15:23 +00:00
Ross Thompson
d5d9bb9d4d
Temporary commit which gets the no branch predictor implementation working.
2022-02-08 14:13:55 -06:00
David Harris
c07584bb70
rv32e config update
2022-02-08 17:59:50 +00:00
Ross Thompson
c2377eaaf4
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-08 11:36:30 -06:00
Ross Thompson
3cd067ac6a
Finished merge.
2022-02-08 11:36:24 -06:00
David Harris
9ad3f26365
Restored E tests to makefrag
2022-02-08 16:41:11 +00:00
Ross Thompson
492c1473f3
Preparing to make a major change to the cache's write enables.
2022-02-08 09:47:01 -06:00
David Harris
e5097e67d4
Fixed TIM tests; rv32e test still failing
2022-02-08 15:24:37 +00:00
David Harris
e9a519a228
Patching up testbench; fixed false passing, but rv32ic and rv32e tests now fail
2022-02-08 12:40:02 +00:00
David Harris
096242a6d8
Merged TIM and regular testbenches. RV32e now working and back in regression.
2022-02-08 12:18:13 +00:00
David Harris
72c2166223
Lab 3 file cleanup
2022-02-08 10:26:37 +00:00
Ross Thompson
190d619940
cachefsm cleanup.
2022-02-07 22:09:56 -06:00
Ross Thompson
ca459a5915
Removed VDWriteEnable.
2022-02-07 21:59:18 -06:00
Ross Thompson
494802b2e1
more partial cleanup of fsm and write enables.
2022-02-07 17:41:56 -06:00
Ross Thompson
23a60d9875
Progress towards simplifying the cache's write enables.
2022-02-07 17:23:09 -06:00
Ross Thompson
fcd43ea004
more cleanup.
2022-02-07 13:29:19 -06:00
Ross Thompson
e72d54ea98
More cachefsm cleanup.
2022-02-07 13:19:37 -06:00
Ross Thompson
a6a7779ec0
More cachefsm cleanup.
2022-02-07 12:30:27 -06:00
Ross Thompson
7f732eb571
More cachefsm cleanup.
2022-02-07 11:16:20 -06:00
Ross Thompson
be67c4d559
More cachefsm cleanup.
2022-02-07 11:12:28 -06:00
Ross Thompson
f1781c6bc8
More cachefsm cleanup.
2022-02-07 10:54:22 -06:00
Ross Thompson
b89ce18473
Cache cleanup.
2022-02-07 10:43:58 -06:00
Ross Thompson
6f4a321d31
More cachfsm cleanup.
2022-02-07 10:33:50 -06:00
David Harris
60c3cdad3a
Reverted cache change
2022-02-07 14:47:20 +00:00
David Harris
d0c40cca7a
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-02-07 14:43:31 +00:00
David Harris
c21eb67a07
Cache syntax cleanup
2022-02-07 14:43:24 +00:00
Ross Thompson
8bcaadda6b
More cachefsm cleanup.
2022-02-06 21:50:44 -06:00
Ross Thompson
347e9228f8
started cachefsm cleanup.
2022-02-06 21:39:38 -06:00
Kip Macsai-Goren
38b75e85a0
added new tests to make and testbench
2022-02-06 19:47:22 +00:00
David Harris
0feb624bab
Added E tests to wally-riscv-arch-test rv32i_m/I and fixed cyclic path in rv32e configuration
2022-02-06 01:22:40 +00:00
