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452 Commits

Author SHA1 Message Date
Jacob Pease
1edd5bb39e New bootloader now works. Added special print functions and print messages. sdclk is set to 3MHz after initialization currently. 2024-08-02 15:19:52 -05:00
Jacob Pease
897f6561cd New bootloader now works. Added special print functions and print messages. sdclk is set to 3MHz after initialization currently. 2024-08-02 15:19:52 -05:00
Jacob Pease
3fde6c13f7 Added functions to read registers and print information on failure. Also added a getTime function for a pretty boot display. 2024-08-02 15:14:30 -05:00
Jacob Pease
fcd88d6e6f Added functions to read registers and print information on failure. Also added a getTime function for a pretty boot display. 2024-08-02 15:14:30 -05:00
Jacob Pease
906fa73747 Updated formatting of gpt.c and boot.c. 2024-07-31 11:12:05 -05:00
Jacob Pease
38071d8267 Updated formatting of gpt.c and boot.c. 2024-07-31 11:12:05 -05:00
Jacob Pease
0396181d1e Added function to set SPI clock speed. 2024-07-31 11:00:44 -05:00
Jacob Pease
ee980e39f3 Added function to set SPI clock speed. 2024-07-31 11:00:44 -05:00
Jacob Pease
826576bfc7 Cleaned up code formatting a bit and added ability to set the SD card clock speed. 2024-07-31 10:59:41 -05:00
Jacob Pease
c4ae17c679 Cleaned up code formatting a bit and added ability to set the SD card clock speed. 2024-07-31 10:59:41 -05:00
Jacob Pease
5d6699dc4c Added extra UART macros and functions for code readability and the ability to print decimal numbers. 2024-07-31 10:58:15 -05:00
Jacob Pease
a263f836f2 Added extra UART macros and functions for code readability and the ability to print decimal numbers. 2024-07-31 10:58:15 -05:00
Jordan Carlin
e78fac1624 Replace /opt/riscv after merge 2024-07-25 21:33:31 -07:00
Jordan Carlin
e851812608
Replace /opt/riscv after merge 2024-07-25 21:33:31 -07:00
Jordan Carlin
2f1a101735 Merge branch 'main' of https://github.com/openhwgroup/cvw into installation 2024-07-25 21:21:57 -07:00
Jordan Carlin
42a9bbf28d
Merge branch 'main' of https://github.com/openhwgroup/cvw into installation 2024-07-25 21:21:57 -07:00
Jacob Pease
8a5898ebc1 Added carriage returns to line feed characters. UART messages print properly now. 2024-07-25 13:05:57 -05:00
Jacob Pease
3975f60299 Added carriage returns to line feed characters. UART messages print properly now. 2024-07-25 13:05:57 -05:00
Jacob Pease
f12319ca96 Changed formatting and added new UART divsor calculation from OpenSBI. 2024-07-25 13:04:27 -05:00
Jacob Pease
a36e846b02 Changed formatting and added new UART divsor calculation from OpenSBI. 2024-07-25 13:04:27 -05:00
Jacob Pease
6fc10adc25 Added ability to split boot.memfile into boot.mem and data.mem. 2024-07-25 11:19:15 -05:00
Jacob Pease
336a413f31 Added ability to split boot.memfile into boot.mem and data.mem. 2024-07-25 11:19:15 -05:00
Jacob Pease
02bb9b0b8b Fixed SDCCLK name discrepency. 2024-07-24 22:48:31 -05:00
Jacob Pease
0dae881a0d Fixed SDCCLK name discrepency. 2024-07-24 22:48:31 -05:00
Jacob Pease
a34836c08b Commented out references to old axi IP from wally.tcl. 2024-07-24 22:47:15 -05:00
Jacob Pease
ebdf25a53b Commented out references to old axi IP from wally.tcl. 2024-07-24 22:47:15 -05:00
Jacob Pease
ffec8cfb20 Removed old axi IP from fpga Makefile. Added sed for data.mem file loaded into uncore ram. 2024-07-24 22:46:24 -05:00
Jacob Pease
2caf9e93be Removed old axi IP from fpga Makefile. Added sed for data.mem file loaded into uncore ram. 2024-07-24 22:46:24 -05:00
Jacob Pease
36d330a173 Masked lower byte when writing to DLL. 2024-07-24 22:44:27 -05:00
Jacob Pease
d15be492cb Masked lower byte when writing to DLL. 2024-07-24 22:44:27 -05:00
Jacob Pease
a97c7f0b58 Initialized UART with Arty frequency and baud rate. Will make this dynamic in the future 2024-07-24 22:43:47 -05:00
Jacob Pease
286d80de7e Initialized UART with Arty frequency and baud rate. Will make this dynamic in the future 2024-07-24 22:43:47 -05:00
Jacob Pease
e175a41863 Added uart header to gpt.c. 2024-07-24 22:43:16 -05:00
Jacob Pease
0107a400d1 Added uart header to gpt.c. 2024-07-24 22:43:16 -05:00
Rose Thompson
5cae55561e Removed unused file. 2024-07-24 13:30:25 -05:00
Rose Thompson
994386f12c Removed unused file. 2024-07-24 13:30:25 -05:00
Rose Thompson
d0a5b278b7 Factored out the rvvi testbench code into rvvitbwrapper. 2024-07-24 13:10:57 -05:00
Rose Thompson
13db14db6b Factored out the rvvi testbench code into rvvitbwrapper. 2024-07-24 13:10:57 -05:00
Rose Thompson
b1a711ae0f Converted fpga's rvvi from a config option to a testbench/fpga top level parameter and is envoked by passing --rvvi to wsim. 2024-07-24 12:47:50 -05:00
Rose Thompson
c11036358a Converted fpga's rvvi from a config option to a testbench/fpga top level parameter and is envoked by passing --rvvi to wsim. 2024-07-24 12:47:50 -05:00
Jacob Pease
c18b3d814d Fixed verilog bugs. 2024-07-23 17:26:39 -05:00
Jacob Pease
f1cc7dd5a3 Fixed verilog bugs. 2024-07-23 17:26:39 -05:00
Jacob Pease
23d9c7a486 Fixed syntax bugs. inline functions are now static and in the spi.h header. 2024-07-23 17:00:32 -05:00
Jacob Pease
dcb2edf888 Fixed syntax bugs. inline functions are now static and in the spi.h header. 2024-07-23 17:00:32 -05:00
Jacob Pease
692bbc35fd Initial pass on SPI based bootloader code finished. 2024-07-23 16:33:49 -05:00
Jacob Pease
5f0addd69a Initial pass on SPI based bootloader code finished. 2024-07-23 16:33:49 -05:00
Jacob Pease
659f0d3646 Added some minor error checking to gpt.c. 2024-07-23 16:32:52 -05:00
Jacob Pease
a8b9e7776b Added some minor error checking to gpt.c. 2024-07-23 16:32:52 -05:00
Jacob Pease
fe0f6de2ab Added sd_read64 to help with block reads and crc checking. 2024-07-23 16:32:29 -05:00
Jacob Pease
ab00ea5a5c Added sd_read64 to help with block reads and crc checking. 2024-07-23 16:32:29 -05:00
Jacob Pease
a95106b516 Progress made on implementing new disk read function. 2024-07-23 15:47:23 -05:00
Jacob Pease
57eeba5c8c Progress made on implementing new disk read function. 2024-07-23 15:47:23 -05:00
Jacob Pease
db13ed63b9 Removed references to card_type. 2024-07-23 15:46:18 -05:00
Jacob Pease
9ccb0eb027 Removed references to card_type. 2024-07-23 15:46:18 -05:00
Jacob Pease
188df61037 Added uart print functions and the Wally banner. SD card can now be initialized. Removed old code from boot.c 2024-07-23 14:18:42 -05:00
Jacob Pease
bf65cd2817 Added uart print functions and the Wally banner. SD card can now be initialized. Removed old code from boot.c 2024-07-23 14:18:42 -05:00
Rose Thompson
8ca565ed53 Updated for a better ILA rvvi debugger. 2024-07-22 17:44:04 -05:00
Rose Thompson
5381e1f395 Updated for a better ILA rvvi debugger. 2024-07-22 17:44:04 -05:00
Jacob Pease
ef1f55626c Added sd_cmd and utility SPI functions. 2024-07-22 16:57:04 -05:00
Jacob Pease
b05052311f Added sd_cmd and utility SPI functions. 2024-07-22 16:57:04 -05:00
Rose Thompson
121342f4cc Updated the verilog-ethernet repo to remove most of the warnings. Updated the fpga constraints so the ILA is more useful when using RVVI. 2024-07-22 16:12:06 -05:00
Rose Thompson
3c06556833 Updated the verilog-ethernet repo to remove most of the warnings. Updated the fpga constraints so the ILA is more useful when using RVVI. 2024-07-22 16:12:06 -05:00
Jacob Pease
4585ad8891 Added new SDC clock constraint. 2024-07-22 13:05:16 -05:00
Jacob Pease
cec39fd3aa Added new SDC clock constraint. 2024-07-22 13:05:16 -05:00
Jacob Pease
a722c3c0a1 Removed the old SDC. Added a second SPI peripheral that now will be used to control the SD card. SPI peripheral now outputs SPICLK. Removed references to the now non-existent external SDC in uncore. Removed all of the AXI Xilinx IP. 2024-07-22 12:36:39 -05:00
Jacob Pease
a506d76149 Removed the old SDC. Added a second SPI peripheral that now will be used to control the SD card. SPI peripheral now outputs SPICLK. Removed references to the now non-existent external SDC in uncore. Removed all of the AXI Xilinx IP. 2024-07-22 12:36:39 -05:00
Rose Thompson
556c210e76 Added option to use rvvi ila 2024-07-22 12:19:37 -05:00
Rose Thompson
efa99940c5 Added option to use rvvi ila 2024-07-22 12:19:37 -05:00
Rose Thompson
7223b15134 Merge branch 'rvvi' 2024-07-22 12:01:01 -05:00
Rose Thompson
02f108345a Merge branch 'rvvi' 2024-07-22 12:01:01 -05:00
Rose Thompson
24609f0b7f Now have configurations to switch between supporting RVVI over ethernet. 2024-07-22 10:51:13 -05:00
Jacob Pease
b6fac581f7 Corrected the CRC7 code with the right sequence of instructions. 2024-07-22 01:19:10 -05:00
Jacob Pease
e91d2c8b14 Corrected the CRC7 code with the right sequence of instructions. 2024-07-22 01:19:10 -05:00
Jacob Pease
cc32e90f66 Added inital spi based sd card code. Working on CRC7 code that works. 2024-07-20 14:00:43 -05:00
Jacob Pease
c7d869bc96 Added inital spi based sd card code. Working on CRC7 code that works. 2024-07-20 14:00:43 -05:00
Rose Thompson
00840e4893 Made the fpga top level configurable between rvvi synth and not. 2024-07-19 17:35:30 -05:00
Rose Thompson
9471dcd296 Refactored the fpga and testbench so the RVVI can be synthesized cleanly and simulated without any major code changes. 
Adds three new configuration parameters to control enabling the RVVI packetizer and how much latency should exist between packets and the initial startup delay.
 2024-07-19 17:08:47 -05:00
Rose Thompson
0d40b8c933 Cleanup in prep to merge the rvvi branch into main. 2024-07-19 15:48:20 -05:00
Jacob Pease
6018ab82ab Added tentative spi_send_byte function. 2024-07-19 12:30:32 -05:00
Jacob Pease
53b2a51c89 Added tentative spi_send_byte function. 2024-07-19 12:30:32 -05:00
Jacob Pease
5123a43ba2 Added initial spi code to fpga/zsbl 2024-07-19 11:35:12 -05:00
Jacob Pease
34e89e842c Added initial spi code to fpga/zsbl 2024-07-19 11:35:12 -05:00
Ross Thompson
c72f0fd504 Added csr comparison. 2024-07-11 10:49:06 -05:00
Ross Thompson
abf9da01ab code cleanup. 2024-07-11 10:41:34 -05:00
Ross Thompson
f0096f5a43 Yay. It's actually working! The FPGA/ImperasDV hybrid is working. 2024-07-10 15:10:37 -05:00
Ross Thompson
e6dc962d11 Yay! the trigger is correctly working now! 2024-07-10 12:05:10 -05:00
Ross Thompson
cf986b5fb8 Really close to having the trigger in module work. 
Can trigger on the data of the correct frame, but trigger in is still not
working.
 2024-07-09 19:04:51 -05:00
Ross Thompson
6734685333 Fixed connection bugs in the top level fpga which preventing sending ethernet frames back to the trigger in unit. 2024-07-09 19:04:18 -05:00
Ross Thompson
e0a1f0e39f Really close now. 2024-07-09 14:21:43 -05:00
Ross Thompson
e488ee7225 Correctly sending the ethernet frame on a mismatch. Now just need to get vivado to actually trigger. 2024-07-09 14:16:13 -05:00
Ross Thompson
fd170a6583 Getting closer. 2024-07-09 14:09:56 -05:00
Ross Thompson
bf69a2e1cd Updated to use the newest imperasDV. 2024-07-09 12:30:18 -05:00
Jordan Carlin
e6e070f4e4 Update python shebangs to use /usr/bin/env python3 so virtual environment can be used (also aids in general portability) 2024-07-03 20:42:55 -07:00
Jordan Carlin
7419689359
Update python shebangs to use /usr/bin/env python3 so virtual environment can be used (also aids in general portability) 2024-07-03 20:42:55 -07:00
Ross Thompson
dc97ee5f82 Have some sample code which I know works transmisting a packet. 2024-07-02 09:12:34 -07:00
Ross Thompson
ccf4bb8ddc Maybe have the incircuit trigger working. 2024-06-26 16:15:46 -07:00
Ross Thompson
612a281f62 Added module to receive ethernet frame and trigger the ila. 2024-06-26 11:05:31 -07:00
Ross Thompson
74189e1e4b Have vivado triggering the ILA after the mismatch but the latency is way too long. 2024-06-25 17:04:14 -07:00
Ross Thompson
fa26c9a8b5 Added pipe to vivado to create ila trigger from rvvidaemon. 2024-06-25 13:07:46 -07:00
Ross Thompson
249d58244a It's working!!!!!! 2024-06-20 15:48:30 -07:00
Ross Thompson
1c6ebb86a3 Added some debug code to count frames sent to the ethernet mac and frames sent to the phy. 
Removed the external reset of the phy and now it always reliably starts in the same way.  The first 0x117 frames are always captured.
 2024-06-20 12:54:12 -07:00
Ross Thompson
ab1ee3d69b Removed *** from IFU, lrcs. 2024-06-19 09:40:35 -07:00
Ross Thompson
c5dac4d775 Removed *** from fpga top. 2024-06-19 09:28:21 -07:00
Ross Thompson
93829ce509 Success! We have some instructions comparing across the FPGA and IDV! 
However I'm still losing ethernet frames.
 2024-06-17 13:41:40 -07:00
Ross Thompson
598770da51 Getting much closer to a working version. 2024-06-17 12:37:10 -07:00
Ross Thompson
82b54c0887 Got IDV properly initalized. 2024-06-17 09:15:59 -07:00
Ross Thompson
47523c97ac Getting closer to figuring out the lost ethernet frame bugs. 2024-06-13 15:46:54 -07:00
Ross Thompson
c9f51df34a Fixed bug in rvvi reset. 2024-06-12 14:47:32 -07:00
Ross Thompson
323dbd348e Progress. 2024-06-12 12:54:21 -07:00
Ross Thompson
f5d4db68b1 Modified rvvidaemon to populate a struct with all the relavent fields. 2024-06-12 08:56:16 -07:00
Ross Thompson
3e7d07dfb6 Better. 2024-06-11 17:14:59 -07:00
Ross Thompson
8bce2fc739 Getting closer. 2024-06-11 16:21:53 -07:00
Ross Thompson
c9f3da51cb getting closer to full reconstruction of rvvi. 2024-06-11 15:35:35 -07:00
Ross Thompson
3d9f796f21 Better parsing of rvvi. 2024-06-11 14:36:34 -07:00
Ross Thompson
563980443a Merge branch 'main' into rvvi 2024-06-10 18:10:23 -07:00
Ross Thompson
49912589f5 Added rvviApi.h to rvvidaemon. 2024-06-10 17:57:24 -07:00
Ross Thompson
e16cf9d739 Added Makefile to compile rvvidaemon 2024-06-10 16:56:53 -07:00
Rose Thompson
72c1374d9c Minor code cleanup. 2024-06-04 15:11:57 -05:00
Rose Thompson
f0ed780745 progress. 2024-06-04 15:11:03 -05:00
Rose Thompson
07d66c246c Update. 2024-06-04 11:59:17 -05:00
Rose Thompson
08ff88f428 On the way towards complete reconstruction of the RVVI trace. 2024-06-04 11:47:46 -05:00
Rose Thompson
80f98b3223 now have a working ethernet daemon to collect frames and partially decode into RVVI. 2024-06-04 10:20:51 -05:00
Jacob Pease
7a417d7a6c Added true bootloader to fpga/zsbl directory. 2024-05-31 15:28:25 -05:00
Rose Thompson
6a4c8667df Added new signals to ILA to debug the RVVI tracer. 
The tracer appears to be stuck and the CPU is never getting out of (into reset).
 2024-05-30 16:43:25 -05:00
Rose Thompson
38ddbf860e Fixed bug with mmcm not generating the 4th clock. 2024-05-30 16:19:28 -05:00
Jacob Pease
3f7659c8ad Removed old fpgaTop.v file. 2024-05-30 16:15:19 -05:00
Jacob Pease
7ecd1c7d5f The vcu108 works again. Added renumber.py script that renumbers probes in an xdc file. 2024-05-30 15:48:27 -05:00
Rose Thompson
9703055758 The FPGA is synthesizing with the rvvi and ethernet hardware. 2024-05-30 15:37:17 -05:00
Rose Thompson
8123695831 Maded insert_debug_comment.sh compatible with cygwin. 2024-04-22 10:48:34 -05:00
Rose Thompson
3bed733301 Fixed fpga to work with the updated regression changes. 2024-04-22 10:42:01 -05:00
Rose Thompson
c1221e6608 Fixed insert_debug_comment.sh to work with the older version of bash. 2024-04-16 10:55:26 -05:00
Rose Thompson
6097444b5a Added missing file for compiling the fpga zero stage bootloader. 2024-04-11 10:30:56 -05:00
Rose Thompson
60f96112db Moved the zero stage boot loader to the fpga directory. 2024-03-01 10:23:55 -06:00
Rose Thompson
cc7f433ce0 Update the fpga scripts to use the new derivative configs. 2024-01-31 13:19:28 -06:00
David Harris
45e2317636 Added Wally github address to header comments 2024-01-29 05:38:11 -08:00
Rose Thompson
7693c5d4e2 Updates to fpga top level. 2023-12-15 15:32:05 -06:00
Rose Thompson
26cd22c388 Replaced fpga's verilog top with system verilog. 2023-12-15 13:42:52 -06:00
Rose Thompson
dab9d7ab3c Replaced fpga top level verilog with system verilog. 2023-12-15 13:07:08 -06:00
Rose Thompson
34631c54d3 Get's the fpga building again after the git history rewrite. 2023-12-14 17:08:25 -06:00
Jacob Pease
7e494f2d3b Removed vivado property from rom1p1r.sv. It's now dynamically added using the FPGA makefile. 2023-12-01 18:59:18 -06:00
Jacob Pease
71066cae12 Modified FPGA Makefile to override with relative path. FPGA boots now. 2023-11-30 17:51:15 -06:00
Rose Thompson
b137759b45 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-11-20 10:34:36 -06:00
Rose Thompson
cdd21d6635 Added menvcfg to debugger for checking what linux has configured. 2023-11-19 13:44:22 -06:00
Jacob Pease
87e6a5ccf2 Updated ROM to preload bootloader from file and infer a block ram when building for FPGA. 2023-11-18 19:15:39 -06:00
Jacob Pease
ff73f798ed Replaced vivado-risc-v addins directory with new SDC repo. 2023-11-16 13:59:12 -06:00
Rose Thompson
d4bc9da085 Fixed another bug in the updated script changes. 2023-11-13 18:12:02 -06:00
Rose Thompson
f8b65f50b0 Fixed bugs in the updated fpga synthe script. 2023-11-13 18:10:22 -06:00
Rose Thompson
d5f0c15b90 Modified the fpga build script to generate it's own config file rather than use the one in config/fpga. 2023-11-13 17:48:28 -06:00
Rose Thompson
6b7ff50a84 Reduced Arty A7 clock speed to 20Mhz to support Zicclsm. 2023-11-13 16:44:02 -06:00
Ross Thompson
d33c966a42 Changed SDC outputs to ensure they are aligned to the falling edge of the divided down clock rather than the processor clock. 2023-10-10 17:46:12 -05:00