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https://github.com/openhwgroup/cvw
synced 2025-01-23 21:14:37 +00:00
Removed old axi IP from fpga Makefile. Added sed for data.mem file loaded into uncore ram.
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parent
36d330a173
commit
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@ -1,14 +1,14 @@
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dst := IP
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# vcu118
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#export XILINX_PART := xcvu9p-flga2104-2L-e
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#export XILINX_BOARD := xilinx.com:vcu118:part0:2.4
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#export board := vcu118
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# export XILINX_PART := xcvu9p-flga2104-2L-e
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# export XILINX_BOARD := xilinx.com:vcu118:part0:2.4
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# export board := vcu118
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# vcu108
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#export XILINX_PART := xcvu095-ffva2104-2-e
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#export XILINX_BOARD := xilinx.com:vcu108:part0:1.2
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#export board := vcu108
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# export XILINX_PART := xcvu095-ffva2104-2-e
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# export XILINX_BOARD := xilinx.com:vcu108:part0:1.7
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# export board := vcu108
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# Arty A7
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export XILINX_PART := xc7a100tcsg324-1
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@ -40,11 +40,11 @@ IP_Arty: $(dst)/xlnx_proc_sys_reset.log \
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$(dst)/xlnx_ddr3-$(board).log \
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$(dst)/xlnx_mmcm.log \
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$(dst)/xlnx_axi_clock_converter.log \
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$(dst)/xlnx_ahblite_axi_bridge.log \
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$(dst)/xlnx_axi_crossbar.log \
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$(dst)/xlnx_axi_dwidth_conv_32to64.log \
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$(dst)/xlnx_axi_dwidth_conv_64to32.log \
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$(dst)/xlnx_axi_prtcl_conv.log
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$(dst)/xlnx_ahblite_axi_bridge.log
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#$(dst)/xlnx_axi_crossbar.log \
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#$(dst)/xlnx_axi_dwidth_conv_32to64.log \
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#$(dst)/xlnx_axi_dwidth_conv_64to32.log \
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#$(dst)/xlnx_axi_prtcl_conv.log
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PreProcessFiles:
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@ -59,6 +59,7 @@ PreProcessFiles:
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# This line allows the Bootloader to be loaded in a Block RAM on the FPGA
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sed -i "s/bit \[DATA_WIDTH-1:0\].*ROM.*/(\* rom_style=\"block\" \*) &/g" ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv
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sed -i 's/$$WALLY/\.\.\/\.\.\/\.\.\//g' ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv
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sed -i 's/$$WALLY/\.\.\/\.\.\/\.\.\//g' ../src/CopiedFiles_do_not_add_to_repo/generic/mem/ram1p1rwbe.sv
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$(dst)/%.log: %.tcl
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mkdir -p IP
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