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Added option to use rvvi ila
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@ -90,6 +90,7 @@ write_verilog -force -mode funcsim sim/syn-funcsim.v
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if {$board=="ArtyA7"} {
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source ../constraints/small-debug.xdc
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#source ../constraints/small-debug-rvvi.xdc
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} else {
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# source ../constraints/vcu-small-debug.xdc
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