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224 Commits

Author SHA1 Message Date
Rose Thompson
62eaca0e6e Almost working ImperasDV with testbench.sv and wally.do. For some reason IDV is saying the instructions are mismatching. 2024-05-16 17:01:25 -05:00
Rose Thompson
8391b8b821 Progress towards unified regression. 2024-05-16 15:29:12 -05:00
Rose Thompson
08601d7270 Added functionallity to testbench.sv for single elf files. 2024-05-16 13:59:15 -05:00
Rose Thompson
ceb31fec68 Merge branch 'main' of https://github.com/openhwgroup/cvw 2024-05-10 08:54:23 -05:00
Rose Thompson
b027fa44ef Merge branch 'main' of https://github.com/openhwgroup/cvw 2024-05-10 08:53:00 -05:00
Rose Thompson
4bd5d334df Modified testbench so it instantiates the function logger if DEBUG is greater than 0 rather than just 1. 2024-05-10 08:51:59 -05:00
David Harris
66b33c09be Added Zaamo and Zalrsc support to testbench and regression 2024-05-10 05:41:00 -07:00
David Harris
bdd0043cd1 Testbench terminates buildroot sim at instruction limit 2024-05-09 07:58:53 -07:00
David Harris
47af54b131 Fixed buildroot prematurely terminating in VCS 2024-05-09 07:29:45 -07:00
Divya2030
31ae18922b regression_wally vcs run works 2024-05-08 04:25:03 -07:00
Divya2030
a3f1a274d2 VCS Simulation Passed 2024-05-07 10:41:02 -07:00
David Harris
06d3591a15 Divy's change for VCS signature checking 2024-05-04 02:45:43 -07:00
Divya2030
ee566aa856 pmp coverage 2024-05-02 11:53:04 -07:00
Divya2030
7a5eac963e Revert "pmp functional coverage basic" 
This reverts commit db2b07b05d.
 2024-05-02 11:43:33 -07:00
Divya2030
9f27f3fe28 Merge branch 'main' of github.com:Divya2030/cvw 2024-05-02 11:21:05 -07:00
Divya2030
db2b07b05d pmp functional coverage basic 2024-05-02 11:20:03 -07:00
David Harris
e667adf946 Added covergen directed coverage generator 2024-05-01 14:47:37 -07:00
David Harris
6415bfc3c2 Code and testbench cleanup 2024-04-23 10:17:44 -07:00
David Harris
f9eec8c43f Merged wsim changes 2024-04-22 13:11:35 -07:00
Kunlin Han
9be0303493 Add support for dumping vcd. 2024-04-22 13:03:51 -07:00
David Harris
26711083df Flushing uart.out file to observe progress 2024-04-21 20:08:35 -07:00
David Harris
03f49dea3f regression printing improvements 2024-04-21 19:45:09 -07:00
David Harris
be15a11622 Fixed conflicts on getenv 2024-04-21 08:38:13 -07:00
David Harris
00a1c0fc57 Fixed WALLY/RISCV paths in testbench/rom1p1r; search log files for warnings and errors 2024-04-21 00:02:15 -07:00
David Harris
1817ab2e11 testbench import is happy now for Questa, but throws lint warning for VCS 2024-04-20 23:13:13 -07:00
David Harris
fd6a6b2249 environment variable cleanup 2024-04-20 22:52:08 -07:00
David Harris
a1876b1e7c script cleanup 2024-04-20 17:22:31 -07:00
David Harris
338f37b570 Moved getenv/getenvval declaration to config-shared so lint and regression both run 2024-04-20 17:19:42 -07:00
slmnemo
f0229e970b Fixed getenvvar verilator bug in rom1p1r, Removed unused system function from testbench. 2024-04-20 17:07:54 -07:00
slmnemo
66a002d879 Removed unused rmCmd string declaration 2024-04-20 16:58:23 -07:00
slmnemo
354d447269 Changed testbench to use fopen instead of opening and closing uartfile whenever writing 2024-04-20 16:56:54 -07:00
Kunlin Han
29c19d9cb4 Add system function through DPI to avoid missing support in Verilator. 2024-04-16 11:23:00 -07:00
Rose Thompson
1eb1beed95 Fixed merge conflict bug in the last pull request. 2024-04-16 10:32:24 -05:00
Rose Thompson
9fe86712d8
Merge branch 'main' into wsim_verilator 2024-04-16 09:07:50 -05:00
David Harris
160162c98a
Merge pull request #728 from Karl-Han/verilator_getenv 
Add support for getenvval as wrapper for Verilator's getenv
 2024-04-15 17:55:34 -06:00
slmnemo
39ae26a897 Added documentation for known Verilator hierarchy bug 2024-04-15 15:58:09 -07:00
slmnemo
4b80457f3e Fixed issue with Verilator hierarchical referencing by changing module names, moved run-imperas-linux to correct directory 2024-04-12 21:58:20 -07:00
slmnemo
342c99d6ea Rearranged uart_logger block to only generate if UART is supported 2024-04-12 21:30:33 -07:00
Kunlin Han
eeb5c59143 Remove unnecessary sig and avoid uninitialized signal inside always block. 2024-04-12 16:06:10 -07:00
Kunlin Han
4d9de94029 Add support for getenvval as wrapper for Verilator's getenv. 2024-04-12 14:59:04 -07:00
Rose Thompson
bb072fba84 Fixed the buildroot issue. 2024-04-06 18:25:53 -05:00
Rose Thompson
46fdfde7ec Removed unnecessary display from testbench. 2024-04-06 16:10:18 -05:00
David Harris
e8111da88a Removed unused old regression-wally 2024-04-06 13:47:44 -07:00
David Harris
6b844a2e6e Added GUI support and removed unused wave files 2024-04-06 13:43:06 -07:00
David Harris
3c855e3e90 Passing arguments to buildroot, not yet checking result correctly 2024-04-06 11:42:41 -07:00
David Harris
b3f007ec7f Working on buildroot in regression 2024-04-06 11:11:22 -07:00
David Harris
ac9a21873d Pass TEST to testbench with +TEST=<name> rather than -G TEST=<name> so that we don't have to recompile for every new test 2024-04-06 10:34:21 -07:00
slmnemo
d107a42e8c Replaced rewrite command with system rm command for uart file. Fixed comment on line 573 2024-04-05 21:39:41 -07:00
slmnemo
2fcae601a9 Replaced funky rewrite call with file removal 2024-04-05 20:59:08 -07:00
slmnemo
3ee25c8936 Merged testbench changes 2024-04-05 17:20:03 -07:00