James E. Stine
cfb27de8a3
Fix Issue #541 where FlagMatch was not added which I forgot (apologies)
2024-01-09 08:57:41 -06:00
James E. Stine
f91b749f91
Fix typo missed with === on Issue #541
2024-01-08 22:01:52 -06:00
James E. Stine
79d7bb60ea
Address Issue #541 where CVTINT or CMP in testfloat were not checked. The solution was to check inside the nested for loop. This was done to avoid issue related to the values changing between each cvtint or subsequent operation
2024-01-08 21:28:47 -06:00
David Harris
d93684be21
Verilate running (slowly)
2024-01-07 21:30:33 -08:00
David Harris
7cd02351d9
Updated testbench to count size of signature without searching for x. Now runs with Verilator.
2024-01-07 09:00:19 -08:00
David Harris
caedab679a
Rewrote testbench to count signature entries rather than looking for x; this will facilitate Verilator which does not use x
2024-01-07 07:14:12 -08:00
David Harris
34f97201ee
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2024-01-06 08:19:56 -08:00
David Harris
167e061a1c
Fixed truncated begin_signature in testbench
2024-01-06 08:19:46 -08:00
Rose Thompson
ab07d64195
Fixes coremark. Maybe works with verilator.
2024-01-06 00:41:57 -06:00
David Harris
ed623f1a71
Fixed unsupported riscof YAML string; preparing for Verilator -G testcase
2024-01-05 20:06:21 -08:00
David Harris
d229dc06ee
Coverage improvements; remove incorrect logic checking NAPOT nonleaf PTE
2024-01-02 00:35:17 -08:00
David Harris
52b6d1d163
restored tlbNAPOT coverage tests
2023-12-31 09:55:58 -08:00
David Harris
b3ff1035c4
Propagated MIP-based tracer interrupts to testbench-linux-imperas
2023-12-21 11:47:49 -08:00
David Harris
45b5658d06
Updated Imperas testbench to use MIP bits to communicate pending interrupts
2023-12-21 11:05:26 -08:00
David Harris
8552369687
Merged PR538, delete unused tests
2023-12-20 13:30:31 -08:00
Rose Thompson
70d0169019
All regression tests which matter are running!
2023-12-20 14:57:52 -06:00
Rose Thompson
1b59182d59
Updated tests with ending label.
2023-12-20 14:55:37 -06:00
Rose Thompson
b68dd74f89
Reverted logic to bit change.
2023-12-20 13:16:32 -06:00
Rose Thompson
a8ab3c8342
Ok that is a stange bug.
...
The testbench used logic for the shadow ram, but the memory used bit. This caused questa to allocate huge amounts of memory and crash. Changing shadow ram to bit fixed the issue.
2023-12-20 12:25:34 -06:00
Rose Thompson
9ee1ffe8fe
Almost working with modelsim and verilator.
2023-12-20 11:29:31 -06:00
David Harris
5dbca251d8
Defined new Zicboz and Zcb tests
2023-12-19 13:24:11 -08:00
Rose Thompson
4f59bd492d
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-12-19 12:06:04 -06:00
Rose Thompson
2e792606dd
More progress. Most tests are passing in modelsim.
2023-12-19 12:06:00 -06:00
Rose Thompson
74238defc3
Progress.
2023-12-18 20:23:19 -06:00
David Harris
6186181d46
Merge pull request #537 from ross144/main
...
Almost having working Verilator. One issue in the testbench remains.
2023-12-18 18:13:56 -08:00
Rose Thompson
1e1759c258
Restored the one hack change which prevents verilator from working.
2023-12-18 17:00:53 -06:00
Rose Thompson
408bb2c35b
Yay! I got verilator to compile our testbench! Does it actually work I don't know.
2023-12-18 16:44:34 -06:00
Rose Thompson
0f7b6ada04
Cleanup.
...
Verilator still has issues with riscassertions.sv and the testbench
2023-12-18 16:38:56 -06:00
Rose Thompson
b7b245fe2f
functionName.sv is now linting for rv64gc.
2023-12-18 16:37:26 -06:00
Rose Thompson
c1ac153a4f
Closer to verilator support.
2023-12-18 16:26:56 -06:00
Rose Thompson
58942b246b
Kind of a frustrating set of changes to get the verilator errors out of the copyShadow module.
2023-12-18 13:34:14 -06:00
Rose Thompson
4a3cc8b9c8
More progress towards verilator.
2023-12-18 13:26:43 -06:00
Rose Thompson
5062a8c89c
Added parameter for cache's SRAM length.
...
Progress towards verilator support.
2023-12-18 12:50:49 -06:00
David Harris
6ba3ae662f
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-12-17 19:04:50 -08:00
James E. Stine
f4c1713ed4
Fix issue with running all and then going from one operand width to another. Issue is due to signals resolving between sizes. I did not catch it before because I did not run through the complete exhaustive tests. This time, went through all tests and tested all the data sizes.
2023-12-17 20:55:06 -06:00
David Harris
6cb4a9e905
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-12-15 19:27:10 -08:00
David Harris
a138ef37b1
Switched to using riscv-arch-test rv32e_m suite. Need to rename it from rv32e_unratified (PR pending)
2023-12-15 19:26:50 -08:00
James E. Stine
8d8bad61d4
Fix to take care of Issue #507 . Issue was caused with time delay in testbench-fp.sv that interfered with the if statement in the DIVSQRT condition for generating a vector. This original time delay was given to guarantee that the previous operation would complete. However, the testbench was modified to make sure this would not happen and this time delay is not needed obviating any issue that caused Issue #507 . Some other small enhancements were made to the testbench-fp.sv for beautification, as well. A full test was run on the testbench to check its validity.
2023-12-15 17:02:11 -06:00
David Harris
38f4d9baf8
Use riscv-arch-test arch32e instead of outdated wally-riscv-arch-test wally32e
2023-12-15 05:05:53 -08:00
David Harris
68d96a929c
Fixed hierarchical path to EcallFaultM in testbench
2023-12-13 16:37:54 -08:00
David Harris
ff26baf7e8
Rolled back attempt to support Verilator
2023-12-13 12:53:44 -08:00
David Harris
aff61ea97a
Fixed Linux makefile; load branch predictor RAMs at startup for sim; fixed comment in trap; starting to make testbench more compatible with Verilator
2023-12-13 11:33:59 -08:00
David Harris
b268a3b9d3
Added SPI support to Imperas testbenches
2023-12-07 09:44:31 -08:00
David Harris
c0801263f1
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-11-23 20:43:22 -08:00
David Harris
bcc20c6bd5
Merge pull request #505 from stineje/main
...
Update fix for cvtint testbench-fp
2023-11-23 20:43:00 -08:00
David Harris
3df4c13daa
Updated wallyTracer for Linux boot and wally-batch.do to remove buildroot checkpoint support
2023-11-23 20:36:45 -08:00
David Harris
1f57df7f8b
Fixed reference to deleted atomic signal in cache
2023-11-23 20:29:10 -08:00
James E. Stine
1ab7522064
Update fix for cvtint testbench-fp
2023-11-23 17:56:51 -06:00
Rose Thompson
1dac4d221e
Disable the trace for normal operation.
2023-11-21 13:49:07 -06:00
Rose Thompson
c77a47b403
Output the instruction trace to the logs directory.
2023-11-21 13:47:58 -06:00
