140 Commits

Author	SHA1	Message	Date
David Harris	8a910aabf4	Documentation and comment fixes	2024-11-27 05:42:39 -08:00
David Harris	028ffe9f4a	Removing obsolete ***	2024-11-20 07:23:51 -08:00
David Harris	147f62d9a5	Fixed timer offset in RV32 WALLY-wfi; simplified in RV64 WALLY-wfi	2024-11-17 06:43:13 -08:00
David Harris	205db4348c	Fixed cause_m_time_interrupt most significant byte	2024-11-16 18:31:02 -08:00
naichewa	73c2165756	recommit sckmode 10 11 delay regression tests	2024-11-05 11:30:13 -08:00
naichewa	9822902a4f	Revert "Added SCKMODE 10 and 11 delay cases to regression tests" ... unwanted submodule changes This reverts commit 38a88862ac.	2024-11-05 11:17:01 -08:00
naichewa	38a88862ac	Added SCKMODE 10 and 11 delay cases to regression tests	2024-11-04 16:22:42 -08:00
naichewa	3fda7ecb81	Fix SPI regression tests	2024-11-01 13:09:41 -07:00
naichewa	960d72295c	Removed SPI hardware interlock test cases	2024-11-01 11:27:41 -07:00
Rose Thompson	8fb1673ab3	Updated email address authorship for my files.	2024-10-15 10:27:53 -05:00
naichewa	3b7661dfd5	SckDiv Zero bug fixes	2024-09-03 14:58:46 -07:00
Jacob Pease	d8b75440b6	With Naiche's help, we fixed the SPI controllers clock polarity and phase settings. Added conditions to the SPI regression tests.	2024-08-20 16:24:37 -05:00
Rose Thompson	6110799a1e	Updated the wally rv32 priv tests to not use sail.	2024-02-16 11:39:06 -06:00
naichewa	8b60992e72	fixed SPI tests failing when no icache	2024-01-17 14:38:11 -08:00
Rose Thompson	1b59182d59	Updated tests with ending label.	2023-12-20 14:55:37 -06:00
Rose Thompson	418ae0decc	Fixed some regression tests with David's help.	2023-12-19 14:18:21 -06:00
David Harris	6c017141c5	Renamed HADE to ADUE for Svadu	2023-12-13 11:49:04 -08:00
naichewa	d67badfc60	fix hardware interlock, hold mode deassert	2023-11-08 15:20:51 -08:00
naichewa	a5837eb62c	fifo fixes and edge case testing	2023-11-07 17:59:46 -08:00
naichewa	7dd3f24d6c	Merge branch 'main' into spi	2023-10-30 17:01:41 -07:00
Rose Thompson	0fd5b3b2ce	Updated comments in the cboz tests.	2023-10-20 15:15:47 -05:00
Rose Thompson	5a4028064a	Updated comments for the cbom tests.	2023-10-20 15:13:52 -05:00
naichewa	0ff9ce527d	Merge branch 'main' into spi	2023-10-16 22:59:50 -07:00
David Harris	ac4216b43d	Incorporated new AMO tests from riscv-arch-test	2023-10-16 10:25:45 -07:00
David Harris	6245748ed7	Added CSR permission tests for mconfigptr, menvcfg, mseccfg, etc.	2023-10-15 15:31:03 -07:00
David Harris	b4891d88db	Added WALLY minfo test for rv32	2023-10-15 06:48:22 -07:00
naichewa	f231c3d3a3	correct delay0, fmt register test entries	2023-10-12 15:13:23 -07:00
naichewa	d5d4f9d044	transferred spi changes in ECA-authorized commit	2023-10-12 13:36:57 -07:00
David Harris	d526d28804	Added MENVCFG.HADE bit and updated SVADU to depend on this bit	2023-10-04 09:34:28 -07:00
David Harris	8d3ff59673	Completed basic tests of svnapot and svpbmt	2023-08-28 06:57:35 -07:00
Ross Thompson	cd3349bd26	Added rv32 cboz test.	2023-08-24 17:02:53 -05:00
Ross Thompson	7d51690b7c	Oups forgot to include the 32-bit cbom test in previous commit.	2023-08-24 09:04:41 -05:00
David Harris	c137a1c8cf	Fixed timer interrupt testing	2023-06-09 17:20:41 -07:00
David Harris	f68b9c224a	Fixed WALLY-trap test case to use menvcfg	2023-06-09 15:24:26 -07:00
David Harris	b70b0c7c5e	Added support for menvcfg and senvcfg, including menvcfg.STCE for supervisor timer compare	2023-06-09 14:40:01 -07:00
David Harris	19096a812a	Added Zifencei ISA to tests where necessary to support new compiler	2023-05-16 11:18:27 -07:00
David Harris	0a7a159d69	Added Zicsr and zifencei to RVTEST_ISA in custom tests where necessary to make them compile	2023-05-14 06:58:29 -07:00
Kip Macsai-Goren	34200e8c76	restored original virt mem tests when svadu is not supported	2023-04-11 18:47:08 -07:00
Kip Macsai-Goren	c4766c8a02	renamed virt mem tests to include svadu	2023-04-11 18:46:37 -07:00
Kip Macsai-Goren	a82c0a7780	Modified virt mem tests to do correct r/w when svadu is enabled	2023-04-11 18:08:30 -07:00
Kip Macsai-Goren	a899606c2b	Removed Sail from virt mem tests due to sail not recognizing SVADU	2023-04-11 17:41:31 -07:00
Kip Macsai-Goren	19305fe60a	Added sail simulation to priv tests that support it	2023-04-11 13:26:59 -07:00
David Harris	e8904411ce	Fixed PMP issue 132. Updated tests to initialize PMP before using. Needs to remake tests	2023-03-28 06:58:17 -07:00
Kip Macsai-Goren	758da62a9f	ported fixes to 32 bit tests	2023-03-24 11:22:39 -07:00
Kip Macsai-Goren	db6caedfec	added in the CSR name for stimecmp(h)	2023-03-04 15:53:03 -08:00
Kip Macsai-Goren	ab6b953a4b	removed changes to counteren from stimecmp tests	2023-03-04 15:46:57 -08:00
Kip Macsai-Goren	ac5c53a870	Added correct causing and handling of S time interrupts to test suite.	2023-03-04 15:04:17 -08:00
David Harris	f0c0111ab0	Renamed section 12.3 to 8.3 in MMU test definitions	2023-02-19 05:46:46 -08:00
Kip Macsai-Goren	ee1bcf62ee	Fixed regression test dependance on bp status by adding handling of UART tx empty interrupts.	2023-01-28 17:29:35 -08:00
Kip Macsai-Goren	964084f0b3	added fs=00 to status fp enabled test	2022-12-22 15:15:53 -08:00