Ross Thompson
055e00b8ac
Pushed vcu118 to 71MHz.
2023-08-25 17:04:50 -05:00
Jacob Pease
2bf6207919
Added help option to the flash-sd script.
2023-08-22 13:37:33 -05:00
Ross Thompson
cab40e618f
Updateds to vcu118 constraints and device tree.
2023-08-02 16:51:32 -05:00
Ross Thompson
fb1c1a1832
Added new signals to the vcu118 debug4 ila to help figure out why the new linux build's hptw fails.
2023-08-02 16:14:04 -05:00
Ross Thompson
c4ae856f92
Clean up vcu118 synth scripts.
2023-08-01 14:39:33 -05:00
Ross Thompson
06efd2cdde
Pushed performance of arty a7 to 23Mhz.
2023-07-31 14:13:09 -05:00
Jacob Pease
9d33e08dbb
Removed non-existent SDC dependency from VCU targets in FPGA Makefile.
2023-07-27 15:01:20 -05:00
Ross Thompson
b1f7a5768f
Removed all old references to the old flash card controller.
...
Added git submodule for the flash card in addins.
Replicated flash card top level for our changes into the fpga/src directory.
2023-07-24 15:45:57 -05:00
Ross Thompson
49b87d4550
Merge branch 'main' of github.com:ross144/cvw
2023-07-24 10:47:05 -05:00
Ross Thompson
065e5e98c9
Improved timing constraints for arty a7 to push clock speed to 20Mhz.
2023-07-24 10:46:49 -05:00
Ross Thompson
ab6ef5bb58
At least it simulates and gets through fpga elaboration.
2023-07-21 18:40:26 -05:00
Ross Thompson
a89a1e675c
Merge branch 'boot' into mergeBoot
...
Merges Jacob's new sdc controller into wally.
2023-07-21 17:43:45 -05:00
Jacob Pease
380d96b359
Working new boot process. Buildroot package for sdc.
2023-07-20 14:15:59 -05:00
Ross Thompson
2752e5de4c
Fixed a bunch of timing constraints for the arty a7 board.
2023-07-19 17:08:16 -05:00
Ross Thompson
b756b248b4
Wow. The newest version of Vivado does not like the enums as parameters.
...
The solution is simple. I changed the type to logic [31:0] and defined macros for the branch predictor types as 32 bit integers.
2023-07-18 15:07:10 -05:00
Ross Thompson
a8f11dcad0
FPGA updates.
2023-06-20 11:11:34 -05:00
Ross Thompson
af187d96ca
Updated fpga wave config.
2023-06-19 12:28:30 -05:00
Ross Thompson
1a23f1360f
Updated fpga wally wrapper to work with the ILA.
2023-06-19 12:15:48 -05:00
Ross Thompson
0423d7df82
I think the fpga is building again, but the debugger script needs to be updated. For some reason the nets are not present despite being marked debug.
2023-06-16 17:00:27 -05:00
Ross Thompson
443c568994
Vivado requires an intermediate wrapper file for parameterization.
2023-06-16 16:30:14 -05:00
Ross Thompson
c44d4321fb
FPGA synthesis is broken. This commit moves closer to fixing the issues causes by parameterization.
2023-06-16 15:40:13 -05:00
Jacob Pease
40f81d5da6
The Vivado-RISC-V SDC works. Wally is now booting through it.
2023-05-26 15:42:33 -05:00
Ross Thompson
6907f0ccc1
FPGA makefile update.
2023-04-25 16:24:26 -05:00
Ross Thompson
f22e6d0e48
Updated fpga Makefile to work with both the Arty and VCU platforms.
2023-04-21 11:08:35 -05:00
Jacob Pease
2839f4f41a
AHB triggers write, but AXI side doesn't update.
2023-04-18 15:23:22 -05:00
Ross Thompson
3588c53e66
It's almost working.
2023-04-18 14:24:59 -05:00
Ross Thompson
deb0bfc24d
Improved constraints and set ddr3 voltage to correct 1.35V. This voltage is only for synthesis. However I'm concerned because the gui did not let me select 1.35V.
2023-04-17 20:05:59 -05:00
Ross Thompson
b0f0fb1da7
Adding in the ILA to the arty a7.
2023-04-17 14:54:10 -05:00
Ross Thompson
30d017c258
Lowered arty a7 clock frequency to 15Mhz to meet timing. can probalby go faster.
2023-04-17 12:16:31 -05:00
Ross Thompson
fe692dacce
Finally got the arty a7 to build.
2023-04-17 11:54:22 -05:00
Ross Thompson
4ad33d7acc
OMG. the ddr3 has it's own mmcm (pll) which had incorreclty specified the input clock period as 3000 ps rather than 6000 ps so the pll was running at twice the speed. I speed the whole weekend on this. :(
2023-04-17 11:10:19 -05:00
Ross Thompson
5591b447d6
Fixed more issues with arty a7 constarints.
2023-04-16 13:25:02 -05:00
Ross Thompson
f4734c0d1b
Found and fixed the major architecture issue with the mig 7 used in the arty a7 board.
...
mig 7 is completely different from the ddr4 mig in that the internal pll does not general the required clocks. An external mmcm is required to general two inputs clocks and the required user clock.
2023-04-15 11:13:28 -05:00
Ross Thompson
2f8359e6cc
Realized we need a separate mmcm when using the mig 7 for ddr3 rather than the ddr4 mig. Go figure.
2023-04-14 18:02:16 -05:00
Ross Thompson
d967e05c20
Finally fixed the ddr3 mig script to work correclty.
2023-04-14 11:41:51 -05:00
Ross Thompson
777edb0fcd
Progress on arty a7 board.
2023-04-13 17:57:12 -05:00
Ross Thompson
e490ab09cf
Updated to help debut Jacob's crossbar woes.
2023-04-11 14:22:42 -05:00
Ross Thompson
c4e5b8db49
Updates for arty a7.
2023-04-10 17:02:19 -05:00
Ross Thompson
5bcb0f6ace
Fixed syntax errors in arty7 top level.
2023-04-10 16:08:40 -05:00
Ross Thompson
0700202001
Added more support for Arty A7 board.
2023-04-10 16:01:17 -05:00
Ross Thompson
9d9c2b170d
Finally building ddr3 xilinx ip from script.
2023-04-10 14:36:33 -05:00
Ross Thompson
e7f494ef95
Started putting together the arty a7 board package files.
2023-04-10 13:15:55 -05:00
Ross Thompson
6cdfbef2ca
Added Jacob's ILA script.
2023-04-06 15:32:36 -05:00
Jacob Pease
85d789a7e0
AXI Crossbar is working. Fixed address width in generator script.
2023-02-22 15:13:16 -06:00
Jacob Pease
45b264fa59
Merge branch 'main' of github.com:openhwgroup/cvw into boot
2023-02-16 17:36:26 -06:00
David Harris
78eb90715c
Removed pipelined level of hierarchy
2023-02-02 14:14:11 -08:00
Jacob Pease
07e279b5b5
Modified makefile. Added axi protocol converter IP.
2023-01-23 19:30:29 -06:00
Jacob Pease
293cc88bd9
Added extra core signal to mark_debug.txt. Modified wally.tcl
2023-01-23 17:00:24 -06:00
Jacob Pease
9b612fbf6c
Merge branch 'main' of github.com:openhwgroup/cvw into boot
2023-01-23 12:41:02 -06:00
Ross Thompson
0ed9811e31
Updated fpga constraints.
2023-01-20 20:16:33 -06:00
