cvw/fpga/generator
2023-04-10 14:36:33 -05:00
..
debug
bootrom.txt
insert_debug_comment.sh
Makefile Finally building ddr3 xilinx ip from script. 2023-04-10 14:36:33 -05:00
probe
wally.tcl
wave_config.wcfg
xlnx_ahblite_axi_bridge.tcl
xlnx_axi_clock_converter.tcl
xlnx_ddr3-artya7-mig.prj Started putting together the arty a7 board package files. 2023-04-10 13:15:55 -05:00
xlnx_ddr3-artya7.tcl Finally building ddr3 xilinx ip from script. 2023-04-10 14:36:33 -05:00
xlnx_ddr4-vcu108.tcl
xlnx_ddr4-vcu118.tcl
xlnx_ddr4.tcl
xlnx_proc_sys_reset.tcl