mirror of
https://github.com/openhwgroup/cvw
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f4734c0d1b
mig 7 is completely different from the ddr4 mig in that the internal pll does not general the required clocks. An external mmcm is required to general two inputs clocks and the required user clock. |
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.. | ||
debug | ||
bootrom.txt | ||
insert_debug_comment.sh | ||
Makefile | ||
probe | ||
wally.tcl | ||
wave_config.wcfg | ||
xlnx_ahblite_axi_bridge.tcl | ||
xlnx_axi_clock_converter.tcl | ||
xlnx_ddr3-artya7-mig.prj | ||
xlnx_ddr3-ArtyA7.tcl | ||
xlnx_ddr4-vcu108.tcl | ||
xlnx_ddr4-vcu118.tcl | ||
xlnx_ddr4.tcl | ||
xlnx_mmcm.tcl | ||
xlnx_proc_sys_reset.tcl |