cvw/fpga/generator
Ross Thompson f4734c0d1b Found and fixed the major architecture issue with the mig 7 used in the arty a7 board.
mig 7 is completely different from the ddr4 mig in that the internal pll does not general the required clocks. An external mmcm is required to general two inputs clocks and the required user clock.
2023-04-15 11:13:28 -05:00
..
debug Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile. 2022-10-24 15:38:39 -05:00
bootrom.txt
insert_debug_comment.sh
Makefile
probe
wally.tcl Found and fixed the major architecture issue with the mig 7 used in the arty a7 board. 2023-04-15 11:13:28 -05:00
wave_config.wcfg
xlnx_ahblite_axi_bridge.tcl
xlnx_axi_clock_converter.tcl
xlnx_ddr3-artya7-mig.prj
xlnx_ddr3-ArtyA7.tcl Finally fixed the ddr3 mig script to work correclty. 2023-04-14 11:41:51 -05:00
xlnx_ddr4-vcu108.tcl
xlnx_ddr4-vcu118.tcl
xlnx_ddr4.tcl
xlnx_mmcm.tcl
xlnx_proc_sys_reset.tcl