Noah Boorstin
c42c485377
busybear: instantiate soc instead of hart
2021-02-23 18:59:06 +00:00
David Harris
7737b0f709
Fixed fetch stall after jump in bus unit
2021-02-23 09:08:57 -05:00
David Harris
f372e2b8e8
Debugging Bus interface
2021-02-22 13:48:30 -05:00
kaveh pezeshki
e146946e58
Merge remote-tracking branch 'origin/tlb_toy' into busybear
2021-02-22 02:23:01 -08:00
Ross Thompson
c856003f73
RAS needs to be reset or preloaded. For now I just reset it.
...
Fixed bug with the instruction class.
Most tests now pass. Only Wally-JAL and the compressed instruction tests fail. Currently the bpred does not support compressed. This will be in the next version.
2021-02-19 20:09:07 -06:00
Ross Thompson
597dd1e7e6
Added FlushF to hazard unit.
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Fixed some typos with the names of signals in the branch predictor. They were causing signals to be not set. Note there is a modelsim flag which prevents it from compiling if a logic is undefined.
I will look this up and add it to the compiler.
2021-02-19 16:36:51 -06:00
Ross Thompson
06e975ac2f
minor change to wave file.
2021-02-19 09:08:13 -06:00
Ross Thompson
7d6093b302
Hacked the sram memory models to reset their internal registers. This allows the simulation to run but is only temporary.
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About 149307ns of simulation run.
2021-02-18 21:32:15 -06:00
Thomas Fleming
ca51e7ca1c
Create simple TLB
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This TLB is just a demonstration and is not currently
instantiated by the IFU or DFU.
2021-02-18 18:06:09 -05:00
David Harris
87ad559a90
Updated creation date of mul
2021-02-18 08:13:08 -05:00
Ross Thompson
8cbc9f7e51
Wrote a bash script to generate custom modelsim radix which maps instruction addresses into human readable lables.
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Once combined with some simulation verilog this will display the current function in modelsim.
2021-02-17 22:20:28 -06:00
Ross Thompson
bbe0db3ebe
Integrated the branch predictor into the hardward. Not yet working.
2021-02-17 22:19:17 -06:00
David Harris
fe7299c155
Resotred part of multiplier for lab 2
2021-02-17 16:14:04 -05:00
David Harris
492ec0ee78
Removed multiplier for lab 2
2021-02-17 16:06:16 -05:00
David Harris
e8d3c7d9e7
Multiplier tweaks
2021-02-17 16:00:27 -05:00
David Harris
e64e8afb7f
Started to integrate OSU divider
2021-02-17 15:38:44 -05:00
David Harris
a7dd20b388
Multiply instructions working
2021-02-17 15:29:20 -05:00
Noah Boorstin
43f9abdbed
busybear testbench: check (almost) all the CSRs
2021-02-16 20:03:24 -05:00
Noah Boorstin
5ce01fa86a
busybear: more small updates
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not sure what to do about MMU yet, hopefully we'll decide at saturday's meeting
2021-02-16 20:01:00 -05:00
David Harris
adc5d5bc1a
Added MUL
2021-02-15 22:27:35 -05:00
Ross Thompson
ca546beaf8
We now have a solid rough draft of the 2 bit sat counter branch predictor with BTB and RAS.
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This is not yet tested but the system verilog does compile.
2021-02-15 14:51:39 -06:00
Teo Ene
95b63af0a1
Added scripts to report power and area on a module-by-module basis
2021-02-15 12:09:33 -06:00
David Harris
3900abeb86
WALLY ALU tests
2021-02-15 10:16:31 -05:00
David Harris
36f7747752
Makefrag for ALU testsgen
2021-02-15 10:12:24 -05:00
David Harris
cc42655789
More memory interface, ALU testgen
2021-02-15 10:10:50 -05:00
Domenico Ottolia
3ee975dd5a
Add privileged test cases
2021-02-14 17:01:46 -05:00
Ross Thompson
935e9e59e9
added branch predictor 2 bit table + SRAM model. The SRAM model is only approximate, but it does correctly model the read and write pipelined behavior.
2021-02-14 15:13:55 -06:00
Teo Ene
f789e9c8ba
Due to legacy code, make pnr would print out an internal Makefile error at the end of the run. While this error was inconsequential and did not affect anything, it still needed to be removed.
2021-02-14 13:43:30 -06:00
Ross Thompson
8486f426b7
The top level of the branch predictor built and compiles. Does not yet function. Missing the BTB, RAS, and direction prediction tables.
2021-02-14 11:06:31 -06:00
Teo Ene
bd99a5613a
sky130 18T and 15T cell libraries removed
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Upon noticing their size, concerns were raised about available drive space.
As 12T is the main implementation focus, the decision was made to remove 15T and 18T.
Apologies if any were interested in implementing the processor across multiple standard cell libraries for comparison.
2021-02-14 09:05:41 -06:00
Teo Ene
67881ff686
After conferring with Dr. Harris, removed riscv-o3 submodule that most contributors to this repository lack access to.
2021-02-14 08:58:33 -06:00
Teo Ene
555e0296b2
After going through Lab 3 again, I've decided to make small changes to the provided floorplan so that it may serve as a slighly better example of a good floorplan.
2021-02-14 04:43:07 -06:00
Teo Ene
d6da36fbf6
Cleaning up my code a little bit more
2021-02-14 02:58:25 -06:00
Teo Ene
1ea01389b9
Final changes to the lab3 branch
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- Removed manual register file placement script, as it has been removed from lab.
- Created pre-sets that only have to be uncommented for the changing clock target portion of lab.
- Cleaned up Makefile in case anyone looks inside of it.
2021-02-14 02:01:20 -06:00
Teo Ene
5cc0d73aa0
Commiting sample floorplan that I failed to commit last night
2021-02-13 12:08:03 -06:00
Teo Ene
eab780afb9
- Cleaned up unnecessary files
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- Pulled updates for std cells
- Fixed typo that prevented easy switching between standard cell variants
- Fixed asynchronous reset paths from not being flagged as false
2021-02-12 21:49:42 -06:00
Shreya Sanghai
4e887f83a3
added branch tests
2021-02-12 22:40:08 -05:00
Teo Ene
2823bb1013
When Alex taught me how to use git, he stressed the importance of good commit messages that properly describe what changes were made
2021-02-12 16:52:23 -06:00
Teo Ene
9667f0f10f
Fixed rm bug for Ryan
2021-02-12 16:36:04 -06:00
Teo Ene
af3a888cde
Removed riscv-o3 module
2021-02-12 16:08:34 -06:00
Teo Ene
6c3c319d70
Quick commit for Ryan / branch / debugging.
2021-02-12 16:06:02 -06:00
Noah Boorstin
84d856d1e5
busybear: allow testbench to ignore lack of MMU for now
...
I'd really like to go over this with someone else, not sure if this is
a good thing to be doing
If it is, we're at 1M instructions!
2021-02-12 20:08:56 +00:00
Noah Boorstin
4bfed99da3
add reference output for some tests
2021-02-12 18:33:24 +00:00
Noah Boorstin
dd3a5b74a1
busybear: slightly neater error handling
2021-02-12 17:21:56 +00:00
bbracker
deb7780897
bus rw bugfix and peripherals testing
2021-02-12 00:02:45 -05:00
Noah Boorstin
79fb83409f
bump into virtual/physcial memory?
2021-02-11 23:06:12 -05:00
Noah Boorstin
e89af96bc0
busybear: more updates
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now gets to instruction 839037 before failing
also updates to match new gdb output format
umm there seems to be something wrong with the SSTATUS CSR. Just leaving
it out for now, will come back and check it later
2021-02-11 22:42:58 -05:00
Noah Boorstin
f08e549118
gdb output combine script updates
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check that everything is actually the same instruction
update to new 4-file output
this file should be finished for now
2021-02-11 14:59:15 -05:00
Tejus Rao
fb6a4bbbf0
added test cases for ADDW, SUBW, SLLW, SRLW, SRAW
2021-02-11 13:38:38 -05:00
Teo Ene
3e29e28132
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-02-10 20:49:12 -06:00
