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Configurable RISC-V Processor
151 Commits 5 Branches 2 Tags 53 MiB
SystemVerilog 33.7%
Python 19.2%
Assembly 17.5%
Tcl 16.2%
C 5.8%
Other 7.4%
eab780afb9
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Teo Ene eab780afb9 - Cleaned up unnecessary files 
- Pulled updates for std cells
 - Fixed typo that prevented easy switching between standard cell variants
 - Fixed asynchronous reset paths from not being flagged as false
2021-02-12 21:49:42 -06:00
sky130 - Cleaned up unnecessary files 2021-02-12 21:49:42 -06:00
wally-pipelined bus rw bugfix and peripherals testing 2021-02-12 00:02:45 -05:00
.gitignore Add the regression logs and new regression byproducts to the gitignore 2021-02-02 10:43:41 -05:00
.gitmodules Removed riscv-o3 module 2021-02-12 16:08:34 -06:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor