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Configurable RISC-V Processor
155 Commits 4 Branches 2 Tags 52 MiB
SystemVerilog 33.8%
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Assembly 17.5%
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555e0296b2
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Teo Ene 555e0296b2 After going through Lab 3 again, I've decided to make small changes to the provided floorplan so that it may serve as a slighly better example of a good floorplan.
2021-02-14 04:43:07 -06:00
sky130 - Cleaned up unnecessary files 2021-02-12 21:49:42 -06:00
wally-pipelined bus rw bugfix and peripherals testing 2021-02-12 00:02:45 -05:00
.gitignore Add the regression logs and new regression byproducts to the gitignore 2021-02-02 10:43:41 -05:00
.gitmodules Removed riscv-o3 module 2021-02-12 16:08:34 -06:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor