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Configurable RISC-V Processor
155 Commits 4 Branches 2 Tags 52 MiB
SystemVerilog 33.8%
Python 19.2%
Assembly 17.5%
Tcl 16.2%
C 5.8%
Other 7.4%
7d6093b302
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Ross Thompson 7d6093b302 Hacked the sram memory models to reset their internal registers. This allows the simulation to run but is only temporary. 
About 149307ns of simulation run.
2021-02-18 21:32:15 -06:00
sky130 Added synth and PnR flow 2021-01-25 14:28:14 -06:00
wally-pipelined Hacked the sram memory models to reset their internal registers. This allows the simulation to run but is only temporary. 2021-02-18 21:32:15 -06:00
.gitignore Add the regression logs and new regression byproducts to the gitignore 2021-02-02 10:43:41 -05:00
.gitmodules After conferring with Dr. Harris, removed riscv-o3 submodule that most contributors to this repository lack access to. 2021-02-14 08:58:33 -06:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md

README.md

riscv-wally

Configurable RISC-V Processor