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Configurable RISC-V Processor
128 Commits 4 Branches 2 Tags 52 MiB
SystemVerilog 33.8%
Python 19.2%
Assembly 17.5%
Tcl 16.2%
C 5.8%
Other 7.4%
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Noah Boorstin 79fb83409f bump into virtual/physcial memory?
2021-02-11 23:06:12 -05:00
riscv-o3@afb27bd558
sky130
wally-pipelined bump into virtual/physcial memory? 2021-02-11 23:06:12 -05:00
.gitignore Add the regression logs and new regression byproducts to the gitignore 2021-02-02 10:43:41 -05:00
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README.md

README.md

riscv-wally

Configurable RISC-V Processor