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Configurable RISC-V Processor
158 Commits 4 Branches 2 Tags 52 MiB
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c856003f73
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Ross Thompson c856003f73 RAS needs to be reset or preloaded. For now I just reset it. 
Fixed bug with the instruction class.
Most tests now pass.  Only Wally-JAL and the compressed instruction tests fail.  Currently the bpred does not support compressed.  This will be in the next version.
2021-02-19 20:09:07 -06:00
sky130 Added synth and PnR flow 2021-01-25 14:28:14 -06:00
wally-pipelined RAS needs to be reset or preloaded. For now I just reset it. 2021-02-19 20:09:07 -06:00
.gitignore Add the regression logs and new regression byproducts to the gitignore 2021-02-02 10:43:41 -05:00
.gitmodules After conferring with Dr. Harris, removed riscv-o3 submodule that most contributors to this repository lack access to. 2021-02-14 08:58:33 -06:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor