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Configurable RISC-V Processor
127 Commits 4 Branches 2 Tags 53 MiB
SystemVerilog 33.7%
Python 19.2%
Assembly 17.5%
Tcl 16.2%
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Noah Boorstin e89af96bc0 busybear: more updates 
now gets to instruction 839037 before failing
also updates to match new gdb output format

umm there seems to be something wrong with the SSTATUS CSR. Just leaving
it out for now, will come back and check it later
2021-02-11 22:42:58 -05:00
riscv-o3@afb27bd558 Hint to optimize ifu 2021-01-28 21:40:48 -05:00
sky130 Added synth and PnR flow 2021-01-25 14:28:14 -06:00
wally-pipelined busybear: more updates 2021-02-11 22:42:58 -05:00
.gitignore Add the regression logs and new regression byproducts to the gitignore 2021-02-02 10:43:41 -05:00
.gitmodules Added synth and PnR flow 2021-01-25 14:28:14 -06:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor