David Harris
3fa37b0233
Lint cleanup
2024-06-18 06:15:17 -07:00
David Harris
7509e856df
Removed asynchronous reset causing lint issue in peripherals
2024-06-18 05:49:12 -07:00
David Harris
4a4bbdfc43
More code cleanup
2024-06-14 09:50:07 -07:00
David Harris
53477b2c85
Code cleanup
2024-06-14 07:08:17 -07:00
David Harris
8f09240e6c
Simplified outdated documentation pointers
2024-06-14 03:42:15 -07:00
David Harris
3f195884e9
Defined bit sizes more precisely to help VCS lint and conform to coding style
2024-04-21 08:40:11 -07:00
David Harris
0419b5484a
parameterized register names in peripherals
2024-04-21 07:43:01 -07:00
slmnemo
39ae26a897
Added documentation for known Verilator hierarchy bug
2024-04-15 15:58:09 -07:00
slmnemo
4b80457f3e
Fixed issue with Verilator hierarchical referencing by changing module names, moved run-imperas-linux to correct directory
2024-04-12 21:58:20 -07:00
David Harris
79cccfca82
Progress toward run_vcs
2024-04-03 14:05:07 -07:00
Kunlin Han
22b59138f0
Remove all #delay from non-testbench.
2024-03-16 11:20:32 -07:00
Kunlin Han
8c67a76912
Remove all #delay from non-testbench.
2024-03-13 10:31:40 -07:00
David Harris
e0eb91f795
Changed always @(posedge clk) to always_ff @(posedge clk) where it was omitted in several places
2024-03-06 11:02:04 -08:00
David Harris
b386331cc8
Changed '0 to 0 where possible per Chapter 4 style guidelines
2024-03-06 05:48:17 -08:00
David Harris
0abfe5cb55
Fixed some lint errors in derived configs
2024-01-31 11:39:59 -08:00
David Harris
f37c7bb1f6
Incorporated RAM_LATENCY and BURST_EN as parameters rather than define in code. Still need to update testbench to use this
2024-01-30 06:27:18 -08:00
David Harris
45e2317636
Added Wally github address to header comments
2024-01-29 05:38:11 -08:00
David Harris
6395cd0284
Reversed numbering of adrdecs to make it easier to add new peripherals without renumbering the old ones; update figure to match
2023-12-21 12:29:37 -08:00
Rose Thompson
053b094620
Simpilified pmachecker for cmo.
2023-11-29 12:26:18 -06:00
Rose Thompson
beb95dd592
Modified the pmachecker to correctly check the permissions for cmo instructions.
...
However this isn't fully tested.
2023-11-27 17:44:11 -06:00
David Harris
d3ce683e06
Removed other unused signals from Verilog
2023-11-20 23:37:56 -08:00
naichewa
8ffce456bd
Merge branch 'spi' into main
2023-11-14 14:51:06 -08:00
naichewa
1ab7c926ea
Final Code Review
2023-11-14 13:44:59 -08:00
Rose Thompson
95fc5f4a1c
Towards removing the FPGA config file.
2023-11-13 17:20:26 -06:00
Rose Thompson
a6995af91c
Fixed bug in uncore updates which broke SDC.
2023-11-13 16:15:23 -06:00
naichewa
5ce16dcb63
Cleanup
2023-11-09 16:52:55 -08:00
naichewa
3052a68d84
Remove old 2/4 bit logic, add comments,
...
clean up unused signals
2023-11-09 16:48:11 -08:00
naichewa
b13b8feee4
updated to-do comments
2023-11-08 15:28:51 -08:00
naichewa
d67badfc60
fix hardware interlock, hold mode deassert
2023-11-08 15:20:51 -08:00
naichewa
a5837eb62c
fifo fixes and edge case testing
2023-11-07 17:59:46 -08:00
David Harris
4de21c206f
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-11-03 16:04:10 -07:00
David Harris
1f2899de14
Modified rams to take USE_SRAM rather than P to facilitate synthesis
2023-11-03 05:44:13 -07:00
naichewa
29e42b21df
added test cases
2023-11-02 15:42:28 -07:00
naichewa
e3d8162279
harris code review 3
2023-11-01 10:14:15 -07:00
naichewa
9aa8a7af3e
comments, more test cases
2023-11-01 01:26:34 -07:00
naichewa
fefb5adb8f
code review harris
2023-10-31 12:27:41 -07:00
naichewa
7dd3f24d6c
Merge branch 'main' into spi
2023-10-30 17:01:41 -07:00
naichewa
2330f4ee63
hardware interlock
2023-10-30 17:00:20 -07:00
David Harris
48d42c1e7c
Removed unnecessary RV64 PWDATA muxing from AHB peripherals because LSU already replicates
2023-10-18 05:50:41 -07:00
naichewa
4941fe1769
sync fifo passes
2023-10-16 22:57:02 -07:00
naichewa
aa5abfc8e8
always working after reg bit swizzle changes
2023-10-13 14:22:32 -07:00
naichewa
d5d4f9d044
transferred spi changes in ECA-authorized commit
2023-10-12 13:36:57 -07:00
David Harris
28823aca6e
Cleaned up lint for plic_apb part select
2023-07-30 02:00:38 -07:00
David Harris
654cafb7f7
Fixed Questa warnings in plic_apb about part select out of bounds
2023-07-30 01:54:41 -07:00
Ross Thompson
b1f7a5768f
Removed all old references to the old flash card controller.
...
Added git submodule for the flash card in addins.
Replicated flash card top level for our changes into the fpga/src directory.
2023-07-24 15:45:57 -05:00
Ross Thompson
63afd95ad3
Fixed bugs in boot and new flash card merge. Works with arty a7 now.
2023-07-22 15:52:25 -05:00
Ross Thompson
a89a1e675c
Merge branch 'boot' into mergeBoot
...
Merges Jacob's new sdc controller into wally.
2023-07-21 17:43:45 -05:00
Jacob Pease
b3aaa87cba
Modified bootloader to access GUID partitions. SDC interrupt to PLIC.
...
Since writing an SD card image generation script, the bootloader
needed to be altered to access individual binaries from specific
partitions. A new file, gpt.c with it's header gpt.h, have been added
to the bootloader to facilitate this.
The SDC has been added to the device tree for the VCU108
board. Additionally the SDC interrupt signal was added to the PLIC
node in the device tree. The PLIC itself was modified to accept the
SDC interrupt signal.
2023-07-14 13:36:44 -05:00
Ross Thompson
cdf73d3b51
Updated comments.
2023-07-06 15:24:26 -05:00
Ross Thompson
e4555dc4af
Removed unused parameter.
2023-07-06 14:57:07 -05:00
Ross Thompson
a963e50e88
It's a bit hacky, but the plic now passes the regression test and should be compatible with the fpga.
2023-07-06 14:07:37 -05:00
Ross Thompson
df56ff73c0
This is at least functionally correct, but has verilator lint issues.
2023-07-06 11:53:34 -05:00
Ross Thompson
c000366d3e
closer, but the wally32/64priv tests are failing.
2023-07-05 17:47:38 -05:00
Ross Thompson
98147e116a
Partially solved fpga boot.
2023-07-05 17:30:55 -05:00
Ross Thompson
c44d4321fb
FPGA synthesis is broken. This commit moves closer to fixing the issues causes by parameterization.
2023-06-16 15:40:13 -05:00
Ross Thompson
bdc5656ef3
Added comment to uart LCR to check reset value after updating FPGA.
2023-06-15 15:39:51 -05:00
Ross Thompson
4428babda9
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-06-15 15:38:38 -05:00
Ross Thompson
85567841eb
Merge branch 'testbench-params2'
2023-06-15 15:31:13 -05:00
Ross Thompson
009d8966e9
Got the srams parameterized correctly now.
2023-06-15 13:42:24 -05:00
David Harris
d3aebc00d4
Fixed UART merge conflict
2023-06-15 11:36:37 -07:00
Harshini Srinath
b5354a811e
Update uncore.sv
...
Program clean up
2023-06-15 10:23:47 -07:00
Harshini Srinath
85b982f569
Update uart_apb.sv
...
Program clean up
2023-06-15 10:21:46 -07:00
Harshini Srinath
59178a2e56
Update uartPC16550D.sv
...
Program clean up
2023-06-15 10:20:29 -07:00
Harshini Srinath
d02891d244
Update rom_ahb.sv
...
Program clean up
2023-06-15 10:13:15 -07:00
Harshini Srinath
e227f71d46
Update ram_ahb.sv
...
Program clean up
2023-06-15 10:10:38 -07:00
Harshini Srinath
57f4c8a3e4
Update plic_apb.sv
...
Program clean up
2023-06-15 10:08:16 -07:00
Harshini Srinath
cf25e9ce49
Update gpio_apb.sv
...
Program clean up
2023-06-15 10:04:28 -07:00
Harshini Srinath
a8fa38ff14
Update clint_apb.sv
...
Program clean up
2023-06-15 09:59:11 -07:00
David Harris
325a670435
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-06-15 07:01:44 -07:00
David Harris
9da4005a1e
Removed *** from UART code
2023-06-14 08:47:01 -07:00
David Harris
5a2bcb917f
Removed QEMU from UART
2023-06-14 08:39:01 -07:00
Harshini Srinath
9e1f03f93b
Update ahbapbbridge.sv
...
Program clean up
2023-06-12 20:49:46 -07:00
Ross Thompson
a963f0af3a
Updated source code to be compatible with verilator 5.011 for lint only.
2023-05-31 10:44:23 -05:00
Ross Thompson
169539f773
Cleanup parameterization for verilator 5.010.
2023-05-31 10:02:34 -05:00
Ross Thompson
3cc85349b5
Uncore is now parameterized.
2023-05-26 16:24:12 -05:00
Jacob Pease
40f81d5da6
The Vivado-RISC-V SDC works. Wally is now booting through it.
2023-05-26 15:42:33 -05:00
Ross Thompson
02a788a083
PMA checker's address decoder is now parameterized. I did not see bit slicing in Lim's code. I'm not sure how they got around this issue.
2023-05-26 11:06:48 -05:00
Jacob Pease
b796b1b492
Build doesn't work. AXI Crossbar has problems.
2023-04-06 16:01:58 -05:00
Ross Thompson
ca4b058373
Modified plic and uart to remove async reset. This removes vivado critical warning.
2023-03-24 20:37:48 -05:00
Ross Thompson
0afba56927
Updated GPIO signal names to reflect book.
2023-03-24 18:55:43 -05:00
Ross Thompson
46b1bca4fc
Fixed all tap/space issue in RTL.
2023-03-24 17:32:25 -05:00
Jacob Pease
2d0199a354
Added sdio_cd to vcu108 constraints. Removed SDC signals from uncore
2023-03-24 17:01:27 -05:00
Jacob Pease
45b264fa59
Merge branch 'main' of github.com:openhwgroup/cvw into boot
2023-02-16 17:36:26 -06:00
David Harris
78eb90715c
Removed pipelined level of hierarchy
2023-02-02 14:14:11 -08:00
