Rose Thompson
d31622fa21
Merge pull request #1103 from JacobPease/main
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Made minor changes to the controller to clean up the logic. Still need to simplify the first always block.
2024-12-03 17:03:43 -06:00
Rose Thompson
2f04e5e597
Merge branch 'main' of github.com:rosethompson/cvw
2024-11-25 15:53:27 -06:00
Rose Thompson
7358c1fe67
Fixed sublte bug in the spi_fifo which allows for spurious write to fifo. Fixed fpga zsbl so that is uses read fifo interrupt pending (IP) rather than transmit fifo IP. Resolves issue with stalled load reading the wrong fifo status.
2024-11-25 15:50:29 -06:00
David Harris
ce7b036b78
Merge pull request #1109 from jordancarlin/lint
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More lint cleanup: remove unused params
2024-11-16 16:34:15 -08:00
Jacob Pease
2dcfe10013
Merged changes and reverted my commits.
2024-11-16 14:50:06 -06:00
Jordan Carlin
f6b0805fd4
More lint cleanup: remove unused params
2024-11-16 12:35:37 -08:00
Jacob Pease
dda3cd6bea
Removed unnecessary separate if statement.
2024-11-16 14:29:58 -06:00
David Harris
56cbcf222b
Merge pull request #1107 from jordancarlin/lint
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Clean up verilator lint off commands and remove unnecessay ones
2024-11-16 12:16:52 -08:00
Jacob Pease
2ee4525ba9
Made minor changes to the controller to clean up the logic. Still need to simplify the first always block.
2024-11-16 11:34:31 -06:00
Jordan Carlin
a462b9a2e6
Clean up verilator lint off commands and remove unnecessay ones
2024-11-15 23:52:50 -08:00
David Harris
234e47a7c5
MTIMECMP should reset to maximum value for RV32, not just for RV64
2024-11-15 15:37:25 -08:00
naichewa
396a17623b
Fixed TransmitStart resetting SCK and delay counter while already counting
2024-11-08 11:05:38 -08:00
naichewa
987015a2a7
Fix SPI Delay1 behavior
2024-11-07 12:14:23 -08:00
naichewa
7964358651
Fix erroneous implicit sckcs and cssck phase delays
2024-11-07 10:47:51 -08:00
naichewa
7637f3e33b
Fix erroneous implicit sckcs and cssck phase delays
2024-11-07 10:19:55 -08:00
naichewa
927398a017
Fix SPI state skipping sck-cs delay when at end of transmission
2024-11-07 10:17:22 -08:00
Jacob Pease
507c1dad1c
Removed impossible condition in receive register logic.
2024-11-04 16:15:42 -06:00
Jacob Pease
120b21d7d5
More SPI optimizations.
2024-11-04 15:38:12 -06:00
Jacob Pease
a9e6962cd4
Removed unused signals and renamed other signals. Removed a bunch of delay counters and simply reuse one counter for all delay types. Tested on FPGA and it also passes regression.
2024-11-03 00:35:40 -05:00
Jacob Pease
674d008f23
Added headers to files.
2024-11-02 14:31:05 -05:00
Jacob Pease
c197d4a3c6
Cleaned up some code. Still more work to do there.
2024-11-01 17:35:55 -05:00
Jacob Pease
e881bd3120
Changed the condition for TransmitStart fsm to avoid edge condition.
2024-11-01 17:04:07 -05:00
Jacob Pease
eddae8e1a6
Fixed ShiftEdge and SampleEdge to not always include PhaseOneOffset. Before, it worked in simulation, but not on the FPGA.
2024-11-01 13:02:17 -05:00
Jacob Pease
56a6ad3376
Fixed lint issues.
2024-10-31 15:56:16 -05:00
Jacob Pease
3ee5fffe02
Fixing latches.
2024-10-31 13:54:56 -05:00
Jacob Pease
72a854eb07
Refactored SPI passes regression save for hardware interlock tests.
2024-10-31 13:01:25 -05:00
Jacob Pease
419030bc33
Fixed FSM to continue transmitting after delay.
2024-10-31 10:41:38 -05:00
Jacob Pease
35c9fe7648
Added changed SPI controller module. New signal TransmitStartD that starts the FSM based on SCLKenable. TransmitStart is responsible for resetting SCLKenable and loading the Transmit Shift Register.
2024-10-30 18:45:54 -05:00
Jacob Pease
4e7e311b26
Fixed issues relating to SCLKenable and TransmitStart. Works at multiple dividers now, instead of just SckDiv = 0.
2024-10-30 18:39:04 -05:00
Jacob Pease
4f0723f236
Fixed enabling of TransmitFIFOReadIncrement and ReceiveFIFOWriteIncrement
2024-10-30 16:19:46 -05:00
Jacob Pease
b667581ffa
Refactored SPI peripheral based on SPI controller module. Works in tests/custom/spitest.
2024-10-29 17:50:36 -05:00
Jacob Pease
784630b945
Added wally header to spi_controller.
2024-10-29 10:53:33 -05:00
Jacob Pease
37d2f3220e
Added a new spi controller design. Designed as a proof of concept to see if timing issues can be fixed. I intend to work it into existing SPI peripheral.
2024-10-29 10:30:08 -05:00
David Harris
1c1acc467e
Tweaked SPI to avoid breaking VCS, but the SCLK divider still doesn't produce the right frequency and SCLKenableEarly looks like it wouldn't work for SckDiv = 0
2024-10-26 02:01:09 -07:00
Rose Thompson
a4cda877ef
Fixed bit position of SPI fifo receive and transmit flags.
2024-10-21 14:52:40 -05:00
Rose Thompson
32624bc6ee
Relocated a logic in a file to avoid a future merge conflict.
2024-09-05 12:50:09 -07:00
Rose Thompson
005ea52b72
Added missing signal declaration for SPI.
2024-09-05 12:20:06 -07:00
Rose Thompson
ac047a04fa
Fixed bug in SPI with the help of Naiche and Jacob. Have yet to test
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if SPI will now run correctly with div=0 (SYSTEMCLOCK/2), but the SPI
flash card now correctly loads into the Linux OS and mount and is
reading and writting without error.
2024-09-04 17:51:48 -07:00
naichewa
3b7661dfd5
SckDiv Zero bug fixes
2024-09-03 14:58:46 -07:00
Jacob Pease
938879c5a4
Update PREADY signal to not stall during transmission on reads to read only registers.
2024-08-21 12:39:01 -05:00
Jacob Pease
b7edffdfd4
Removed now inaccurate comments.
2024-08-20 16:38:15 -05:00
Jacob Pease
d8b75440b6
With Naiche's help, we fixed the SPI controllers clock polarity and phase settings. Added conditions to the SPI regression tests.
2024-08-20 16:24:37 -05:00
Jacob Pease
43b17b5058
Update SPI peripheral to accept writes to FIFO always. Worked on this together with Naiche and Rose.
2024-08-20 14:40:50 -05:00
Jacob Pease
11a057b0b3
Updated wally source files for zsbl testing.
2024-08-02 15:33:57 -05:00
Jacob Pease
336a413f31
Added ability to split boot.memfile into boot.mem and data.mem.
2024-07-25 11:19:15 -05:00
Jacob Pease
f1cc7dd5a3
Fixed verilog bugs.
2024-07-23 17:26:39 -05:00
Jacob Pease
a506d76149
Removed the old SDC. Added a second SPI peripheral that now will be used to control the SD card. SPI peripheral now outputs SPICLK. Removed references to the now non-existent external SDC in uncore. Removed all of the AXI Xilinx IP.
2024-07-22 12:36:39 -05:00
Ross Thompson
7f0ba87231
Updated comments in uart.
2024-06-19 13:51:30 -07:00
David Harris
cb563e8018
Clean up unused signals
2024-06-18 08:07:14 -07:00
David Harris
c1fd7a9589
Removed unused signals
2024-06-18 07:28:52 -07:00
