Ross Thompson
54abd944e2
Simplified byte write enable logic.
2022-03-10 18:13:35 -06:00
Ross Thompson
50789f9ddd
Byte write enables are passing all configs now.
2022-03-10 17:26:32 -06:00
Ross Thompson
f7df3a0666
Progress on the path to getting all configs working with byte write enables.
2022-03-10 17:02:52 -06:00
Ross Thompson
83133f8c47
Partially working byte write enables. Works for cache, but not dtim or bus only.
2022-03-10 16:11:39 -06:00
Ross Thompson
d5f524a15e
Added byte write enables to cache SRAMs.
2022-03-10 15:48:31 -06:00
David Harris
b1340653cf
bit write update
2022-03-09 19:09:20 +00:00
David Harris
004853c312
Refactored SRAM bit write enable
2022-03-09 17:49:28 +00:00
David Harris
ba9320d822
Updated testbench to read expected flags
2022-03-09 13:58:17 +00:00
Ross Thompson
2a8a1cd191
Minor cleanup to interlockfsm.
2022-03-08 23:38:58 -06:00
Ross Thompson
ac9528b450
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-03-08 18:05:35 -06:00
Ross Thompson
ed32801cc1
Comments.
2022-03-08 18:05:25 -06:00
Ross Thompson
534fd70f76
Marked signals for name changes.
2022-03-08 17:41:02 -06:00
David Harris
5d0b9bab6e
Added more test cases and rounding modes to fma test generator
2022-03-08 23:29:29 +00:00
David Harris
cfa82efccc
fma16_testgen.c test cases
2022-03-08 23:18:18 +00:00
Ross Thompson
acd60218b8
Removed unused signal.
2022-03-08 16:58:26 -06:00
Ross Thompson
cc21414051
Added parameter to spillsupport.
2022-03-08 16:38:48 -06:00
Ross Thompson
60e6c1ffa7
Moved cacheable signal into cache.
2022-03-08 16:34:02 -06:00
David Harris
d2282d5e87
Checked in fma16_template.v
2022-03-06 13:29:35 +00:00
David Harris
48705457d5
LSU/Cache code review notes
2022-03-04 00:07:31 +00:00
David Harris
545f569f78
Fixed fma files to stop breaking synthesis. Changed Makefiles to skip Imperas
2022-03-03 15:38:08 +00:00
David Harris
8fbdbba81a
fma file fixes
2022-03-02 23:47:01 +00:00
bbracker
be2f668867
but apparently QEMU doesn't show UXL in SSTATUS
2022-03-02 22:44:19 +00:00
bbracker
01e0f2f0d2
update SXL UXL bits in MSTATUS to match new QEMU trace
2022-03-02 22:15:57 +00:00
David Harris
3bea7bb431
removed imperas-riscv-tests
2022-03-02 17:28:20 +00:00
David Harris
1661983345
FMA project ready to start
2022-03-01 20:58:08 +00:00
David Harris
f314e60dc8
Renamed unpacking unit to unpack and renamed WriteDataW to ResultW in IEU datapath
2022-02-28 20:50:51 +00:00
David Harris
f0a7ae2bba
adrdecs comments
2022-02-28 20:33:41 +00:00
David Harris
e108eb5195
Modified address decoder for native access to CLINT
2022-02-28 19:13:14 +00:00
David Harris
3519a20ccf
hptw cleanup for synthesis
2022-02-28 05:54:34 +00:00
David Harris
bb14dba9be
Created softfloat_demo showcasing how to do math with SoftFloat
2022-02-27 18:17:21 +00:00
David Harris
c7b5d32a72
Linking against riscv-isa-sim SoftFloat library for RISC-V NaN behavior
2022-02-27 17:23:33 +00:00
David Harris
c6561d1e8b
Moved FMA back into source tree to facilitate synthesis
2022-02-27 15:41:41 +00:00
David Harris
274ecf13ad
Moved fma directory
2022-02-27 14:20:15 +00:00
David Harris
5a5142c14f
fma simulation infrastructure
2022-02-27 04:36:43 +00:00
David Harris
d917cc1379
fma passing multiply vectors
2022-02-27 04:36:01 +00:00
David Harris
8a55935456
simplified fma Makefile
2022-02-26 19:55:42 +00:00
David Harris
1852eccaab
Made softfloat.a a symlink
2022-02-26 19:53:04 +00:00
David Harris
87d1a8a1ac
Added start of fma
2022-02-26 19:51:19 +00:00
Ross Thompson
97d64201f7
Fixed bug with DAPageFault being wrong when HPTW writes not supported.
2022-02-23 10:54:34 -06:00
Ross Thompson
53f13d4cbc
More spillsupport more structual.
2022-02-23 10:27:14 -06:00
Ross Thompson
c23f6c7d90
Fixed bug with spill support and Instruction DA Page Faults.
2022-02-23 10:16:12 -06:00
Ross Thompson
62e1a97287
Added generates to pcnextf muxes for privileged and caches.
2022-02-22 22:45:00 -06:00
Ross Thompson
6a52f95cc8
Minor busdp cleanup.
2022-02-22 17:28:26 -06:00
Ross Thompson
59a2c09c5e
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-22 14:45:53 -06:00
Ross Thompson
90be3d4360
Clarified interlockfsm.
2022-02-22 11:31:28 -06:00
bbracker
b8fd06576c
fix lint bugs in PLIC and UART
2022-02-22 05:04:18 +00:00
bbracker
a6047697c3
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-02-22 04:27:50 +00:00
bbracker
e7934c585a
change RX side of UART to aslo be LSB-first
2022-02-22 03:34:08 +00:00
Ross Thompson
3a29504279
Added some clearity to lsuvirtmem.sv.
2022-02-21 17:20:58 -06:00
Ross Thompson
ca59778c5a
Annotated IFU for mux changes.
2022-02-21 17:20:34 -06:00
Ross Thompson
2f711fb642
Changed HPTWRead/HPTWWrite to be HPTWRW to be similar to MemRW.
2022-02-21 16:54:38 -06:00
Ross Thompson
0c65ea96d8
Cleaned up names in lsuvirtmem.
2022-02-21 16:44:30 -06:00
Ross Thompson
56fc6d0d7c
Minor cleanup of lsu.
2022-02-21 12:46:06 -06:00
Ross Thompson
f48b12b089
Moved mux into lsuvirtmem.
2022-02-21 09:31:29 -06:00
Ross Thompson
cbf4395457
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-21 09:06:09 -06:00
Ross Thompson
ae06785b9f
Minor changes to LSU.
2022-02-19 14:38:17 -06:00
David Harris
20a5798f43
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-02-18 23:08:47 +00:00
David Harris
6a0ffff05d
Removed problematic warning about reaching default state in HPTW
2022-02-18 23:08:40 +00:00
Ross Thompson
6cd9d84e7f
New config option to enable hptw writes to PTE in memory to update Access and Dirty bits.
2022-02-17 17:19:41 -06:00
Ross Thompson
ad237b3ce5
Accidentally cleared dirty bit when setting access bit in hptw.
2022-02-17 16:20:20 -06:00
Ross Thompson
cbac34943c
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-17 14:49:37 -06:00
Ross Thompson
0eec096474
Rough implementation passing regression test with hptw atomic writes to memory.
2022-02-17 14:46:11 -06:00
David Harris
f3c7025ade
Started make allsynth to try many experiments
2022-02-17 17:57:02 +00:00
Ross Thompson
2fc7dc3e57
Fixed a bunch of the virtual memory changes. Now supports atomic update of PTE in memory concurrent with TLB.
2022-02-17 10:04:18 -06:00
Ross Thompson
62f5f1e622
Broken state. address translation not working after changes to hptw to support atomic updates to PT.
2022-02-16 23:37:36 -06:00
Ross Thompson
c9e33208e3
Moved a few muxes around after sww changes.
2022-02-16 15:43:03 -06:00
Ross Thompson
71ed49bf2b
cleanup of signal names.
2022-02-16 15:29:08 -06:00
Ross Thompson
6dc12b4968
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-16 15:22:35 -06:00
Ross Thompson
27042f028e
Modified lsu and uncore so only 1 sww is present. The sww is in the LSU if there is a cache or dtim. uncore.sv contains the sww if there is no local memory in the LSU. This is necessary as the subword write needs the read data to be valid and that read data is not aviable in the correct cycle in the LSU if there is no dtim or cache. Muxing could be done to provide the correct read data, but it adds muxes to the critical path.
2022-02-16 15:22:19 -06:00
David Harris
c23db6a31e
Cleaned warning on HPTW default state
2022-02-16 17:40:13 +00:00
David Harris
01fa5c94bd
Register file comments about reset
2022-02-16 17:21:05 +00:00
Ross Thompson
c56c4db47f
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-16 09:48:16 -06:00
David Harris
aa990be959
removed csrn and all of its outputs because depricated
2022-02-15 19:59:29 +00:00
David Harris
d8170e9dd3
Mostly removed N_SUPPORTED
2022-02-15 19:50:44 +00:00
David Harris
ed8ac3d881
Just needed to recompile - all good. Now removed uretM because N-mode is depricated
2022-02-15 19:48:49 +00:00
David Harris
5ef8f6bc7e
Removed depricated N-mode support and SI/EDELEG registers. rv64gc_wally64priv tests are failing, but seem to be failing before this change.
2022-02-15 19:20:41 +00:00
Ross Thompson
fcbb577f31
Cache mods to be consistant with diagrams.
2022-02-14 12:40:51 -06:00
David Harris
caa4d83e57
t push
...
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-02-14 01:22:22 +00:00
Ross Thompson
86e117ea77
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-13 18:21:15 -06:00
Ross Thompson
6e1a0af5d0
Eliminated more ports in cacheway.
2022-02-13 15:53:46 -06:00
Ross Thompson
a440bc2ac5
More cache cleanup.
2022-02-13 15:47:27 -06:00
Ross Thompson
1e7e59bdbd
Changed names of signals in cache.
2022-02-13 15:06:18 -06:00
Ross Thompson
f87a6f2c63
More cache cleanup.
2022-02-13 12:38:39 -06:00
David Harris
f5678e25db
Synthesis cleanup
2022-02-12 06:25:12 +00:00
David Harris
b537df2651
Synthesis script cleanup, eliminated privileged instructiosn from controller when ZICSR_SUPPORTED = 0
2022-02-12 05:50:34 +00:00
Ross Thompson
f5c4bca47e
Formating improvements to cache.
2022-02-11 23:10:58 -06:00
Ross Thompson
6fa9490d0b
More cache simplifications.
2022-02-11 22:54:05 -06:00
Ross Thompson
ae2011eb07
Reduced seladr to 1 bit as second bit is same as selflush.
2022-02-11 22:41:36 -06:00
Ross Thompson
cb3d71a63d
Reduced complexity of the address selection during flush.
2022-02-11 22:27:27 -06:00
Ross Thompson
a0ee2f3d99
Removed redundant signals from cache.
2022-02-11 22:23:47 -06:00
Ross Thompson
aa04778d0b
Cache fsm simplifications.
2022-02-11 15:16:45 -06:00
Ross Thompson
e6c8cfd49b
Removed STATE_CPU_BUSY_FINISH_AMO from cache. This is redundant with STATE_CPU_BUSY.
2022-02-11 15:09:00 -06:00
Ross Thompson
83adacbee3
Simplified cache fsm.
2022-02-11 14:54:57 -06:00
Ross Thompson
c8e6884926
Fixed bug.
...
It was possible for DTLBMissM to prevent a dcache flush.
2022-02-11 14:00:01 -06:00
Ross Thompson
20456097cd
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-11 10:47:21 -06:00
Ross Thompson
2f2a4f4500
Fixed subtle and infrequenct bug.
...
Loading buildroot at 483M instructions started with a spill + ITLBMiss. The spillsupport logic allowed transition to the second access only after the bus/cache completed the first operation. However the BusStall was suppressed if ITLBMissF occurs resulting in the spillfsm advancing to the second operation. Now the spill logic also takes in ITLBMissF and prevents the early transition to the second access.
2022-02-11 10:46:06 -06:00
David Harris
15fb7fee60
Cleaned up synthesis warnings
2022-02-11 01:15:16 +00:00
Ross Thompson
fc6dc52618
Fixed bugs in ifu spills and missing reset on bus data register.
2022-02-10 18:11:57 -06:00
Ross Thompson
f23817bf69
Replacement policy cleanup.
2022-02-10 11:42:40 -06:00
Ross Thompson
411997010b
Replacement policy cleanup.
2022-02-10 11:40:10 -06:00
