James Stine
|
1108268557
|
Update C program for r=4 division by recurrence to match Table in EL
|
2022-06-20 11:32:40 -05:00 |
|
Daniel Torres
|
d077199608
|
embench and testbench now support running both O2 and Os build variations without overwriting one another
|
2022-06-17 21:15:42 -07:00 |
|
Daniel Torres
|
1ef5ed8005
|
arch tests now run on spike and sail and compare signatures during build
|
2022-06-17 20:53:15 -07:00 |
|
Daniel Torres
|
dcdd3702c3
|
removed old code from makefile, simplified code in testbench
|
2022-06-17 15:13:38 -07:00 |
|
Daniel Torres
|
3a5c02b44a
|
arch bug fixes and testbench changes
|
2022-06-17 15:07:16 -07:00 |
|
David Harris
|
7e4988c2de
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-06-17 15:45:24 +00:00 |
|
Katherine Parry
|
8425f8838d
|
hopefully fixed lint error
|
2022-06-17 00:14:39 +00:00 |
|
Katherine Parry
|
93906b9457
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-06-15 22:58:42 +00:00 |
|
Katherine Parry
|
e121dcd4af
|
postprocess out of fpu critical path
|
2022-06-15 22:58:33 +00:00 |
|
Madeleine Masser-Frye
|
c2493168b6
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-06-15 18:30:27 +00:00 |
|
Madeleine Masser-Frye
|
76e30ed8ab
|
cleanup, plots for paper
|
2022-06-15 18:28:36 +00:00 |
|
James Stine
|
d69a8f4077
|
Add back SV for integer division to use 8-bit CPA in qslc
|
2022-06-15 11:46:39 -05:00 |
|
James Stine
|
535a9a04ee
|
Add r=4 C code
|
2022-06-15 11:44:09 -05:00 |
|
Katherine Parry
|
11b252a735
|
some synth fpu optimizations
|
2022-06-14 23:58:39 +00:00 |
|
David Harris
|
ecd733942a
|
Removed testbench.sv.bak
|
2022-06-14 22:04:38 +00:00 |
|
Katherine Parry
|
998876ce49
|
removed false critical path from fpu
|
2022-06-14 16:50:46 +00:00 |
|
Katherine Parry
|
566001e07b
|
fixed acciedental critical path in FPU
|
2022-06-14 00:02:38 +00:00 |
|
DTowersM
|
919c1818a8
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-06-13 23:34:35 +00:00 |
|
DTowersM
|
1f4d56ba32
|
added back working coremark in benchmarks/riscv64-bcoremarkdirectory, experimental simplifications are in benchmarkscoremark/ but this doesn't currently work (some type of c bug)
|
2022-06-13 23:23:57 +00:00 |
|
Katherine Parry
|
31fd8772cf
|
postprocessing unit created and passing all tests
|
2022-06-13 22:47:51 +00:00 |
|
David Harris
|
8ea484a343
|
Cleanup on RAM module
|
2022-06-13 19:37:43 +00:00 |
|
David Harris
|
b7a7ca6eac
|
Typo in gpio reset
|
2022-06-13 19:37:05 +00:00 |
|
slmnemo
|
eb41185a70
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-06-13 12:30:33 -07:00 |
|
David Harris
|
be65e8f862
|
Removed SRT testvectors from repo
|
2022-06-13 19:27:33 +00:00 |
|
slmnemo
|
915b8e2adb
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-06-13 12:27:23 -07:00 |
|
slmnemo
|
7b704f8db0
|
Merge branch 'cacheburstmode' into main.
Cache burst mode is now working! It also uses the new RAM.
|
2022-06-13 12:26:18 -07:00 |
|
slmnemo
|
98c07ce2c0
|
Added more comments
|
2022-06-13 12:26:08 -07:00 |
|
David Harris
|
ccd16210bc
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-06-13 19:26:07 +00:00 |
|
David Harris
|
e9ef9a5cb8
|
Fixed XOR logic in GPIO
|
2022-06-13 19:26:03 +00:00 |
|
slmnemo
|
3d715a098c
|
Added comment about name of LSUBusInit/Lock signal
|
2022-06-13 10:56:02 -07:00 |
|
slmnemo
|
cadd62e49f
|
Removed irrelevant comments in ahblite and made it more clear when to use certain transmission signals
|
2022-06-10 20:43:56 -07:00 |
|
slmnemo
|
beb4317e68
|
Added comments to signals added so the bus is easier to analyze
|
2022-06-10 20:30:04 -07:00 |
|
slmnemo
|
b7357efc6b
|
Fixed failed regression state by only enabling counting when doing cached operations
|
2022-06-10 20:00:09 -07:00 |
|
slmnemo
|
63ed390c90
|
Fixed error where CntReset would be high one cycle too long, adding a cycle of delay. Broke wally64priv by failing trap-sret-01.
|
2022-06-10 19:10:01 -07:00 |
|
Madeleine Masser-Frye
|
422bd2043f
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-06-10 21:11:47 +00:00 |
|
Madeleine Masser-Frye
|
7cdf9cd4d3
|
added 'd' suffix to muxes for data-critical synths
|
2022-06-10 21:11:05 +00:00 |
|
DTowersM
|
4bbe5eeecd
|
simplified coremark
|
2022-06-10 19:15:17 +00:00 |
|
slmnemo
|
dc11066ff2
|
Passed Regression: Seems to work perfectly fine
|
2022-06-09 18:21:13 -07:00 |
|
slmnemo
|
ec7cdee0f3
|
Merge branch 'main' into cacheburstmode
|
2022-06-09 17:51:03 -07:00 |
|
slmnemo
|
5a6eae214a
|
?
|
2022-06-09 17:50:47 -07:00 |
|
DTowersM
|
9e2d80764d
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-06-10 00:38:07 +00:00 |
|
DTowersM
|
dd34f25ffd
|
changed DCACHE_LINELENINBITS and ICACHE_LINELENINBITS to 512, had to modigy the wfi test to increase timee before interupt to mantain compatability
|
2022-06-10 00:37:53 +00:00 |
|
slmnemo
|
3e8d3bae88
|
Changes made on 9th Jun
|
2022-06-09 17:33:51 -07:00 |
|
slmnemo
|
4ff105f18c
|
Fixed lint error
|
2022-06-09 17:22:04 -07:00 |
|
David Harris
|
c836f37a08
|
New RAM for further testing
|
2022-06-09 23:50:43 +00:00 |
|
stineje
|
470c0552f8
|
Update integer division for r4 and qslc_r4a2.c
|
2022-06-09 16:45:13 -05:00 |
|
David Harris
|
dd4fa7c682
|
qslc_r4a2 generator
|
2022-06-09 17:26:47 +00:00 |
|
slmnemo
|
0d04751c77
|
Fixed error when doing uncached accesses where HTRANS was always 2
|
2022-06-08 18:58:07 -07:00 |
|
slmnemo
|
81d373c7ab
|
Fixed error related to bus being unable to complete a line write after a memory read followed by an idle and cachewrite request.
|
2022-06-08 17:34:02 -07:00 |
|
Madeleine Masser-Frye
|
0e64494e46
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-06-09 00:08:15 +00:00 |
|
Madeleine Masser-Frye
|
a58a756076
|
added one bit muxes for data critical synths
|
2022-06-09 00:06:12 +00:00 |
|
slmnemo
|
11924bdd9b
|
Fixed error where MEMREAD would go into INSTRREAD even when no INSTRREAD was pending
|
2022-06-08 15:59:15 -07:00 |
|
slmnemo
|
e17ee3073e
|
Fixed ifu displaying LSU bus state in wave.do
|
2022-06-08 15:30:32 -07:00 |
|
slmnemo
|
315c2f0669
|
Working version: Fixed error where Word count would always increment even without AHB to bus ACK
|
2022-06-08 15:29:32 -07:00 |
|
slmnemo
|
054cf5f7b0
|
Reworked AHB fsm to support one cycle latency read and writes, renamed key signals to better reflect their use, and fixed HTRANS errors
|
2022-06-08 15:03:15 -07:00 |
|
DTowersM
|
6402b2dec4
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-06-08 16:28:18 +00:00 |
|
DTowersM
|
6944996329
|
added #1 delays to Stalls and Flushes in hazard unit
|
2022-06-08 16:28:09 +00:00 |
|
slmnemo
|
284e0395a0
|
Merge branch 'main' into cacheburstmode
|
2022-06-08 02:21:33 +00:00 |
|
slmnemo
|
2d76953d42
|
Added lock signal to ensure AHB speaks with the right bus
|
2022-06-08 02:19:21 +00:00 |
|
David Harris
|
5240bd1c90
|
Modified RAM for single-cycle latency
|
2022-06-08 02:06:00 +00:00 |
|
David Harris
|
3c8eafc8ee
|
Cleaned bram interface
|
2022-06-08 01:39:44 +00:00 |
|
David Harris
|
9e5ab4d378
|
Added ahbapbbridge and cleaning RAM
|
2022-06-08 01:31:34 +00:00 |
|
DTowersM
|
a190342b8a
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-06-07 23:58:58 +00:00 |
|
DTowersM
|
02a424d65b
|
modified testbench.sv- now works with coremark
|
2022-06-07 23:58:50 +00:00 |
|
DTowersM
|
e324db71b4
|
cleaned up the <begin_signature> code, now works for code bases larger than 0x10000000
|
2022-06-07 23:27:54 +00:00 |
|
slmnemo
|
6d36150c3d
|
Fixed off-by-one error in busdp capture
|
2022-06-07 19:36:39 +00:00 |
|
slmnemo
|
73e0c1c07f
|
Reworked bus to handle burst interfacing
|
2022-06-07 11:22:53 +00:00 |
|
DTowersM
|
df330961b8
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-06-07 06:03:19 +00:00 |
|
DTowersM
|
590cf243bb
|
added support for 64 bit rv tests
|
2022-06-07 06:02:23 +00:00 |
|
Katherine Parry
|
cfcaddf8aa
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-06-06 16:06:54 +00:00 |
|
Katherine Parry
|
8fa0fc4229
|
fma synth warnings and errors removed
|
2022-06-06 16:06:04 +00:00 |
|
slmnemo
|
7f70655113
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-06-03 18:56:29 -07:00 |
|
slmnemo
|
3fe78c9084
|
Fixed recurrent issue with testbench where it would never stop
|
2022-06-03 18:56:24 -07:00 |
|
cturek
|
afdfe770fc
|
Added integer division in srt, parametrized everything to work with integers and floating points, parametrized testbench.
|
2022-06-04 00:14:10 +00:00 |
|
DTowersM
|
caaf56cbf7
|
testbench now reads begin_signature addr from .objdump.addr instead of from tests.vh
|
2022-06-03 22:07:14 +00:00 |
|
Madeleine Masser-Frye
|
56a053fc3d
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-06-03 21:08:49 +00:00 |
|
Madeleine Masser-Frye
|
31e9d0a41a
|
added muxes and inv, fixed priority encoder
|
2022-06-03 21:03:13 +00:00 |
|
Katherine Parry
|
fd980fe9d6
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-06-03 15:34:27 +00:00 |
|
Katherine Parry
|
6b39b8c702
|
fixed compilation errors
|
2022-06-03 15:34:17 +00:00 |
|
slmnemo
|
9d1dfbdb50
|
Changed NO_SPOOFING from 0 to 1 in buildroot-no-trace to better facilitate wally booting linux without following QEMU's trace
|
2022-06-03 04:55:14 -07:00 |
|
Katherine Parry
|
8420b1e87c
|
removed some debuging code accedentally pushed
|
2022-06-02 22:45:19 +00:00 |
|
Katherine Parry
|
6a4502e987
|
added rv64fpquad
|
2022-06-02 22:10:00 +00:00 |
|
Katherine Parry
|
cd8b2a2b98
|
added config rv64fpquad
|
2022-06-02 22:09:11 +00:00 |
|
David Harris
|
c74fec7fa6
|
renamed sim-fp to sim-testfloat
|
2022-06-02 15:05:29 -07:00 |
|
Katherine Parry
|
03280c0f9c
|
added createallvectors
|
2022-06-02 21:56:05 +00:00 |
|
slmnemo
|
c8515001a2
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-06-02 12:54:08 -07:00 |
|
Katherine Parry
|
9a09ee3a35
|
fpu paramaterized - except fdivsqrt
|
2022-06-02 19:50:28 +00:00 |
|
slmnemo
|
88454aa2ab
|
Revert "parametrized linux testbench's DEBUG_TRACE and added parameters to relevant calls of the linux testbench in wally-pipelined.do"
This reverts commit 89c7438424.
|
2022-06-02 12:45:21 -07:00 |
|
slmnemo
|
ad9e85beb9
|
Revert "Fixed buildroot by adding a second ."
This reverts commit 8b27c1884e.
|
2022-06-02 12:43:59 -07:00 |
|
slmnemo
|
65b8d0c32a
|
Revert "Added parameter to keep tracking on for buildroot and buildroot-checkpoint in regression.py"
This reverts commit e33ca59d46.
|
2022-06-02 12:41:01 -07:00 |
|
slmnemo
|
0d650b2880
|
Revert "Added parameters for DEBUG_TRACE to buildroot, buildroot-checkpoint, and buildroot-notrace"
This reverts commit e4024eb503.
|
2022-06-02 12:40:46 -07:00 |
|
David Harris
|
1d8bc2dc1b
|
Added stalls for pending SFENCE.VMA and FENCE.I in hazard unit
|
2022-06-02 09:37:59 -07:00 |
|
David Harris
|
154410a37f
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-06-02 15:48:36 +00:00 |
|
David Harris
|
faa15b1f8d
|
Cleaned up comments in controller
|
2022-06-02 15:48:33 +00:00 |
|
David Harris
|
197b588193
|
Cleaned up test cases in testbench
|
2022-06-02 08:44:28 -07:00 |
|
David Harris
|
c7ec9282fe
|
Provided sfencevmaM to hazard unit and renamed TLBFlush signals to sfencevma going into LSU/IFU. Preparing for SFENCE.VMA to flush the pipeline, but that is not yet working.
|
2022-06-02 14:18:55 +00:00 |
|
slmnemo
|
c16c5beef5
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-06-02 02:52:03 +00:00 |
|
slmnemo
|
65961223f8
|
Updated Linux testbench to use new force/unforce method for Branch predictor init and removed related .txt files
|
2022-06-02 02:51:51 +00:00 |
|
Katherine Parry
|
e42afbfb30
|
paramerterized some small fma units
|
2022-06-01 23:34:29 +00:00 |
|
DTowersM
|
215f69a2ab
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-06-01 21:00:51 +00:00 |
|
DTowersM
|
d28b4cf602
|
added support for embench post processing to testbench.sv
|
2022-06-01 21:00:44 +00:00 |
|
Katherine Parry
|
dd19e55b8f
|
unpacker optimizations
|
2022-06-01 16:52:21 +00:00 |
|
slmnemo
|
446ad498aa
|
Fixed double assignment on LSUBurstType
|
2022-06-01 01:04:49 +00:00 |
|
cturek
|
949f53695d
|
Fixed typos
|
2022-06-01 00:07:36 +00:00 |
|
slmnemo
|
cf05fec9c7
|
Added signals to change HTRANS to the correct signal based on schematic as well as a way to tell if we are not on the first access
|
2022-05-31 16:33:05 -07:00 |
|
slmnemo
|
a86c4d5ff3
|
Merge branch 'cacheburstmode' of github.com:davidharrishmc/riscv-wally into cacheburstmode
|
2022-05-31 15:57:55 -07:00 |
|
slmnemo
|
9ad1a42886
|
Redid the FSM to prepare for burst mode implementation
|
2022-05-31 15:57:42 -07:00 |
|
David Harris
|
475a84491e
|
Unpackinput cleanup
|
2022-05-31 22:31:21 +00:00 |
|
David Harris
|
f9533fea1a
|
Removed normalized output from unpack and simplified interface
|
2022-05-31 21:32:31 +00:00 |
|
David Harris
|
0d0a9cba66
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-05-31 21:12:45 +00:00 |
|
David Harris
|
aa7b0616e4
|
../src/privileged/csrc.sv
|
2022-05-31 21:12:17 +00:00 |
|
DTowersM
|
8903af3764
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-05-31 20:13:41 +00:00 |
|
DTowersM
|
525f6a6069
|
added testbench.sv support for embench tests, test output still WIP
|
2022-05-31 20:13:32 +00:00 |
|
DTowersM
|
0de54a01bf
|
removed delapidated signals SIE_REGW SIP_REGW TimerIntM SwIntM
|
2022-05-31 20:10:56 +00:00 |
|
DTowersM
|
95df88ae70
|
added embench tests to tests.vh
|
2022-05-31 20:08:04 +00:00 |
|
Katherine Parry
|
f6ac33ce8a
|
reorginized unpackinput signals
|
2022-05-31 17:40:34 +00:00 |
|
Katherine Parry
|
4ed7933aa3
|
added unpackinput.sv
|
2022-05-31 16:18:50 +00:00 |
|
David Harris
|
788fe406b5
|
Moved delegation logic from privmode to trap to simplify interface
|
2022-05-31 14:58:11 +00:00 |
|
David Harris
|
0cfe9e3373
|
Removed unused fp add and convert modules
|
2022-05-29 23:07:56 +00:00 |
|
Katherine Parry
|
950a17bef5
|
fixed lint error
|
2022-05-28 10:20:13 -07:00 |
|
slmnemo
|
4a8d0be32c
|
Reverted commit 60e3d7d81b
|
2022-05-28 04:00:01 -07:00 |
|
slmnemo
|
f18989e801
|
Revert Commit 6c61840045
|
2022-05-28 03:35:17 -07:00 |
|
slmnemo
|
60e3d7d81b
|
Changed NO_IE_MTIME_CHECKPOINT so it uses the new parameter name
|
2022-05-28 03:16:55 -07:00 |
|
slmnemo
|
6c61840045
|
Deparametrized Linux testbench and removed mentions of parameters in wally-pipelined.do
|
2022-05-28 03:14:49 -07:00 |
|
slmnemo
|
f78fa3b9b9
|
Reverted incorrect Ack
|
2022-05-28 10:06:26 +00:00 |
|
David Harris
|
b04e9ac1f6
|
fixed merge conflicts
|
2022-05-28 09:44:55 +00:00 |
|
David Harris
|
4237bb7abd
|
Added comments to some files, added a+b = 0 detector to comparator.sv
|
2022-05-28 09:41:48 +00:00 |
|
Katherine Parry
|
9c58c63864
|
removed unused signal from FMA
|
2022-05-27 16:47:56 -07:00 |
|
Katherine Parry
|
a0ff98042c
|
unpacker adds 1 to denorm expoents
|
2022-05-27 14:37:10 -07:00 |
|
Katherine Parry
|
95b506c5e0
|
some optimizations in unpacker
|
2022-05-27 11:36:04 -07:00 |
|
Katherine Parry
|
1be91753fe
|
moved lzc to generic and small optimizations on fcvt
|
2022-05-27 09:04:02 -07:00 |
|
Katherine Parry
|
c6d79cd718
|
Removed guard bit from fma rounding
|
2022-05-27 08:23:46 -07:00 |
|
slmnemo
|
bc17f883d4
|
changed ahb FSM and caught potential bug in ack/wordcountthreshold when on last word
|
2022-05-26 18:41:27 -07:00 |
|
slmnemo
|
847c7930c4
|
added LSUBurstDone signal to signal when a burst has finished
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2022-05-26 16:29:13 -07:00 |
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cturek
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5a0889016c
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fixed sizing issues in expcalc
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2022-05-26 22:35:17 +00:00 |
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cturek
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3301d7c52a
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Implemented on-the-fly conversion for unsigned numbers
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2022-05-26 22:20:43 +00:00 |
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Katherine Parry
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3c04f1bdec
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-05-26 20:48:30 +00:00 |
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Katherine Parry
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9d281b2604
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fcvt.sv paramaterized
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2022-05-26 20:48:22 +00:00 |
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slmnemo
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80fc716cd7
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Added signal to monitor HBURST and comments for each burst in busdp
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2022-05-26 13:35:49 -07:00 |
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DTowersM
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6f0b5753ee
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-05-26 19:05:21 +00:00 |
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DTowersM
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7ffef6ccfa
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fixed indent spacing (cosmetic change)
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2022-05-26 19:04:21 +00:00 |
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cturek
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4a4f153eef
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Set up the divider for on-the-fly conversion
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2022-05-26 16:45:28 +00:00 |
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slmnemo
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08430a1e85
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added burst size signals to the IFU, EBU, LSU, and busdp
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2022-05-25 18:02:50 -07:00 |
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slmnemo
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e8d97f0826
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-05-25 17:41:04 -07:00 |
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slmnemo
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a2300f063d
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added a todo to riscv-wally so that long buildroot looks for a successful boot rather than a specific instruction
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2022-05-25 17:40:57 -07:00 |
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slmnemo
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d1421b88ad
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Added line to testbench to prevent annoying burst sizes
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2022-05-25 17:29:45 -07:00 |
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slmnemo
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cebf93cf9c
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idk lol it says this has an unadded change
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2022-05-25 17:17:49 -07:00 |
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DTowersM
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de60b15cfe
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-05-26 00:12:46 +00:00 |
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slmnemo
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012cb7439d
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-05-25 17:11:03 -07:00 |
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slmnemo
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b5476204da
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see commit 9042cc3c
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2022-05-25 17:10:59 -07:00 |
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Katherine Parry
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f3b28b988b
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added fcvt.sv
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2022-05-26 00:10:51 +00:00 |
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DTowersM
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a1cda79cd5
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Merge branch 'embench' into main
embench contained the working makefiles for embench and is being merged into main as it working and done
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2022-05-26 00:10:50 +00:00 |
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DTowersM
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3f7eddbc89
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working makefile for embench and removed testbench-f64
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2022-05-26 00:08:18 +00:00 |
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slmnemo
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8422095a33
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-05-25 17:03:26 -07:00 |
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slmnemo
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4e5505f301
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added logic to prevent cache line length from exceeding the max size of a burst.
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2022-05-25 17:03:15 -07:00 |
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cturek
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c9845b96f4
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Renamed variables for readability
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2022-05-26 00:01:51 +00:00 |
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cturek
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51debfa186
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Fixed exponent verification, added sign module and added sign tests
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2022-05-25 23:36:21 +00:00 |
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Katherine Parry
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f35450207f
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single and double conversions pass all tests
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2022-05-25 23:02:02 +00:00 |
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Madeleine Masser-Frye
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81a869c921
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ppaAnalyze: docstrings and tsmc28 plotting
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2022-05-25 13:52:20 +00:00 |
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Madeleine Masser-Frye
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dd4997bd1b
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added support for tsmc28, fixed ff modules/analysis for timing
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2022-05-25 06:44:22 +00:00 |
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slmnemo
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0398aa02a0
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fixed a comment spelling typo
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2022-05-23 19:24:28 -07:00 |
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Katherine Parry
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576fe4ec24
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-05-23 23:11:41 +00:00 |
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Katherine Parry
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e5d2dfe94b
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added exponents to srt divider
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2022-05-23 23:07:27 +00:00 |
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David Harris
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d78451e39c
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Checked in qst2.c from James
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2022-05-23 20:26:05 +00:00 |
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Ross Thompson
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b70baed214
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-05-22 23:54:33 -05:00 |
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Ross Thompson
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e2cf941a23
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Possible plic fix?
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2022-05-22 23:47:01 -05:00 |
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Madeleine Masser-Frye
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d91fd44ea5
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-05-22 23:23:39 +00:00 |
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Madeleine Masser-Frye
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dbe4b4bafa
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added widths for csa in ppa
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2022-05-22 23:23:02 +00:00 |
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Ross Thompson
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bcb4ebf888
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-05-22 10:55:33 -05:00 |
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Ross Thompson
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c4f1a0362b
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Fixed receive fifo ITNR bug.
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2022-05-22 10:55:28 -05:00 |
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Ross Thompson
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92a2ad02db
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Added more debug signals to uart.
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2022-05-21 19:47:40 -05:00 |
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Madeleine Masser-Frye
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39a3bf5cdc
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-05-21 09:53:31 +00:00 |
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Madeleine Masser-Frye
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b832a21b73
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ppa updates
added widths to modules, automated frequency sweep synthesis, added slack violation color coding to plots
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2022-05-21 09:53:26 +00:00 |
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slmnemo
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e3a7e3e2f3
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changes suggested by ben, hopefully fixing buildroot (which is now not running)
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2022-05-20 18:42:38 -07:00 |
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Katherine Parry
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5d34db85b2
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Fixed unpacker bug LT EQ LE pass testfloat
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2022-05-20 17:19:50 +00:00 |
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slmnemo
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0afac6904e
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-05-19 18:31:56 -07:00 |
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slmnemo
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af0300c3d7
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added documentation for ahblite burst types to ahblite.sv
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2022-05-19 18:31:46 -07:00 |
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slmnemo
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11e703c8c0
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fixed lint autofailing due to no log being produced in regression-wally
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2022-05-19 18:30:59 -07:00 |
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slmnemo
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79c28d34dc
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-05-19 17:51:45 -07:00 |
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slmnemo
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e4024eb503
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Added parameters for DEBUG_TRACE to buildroot, buildroot-checkpoint, and buildroot-notrace
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2022-05-19 17:51:26 -07:00 |
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slmnemo
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e33ca59d46
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Added parameter to keep tracking on for buildroot and buildroot-checkpoint in regression.py
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2022-05-19 17:50:48 -07:00 |
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slmnemo
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8b27c1884e
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Fixed buildroot by adding a second .
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2022-05-19 17:49:32 -07:00 |
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slmnemo
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89c7438424
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parametrized linux testbench's DEBUG_TRACE and added parameters to relevant calls of the linux testbench in wally-pipelined.do
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2022-05-19 16:21:38 -07:00 |
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Katherine Parry
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ab1f088672
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fixed lint warning
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2022-05-19 20:34:06 +00:00 |
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Katherine Parry
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6f2d8c24ad
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Bug fixed in unpacker and sub/add/mul tests pass TestFloat
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2022-05-19 20:31:23 +00:00 |
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mmasserfrye
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bab7335bee
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-05-19 20:24:57 +00:00 |
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mmasserfrye
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d34f4a7c3c
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updated synth plotting and regression
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2022-05-19 20:24:47 +00:00 |
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Katherine Parry
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738bbf6479
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Added fp tests - doesnpass yet
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2022-05-19 16:32:30 +00:00 |
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slmnemo
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c96f07ad75
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added instructions to slack notifier
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2022-05-18 16:50:31 -07:00 |
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mmasserfrye
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84422f3859
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added support for plotting and fitting power
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2022-05-18 17:01:55 +00:00 |
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mmasserfrye
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f8722f04f9
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-05-18 16:10:36 +00:00 |
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mmasserfrye
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12c42cd507
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adapted shifter in ppa.sv for widths beside 32 and 64
modified plotting and regression in ppaAnalyze.py
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2022-05-18 16:08:40 +00:00 |
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Ross Thompson
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b853c4ba47
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Updated fpga debugger.
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2022-05-17 23:04:01 -05:00 |
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slmnemo
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23d6791b22
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simplified make-tests.sh to run the current makefile in regression
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2022-05-17 17:29:34 -07:00 |
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slmnemo
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82e68f2170
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Revert "same as last breaking commit, testing if the bisect works to output a breaking commit."
This reverts commit dcb485ec61.
gottem
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2022-05-17 17:26:33 -07:00 |
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slmnemo
|
dcb485ec61
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same as last breaking commit, testing if the bisect works to output a breaking commit.
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2022-05-17 17:22:09 -07:00 |
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slmnemo
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b7d036f3d0
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Revert "broke it again but this time it doesn't compile due to a missing semicolon on Rs1D."
This reverts commit f970cc3ea9.
fixed it
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2022-05-17 17:05:11 -07:00 |
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slmnemo
|
f970cc3ea9
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broke it again but this time it doesn't compile due to a missing semicolon on Rs1D.
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2022-05-17 17:03:16 -07:00 |
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slmnemo
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589bd0ca34
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Revert "Intentionally broke wally by setting datapath Rs1D to use bits 18:14 instead of 19:15 to test regression"
This reverts commit 4908f77cf9.
unbroke wally
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2022-05-17 16:57:29 -07:00 |
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slmnemo
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357d77d332
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Revert "Revert "Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main""
This reverts commit 0e3099743c.
reverted the wrong commit
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2022-05-17 16:57:00 -07:00 |
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