added burst size signals to the IFU, EBU, LSU, and busdp

pipelined/src/ebu/ahblite.sv

@@ -45,6 +45,7 @@ module ahblite (
   input logic 				 IFUBusRead,
   output logic [`XLEN-1:0] 	 IFUBusHRDATA,
   output logic 				 IFUBusAck,
+  input logic [2:0]    IFUBurstType,
   // Signals from Data Cache
   input logic [`PA_BITS-1:0] LSUBusAdr,
   input logic 				 LSUBusRead, 
@@ -52,6 +53,7 @@ module ahblite (
   input logic [`XLEN-1:0] 	 LSUBusHWDATA,
   output logic [`XLEN-1:0] 	 LSUBusHRDATA,
   input logic [2:0] 		 LSUBusSize,
+  input logic [2:0]      LSUBurstType,
   output logic 				 LSUBusAck,
   // AHB-Lite external signals
   (* mark_debug = "true" *) input logic [`AHBW-1:0] HRDATA,

pipelined/src/ifu/ifu.sv

@@ -41,6 +41,7 @@ module ifu (
 (* mark_debug = "true" *)	output logic [`PA_BITS-1:0] IFUBusAdr,
 (* mark_debug = "true" *)	output logic 				IFUBusRead,
 (* mark_debug = "true" *)	output logic 				IFUStallF,
+(* mark_debug = "true" *) output logic [2:0]  IFUBurstType,
 	(* mark_debug = "true" *) output logic [`XLEN-1:0] PCF, 
 	// Execute
 	output logic [`XLEN-1:0] 	PCLinkE,
@@ -190,7 +191,7 @@ module ifu (
     busdp #(WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) 
     busdp(.clk, .reset,
           .LSUBusHRDATA(IFUBusHRDATA), .LSUBusAck(IFUBusAck), .LSUBusWrite(), .LSUBusWriteCrit(),
-          .LSUBusRead(IFUBusRead), .LSUBusSize(), 
+          .LSUBusRead(IFUBusRead), .LSUBusSize(), .LSUBurstType(IFUBurstType),
           .LSUFunct3M(3'b010), .LSUBusAdr(IFUBusAdr), .DCacheBusAdr(ICacheBusAdr),
           .WordCount(), 
           .DCacheFetchLine(ICacheFetchLine),

pipelined/src/lsu/busdp.sv

@@ -42,7 +42,8 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED)
   input logic                 LSUBusAck,
   output logic                LSUBusWrite,
   output logic                LSUBusRead,
-  output logic [2:0]          LSUBusSize, 
+  output logic [2:0]          LSUBusSize,
+  output logic [2:0]          LSUBurstType,
   input logic [2:0]           LSUFunct3M,
   output logic [`PA_BITS-1:0] LSUBusAdr, // ** change name to HADDR to make ahb lite.
   output logic [LOGWPL-1:0]   WordCount,
@@ -67,6 +68,15 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED)
   localparam integer   WordCountThreshold = CACHE_ENABLED ? WORDSPERLINE - 1 : 0;
   logic [`PA_BITS-1:0]        LocalLSUBusAdr;
 
+  always_comb begin
+    case(WORDSPERLINE)
+      4:        LSUBurstType = 3'b010;
+      8:        LSUBurstType = 3'b100;
+      16:       LSUBurstType = 3'b110;
+      default:  LSUBurstType = 3'b000;
+    endcase
+  end
+
   // *** implement flops as an array if feasbile; DCacheBusWriteData might be a problem
   // *** better name than DCacheBusWriteData
   genvar                      index;

pipelined/src/lsu/lsu.sv

@@ -69,6 +69,7 @@ module lsu (
    (* mark_debug = "true" *)   input logic [`XLEN-1:0] LSUBusHRDATA,
    (* mark_debug = "true" *)   output logic [`XLEN-1:0] LSUBusHWDATA,
    (* mark_debug = "true" *)   output logic [2:0] LSUBusSize, 
+   (* mark_debug = "true" *)   output logic [2:0] LSUBurstType,
             // page table walker
    input logic [`XLEN-1:0]  SATP_REGW, // from csr
    input logic              STATUS_MXR, STATUS_SUM, STATUS_MPRV,
@@ -211,7 +212,7 @@ module lsu (
             
     busdp #(WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) busdp(
       .clk, .reset,
-      .LSUBusHRDATA, .LSUBusAck, .LSUBusWrite, .LSUBusRead, .LSUBusSize,
+      .LSUBusHRDATA, .LSUBusAck, .LSUBusWrite, .LSUBusRead, .LSUBusSize, .LSUBurstType,
       .WordCount, .LSUBusWriteCrit,
       .LSUFunct3M, .LSUBusAdr, .DCacheBusAdr, .DCacheFetchLine,
       .DCacheWriteLine, .DCacheBusAck, .DCacheBusWriteData, .LSUPAdrM,

pipelined/src/wally/wallypipelinedcore.sv

@@ -136,6 +136,7 @@ module wallypipelinedcore (
   logic [`XLEN-1:0]         IFUBusHRDATA;
   logic             IFUBusRead;
   logic             IFUBusAck;
+  logic [2:0]       IFUBurstType;
   
   // AHB LSU interface
   logic [`PA_BITS-1:0]         LSUBusAdr;
@@ -153,6 +154,7 @@ module wallypipelinedcore (
   logic [4:0]             InstrClassM;
   logic             InstrAccessFaultF;
   logic [2:0]             LSUBusSize;
+  logic [2:0]             LSUBurstType;
   
   logic             DCacheMiss;
   logic             DCacheAccess;
@@ -168,7 +170,7 @@ module wallypipelinedcore (
     .FlushF, .FlushD, .FlushE, .FlushM, 
     // Fetch
     .IFUBusHRDATA, .IFUBusAck, .PCF, .IFUBusAdr,
-    .IFUBusRead, .IFUStallF,
+    .IFUBusRead, .IFUStallF, .IFUBurstType,
     .ICacheAccess, .ICacheMiss,
 
     // Execute
@@ -249,7 +251,7 @@ module wallypipelinedcore (
   .ReadDataM, .FlushDCacheM,
   // connected to ahb (all stay the same)
   .LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusAck,
-  .LSUBusHRDATA, .LSUBusHWDATA, .LSUBusSize,
+  .LSUBusHRDATA, .LSUBusHWDATA, .LSUBusSize, .LSUBurstType,
 
     // connect to csr or privilege and stay the same.
     .PrivilegeModeW, .BigEndianM,          // connects to csr
@@ -281,11 +283,12 @@ module wallypipelinedcore (
      .clk, .reset,
      .UnsignedLoadM(1'b0), .AtomicMaskedM(2'b00),
      .IFUBusAdr,
-     .IFUBusRead, .IFUBusHRDATA, .IFUBusAck,
+     .IFUBusRead, .IFUBusHRDATA, .IFUBusAck, .IFUBurstType,
      // Signals from Data Cache
      .LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusHWDATA,
      .LSUBusHRDATA,
      .LSUBusSize,
+     .LSUBurstType,
      .LSUBusAck,
  
      .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn,