mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
This commit is contained in:
DTowersM
commit
9e2d80764d
4
.gitignore
vendored
4
.gitignore
vendored
@ -107,4 +107,6 @@ pipelined/config/rv64ic_orig
|
||||
synthDC/Summary.csv
|
||||
pipelined/srt/exptestgen
|
||||
pipelined/srt/testgen
|
||||
pipelined/srt/qst2
|
||||
pipelined/srt/qslc_r4a2
|
||||
pipelined/srt/qslc_r4a2.sv
|
||||
pipelined/srt/testvectors
|
||||
|
||||
@ -1,2 +1,2 @@
|
||||
vsim -do "do wally-pipelined.do rv32gc arch32f"
|
||||
vsim -do "do wally-pipelined.do rv32gc arch32i"
|
||||
|
||||
|
||||
@ -6,7 +6,7 @@ add wave -noupdate /testbench/reset_ext
|
||||
add wave -noupdate /testbench/memfilename
|
||||
add wave -noupdate /testbench/dut/core/SATP_REGW
|
||||
add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/BPPredWrongE
|
||||
add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/CSRWritePendingDEM
|
||||
add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/CSRWriteFencePendingDEM
|
||||
add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/RetM
|
||||
add wave -noupdate -group HDU -group hazards -color Pink /testbench/dut/core/hzu/TrapM
|
||||
add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/LoadStallD
|
||||
@ -468,7 +468,7 @@ add wave -noupdate -group {debug trace} -expand -group wb /testbench/PCW
|
||||
add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PCNext2F
|
||||
add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PrivilegedNextPCM
|
||||
add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PrivilegedChangePCM
|
||||
add wave -noupdate -group ifu -color Gold /testbench/dut/core/lsu/bus/busdp/busfsm/BusCurrState
|
||||
add wave -noupdate -group ifu -color Gold /testbench/dut/core/ifu/bus/busdp/busfsm/BusCurrState
|
||||
add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUBusRead
|
||||
add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUBusAdr
|
||||
add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUBusAck
|
||||
|
||||
@ -525,6 +525,30 @@ module ppa_decoder #(parameter WIDTH = 8) (
|
||||
end
|
||||
endmodule
|
||||
|
||||
module ppa_mux2_1 #(parameter WIDTH = 1) (
|
||||
input logic [WIDTH-1:0] d0, d1,
|
||||
input logic s,
|
||||
output logic [WIDTH-1:0] y);
|
||||
|
||||
assign y = s ? d1 : d0;
|
||||
endmodule
|
||||
|
||||
module ppa_mux4_1 #(parameter WIDTH = 1) (
|
||||
input logic [WIDTH-1:0] d0, d1, d2, d3,
|
||||
input logic [1:0] s,
|
||||
output logic [WIDTH-1:0] y);
|
||||
|
||||
assign y = s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0);
|
||||
endmodule
|
||||
|
||||
module ppa_mux8_1 #(parameter WIDTH = 1) (
|
||||
input logic [WIDTH-1:0] d0, d1, d2, d3, d4, d5, d6, d7,
|
||||
input logic [2:0] s,
|
||||
output logic [WIDTH-1:0] y);
|
||||
|
||||
assign y = s[2] ? (s[1] ? (s[0] ? d5 : d4) : (s[0] ? d6 : d7)) : (s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0));
|
||||
endmodule
|
||||
|
||||
module ppa_mux2_8 #(parameter WIDTH = 8) (
|
||||
input logic [WIDTH-1:0] d0, d1,
|
||||
input logic s,
|
||||
|
||||
@ -53,18 +53,18 @@ module ram #(parameter BASE=0, RANGE = 65535) (
|
||||
logic [31:0] HADDRD, RamAddr;
|
||||
//logic prevHREADYRam, risingHREADYRam;
|
||||
logic initTrans;
|
||||
logic memwrite, memwriteD;
|
||||
logic memwrite, memwriteD, memread;
|
||||
logic nextHREADYRam;
|
||||
//logic [3:0] busycount;
|
||||
|
||||
swbytemask swbytemask(.Size(HSIZED[1:0]), .Adr(HADDRD[2:0]), .ByteMask(ByteMask));
|
||||
|
||||
assign initTrans = HREADY & HSELRam & (HTRANS != 2'b00); // *** add burst support, or disable on busy
|
||||
assign memwrite = initTrans & HWRITE;
|
||||
|
||||
// *** this seems like a weird way to use reset
|
||||
flopen #(1) memwritereg(HCLK, initTrans | ~HRESETn, memwrite, memwriteD); // probably drop ~HRESETn in all this
|
||||
flopen #(32) haddrreg(HCLK, initTrans | ~HRESETn, HADDR, HADDRD);
|
||||
assign initTrans = HREADY & HSELRam & (HTRANS[1]);
|
||||
assign memwrite = initTrans & HWRITE; // *** why is initTrans needed? See CLINT interface
|
||||
assign memread = initTrans & ~HWRITE;
|
||||
|
||||
flopenr #(1) memwritereg(HCLK, ~HRESETn, HREADY, memwrite, memwriteD);
|
||||
flopenr #(32) haddrreg(HCLK, ~HRESETn, HREADY, HADDR, HADDRD);
|
||||
|
||||
/* // busy FSM to extend READY signal
|
||||
always @(posedge HCLK, negedge HRESETn)
|
||||
@ -85,7 +85,9 @@ module ram #(parameter BASE=0, RANGE = 65535) (
|
||||
end */
|
||||
|
||||
|
||||
assign nextHREADYRam = ~(memwriteD & ~memwrite);
|
||||
// Stall on a read after a write because the RAM can't take both adddresses on the same cycle
|
||||
assign nextHREADYRam = ~(memwriteD & memread);
|
||||
// assign nextHREADYRam = ~(memwriteD & ~memwrite);
|
||||
flopr #(1) readyreg(HCLK, ~HRESETn, nextHREADYRam, HREADYRam);
|
||||
// assign HREADYRam = ~(memwriteD & ~memwrite);
|
||||
assign HRESPRam = 0; // OK
|
||||
@ -109,8 +111,8 @@ module ram #(parameter BASE=0, RANGE = 65535) (
|
||||
|
||||
|
||||
|
||||
// On writes, use address delayed by one cycle to sync with HWDATA
|
||||
mux2 #(32) adrmux(HADDR, HADDRD, memwriteD, RamAddr);
|
||||
// On writes or during a wait state, use address delayed by one cycle to sync RamAddr with HWDATA or hold stalled address
|
||||
mux2 #(32) adrmux(HADDR, HADDRD, memwriteD | ~HREADY, RamAddr);
|
||||
|
||||
// single-ported RAM
|
||||
bram1p1rw #(`XLEN/8, 8, ADDR_WIDTH)
|
||||
|
||||
@ -92,7 +92,7 @@ module uncore (
|
||||
// generate
|
||||
// on-chip RAM
|
||||
if (`RAM_SUPPORTED) begin : ram
|
||||
ram_orig #(
|
||||
ram #(
|
||||
.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (
|
||||
.HCLK, .HRESETn,
|
||||
.HSELRam, .HADDR,
|
||||
|
||||
@ -1,16 +1,19 @@
|
||||
all: sqrttestgen testgen qst2
|
||||
all: exptestgen testgen qslc_r4a2
|
||||
|
||||
sqrttestgen: sqrttestgen.c
|
||||
gcc sqrttestgen.c -lm -o sqrttestgen
|
||||
gcc sqrttestgen.c -o sqrttestgen -lm
|
||||
|
||||
testgen: testgen.c
|
||||
gcc testgen.c -lm -o testgen
|
||||
|
||||
qst2: qst2.c
|
||||
gcc qst2.c -lm -o qst2
|
||||
gcc -lm -o testgen testgen.c
|
||||
gcc testgen.c -o testgen -lm
|
||||
./testgen
|
||||
|
||||
exptestgen: exptestgen.c
|
||||
gcc -lm -o exptestgen exptestgen.c
|
||||
gcc -o exptestgen exptestgen.c -lm
|
||||
./exptestgen
|
||||
|
||||
qslc_r4a2: qslc_r4a2.c
|
||||
gcc qslc_r4a2.c -o qslc_r4a2 -lm
|
||||
./qslc_r4a2 > qslc_r4a2.sv
|
||||
|
||||
clean:
|
||||
rm -f testgen exptestgen qslc_r4a2
|
||||
|
||||
198
pipelined/srt/qslc_r4a2.c
Normal file
198
pipelined/srt/qslc_r4a2.c
Normal file
@ -0,0 +1,198 @@
|
||||
/*
|
||||
Program: qslc_r4a2.c
|
||||
Description: Prints out Quotient Selection Table (assumes CPA is utilized to reduce memory)
|
||||
User: James E. Stine
|
||||
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
#include <math.h>
|
||||
|
||||
#define DIVISOR_SIZE 3
|
||||
#define CARRY_SIZE 7
|
||||
#define SUM_SIZE 7
|
||||
#define TOT_SIZE 7
|
||||
|
||||
void disp_binary(double, int, int);
|
||||
|
||||
struct bits {
|
||||
unsigned int divisor : DIVISOR_SIZE;
|
||||
int tot : TOT_SIZE;
|
||||
} pla;
|
||||
|
||||
/*
|
||||
|
||||
Function: disp_binary
|
||||
Description: This function displays a Double-Precision number into
|
||||
four 16 bit integers using the global union variable
|
||||
dp_number
|
||||
Argument List: double x The value to be converted
|
||||
int bits_to_left Number of bits left of radix point
|
||||
int bits_to_right Number of bits right of radix point
|
||||
Return value: none
|
||||
|
||||
*/
|
||||
void disp_binary(double x, int bits_to_left, int bits_to_right) {
|
||||
int i;
|
||||
double diff;
|
||||
|
||||
if (fabs(x) < pow(2.0, ((double) -bits_to_right)) ) {
|
||||
for (i = -bits_to_left + 1; i <= bits_to_right; i++) {
|
||||
printf("0");
|
||||
}
|
||||
if (i == bits_to_right+1)
|
||||
;
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
if (x < 0.0)
|
||||
x = pow(2.0, ((double) bits_to_left)) + x;
|
||||
|
||||
for (i = -bits_to_left + 1; i <= bits_to_right; i++) {
|
||||
diff = pow(2.0, ((double) -i) );
|
||||
if (x < diff)
|
||||
printf("0");
|
||||
else {
|
||||
printf("1");
|
||||
x -= diff;
|
||||
}
|
||||
if (i == 0)
|
||||
;
|
||||
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
int main() {
|
||||
int m;
|
||||
int n;
|
||||
int o;
|
||||
pla.divisor = 0;
|
||||
pla.tot = 0;
|
||||
printf("\tcase({D[5:3],Wmsbs})\n");
|
||||
for (o=0; o < pow(2.0, DIVISOR_SIZE); o++) {
|
||||
for (m=0; m < pow(2.0, TOT_SIZE); m++) {
|
||||
printf("\t\t10'b");
|
||||
disp_binary((double) pla.divisor, DIVISOR_SIZE, 0);
|
||||
printf("_");
|
||||
disp_binary((double) pla.tot, TOT_SIZE, 0);
|
||||
printf(": q = 4'b");
|
||||
|
||||
/*
|
||||
4 bits for Radix 4 (a=2)
|
||||
1000 = +2
|
||||
0100 = +1
|
||||
0000 = 0
|
||||
0010 = -1
|
||||
0001 = -2
|
||||
*/
|
||||
switch (pla.divisor) {
|
||||
case 0:
|
||||
if ((pla.tot) >= 12)
|
||||
printf("1000");
|
||||
else if ((pla.tot) >= 4)
|
||||
printf("0100");
|
||||
else if ((pla.tot) >= -4)
|
||||
printf("0000");
|
||||
else if ((pla.tot) >= -13)
|
||||
printf("0010");
|
||||
else
|
||||
printf("0001");
|
||||
break;
|
||||
case 1:
|
||||
if ((pla.tot) >= 14)
|
||||
printf("1000");
|
||||
else if ((pla.tot) >= 4)
|
||||
printf("0100");
|
||||
else if ((pla.tot) >= -6)
|
||||
printf("0000");
|
||||
else if ((pla.tot) >= -15)
|
||||
printf("0010");
|
||||
else
|
||||
printf("0001");
|
||||
break;
|
||||
case 2:
|
||||
if ((pla.tot) >= 15)
|
||||
printf("1000");
|
||||
else if ((pla.tot) >= 4)
|
||||
printf("0100");
|
||||
else if ((pla.tot) >= -6)
|
||||
printf("0000");
|
||||
else if ((pla.tot) >= -16)
|
||||
printf("0010");
|
||||
else
|
||||
printf("0001");
|
||||
break;
|
||||
case 3:
|
||||
if ((pla.tot) >= 16)
|
||||
printf("1000");
|
||||
else if ((pla.tot) >= 4)
|
||||
printf("0100");
|
||||
else if ((pla.tot) >= -6)
|
||||
printf("0000");
|
||||
else if ((pla.tot) >= -18)
|
||||
printf("0010");
|
||||
else
|
||||
printf("0001");
|
||||
break;
|
||||
case 4:
|
||||
if ((pla.tot) >= 18)
|
||||
printf("1000");
|
||||
else if ((pla.tot) >= 6)
|
||||
printf("0100");
|
||||
else if ((pla.tot) >= -8)
|
||||
printf("0000");
|
||||
else if ((pla.tot) >= -20)
|
||||
printf("0010");
|
||||
else
|
||||
printf("0001");
|
||||
break;
|
||||
case 5:
|
||||
if ((pla.tot) >= 20)
|
||||
printf("1000");
|
||||
else if ((pla.tot) >= 6)
|
||||
printf("0100");
|
||||
else if ((pla.tot) >= -8)
|
||||
printf("0000");
|
||||
else if ((pla.tot) >= -20)
|
||||
printf("0010");
|
||||
else
|
||||
printf("0001");
|
||||
break;
|
||||
case 6:
|
||||
if ((pla.tot) >= 20)
|
||||
printf("1000");
|
||||
else if ((pla.tot) >= 8)
|
||||
printf("0100");
|
||||
else if ((pla.tot) >= -8)
|
||||
printf("0000");
|
||||
else if ((pla.tot) >= -22)
|
||||
printf("0010");
|
||||
else
|
||||
printf("0001");
|
||||
break;
|
||||
case 7:
|
||||
if ((pla.tot) >= 24)
|
||||
printf("1000");
|
||||
else if ((pla.tot) >= 8)
|
||||
printf("0100");
|
||||
else if ((pla.tot) >= -8)
|
||||
printf("0000");
|
||||
else if ((pla.tot) >= -24)
|
||||
printf("0010");
|
||||
else
|
||||
printf("0001");
|
||||
break;
|
||||
default: printf ("XXX");
|
||||
|
||||
}
|
||||
|
||||
printf(";\n");
|
||||
(pla.tot)++;
|
||||
}
|
||||
(pla.divisor)++;
|
||||
}
|
||||
printf("\tendcase\n");
|
||||
|
||||
}
|
||||
@ -1,201 +0,0 @@
|
||||
/*
|
||||
Program: qst2.c
|
||||
Description: Prints out QST (assumes CPA is utilized to reduce memory)
|
||||
User: James E. Stine
|
||||
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
#include <math.h>
|
||||
|
||||
#define DIVISOR_SIZE 3
|
||||
#define CARRY_SIZE 7
|
||||
#define SUM_SIZE 7
|
||||
#define TOT_SIZE 7
|
||||
|
||||
void disp_binary(double, int, int);
|
||||
|
||||
struct bits {
|
||||
unsigned int divisor : DIVISOR_SIZE;
|
||||
int tot : TOT_SIZE;
|
||||
} pla;
|
||||
|
||||
/*
|
||||
|
||||
Function: disp_binary
|
||||
Description: This function displays a Double-Precision number into
|
||||
four 16 bit integers using the global union variable
|
||||
dp_number
|
||||
Argument List: double x The value to be converted
|
||||
int bits_to_left Number of bits left of radix point
|
||||
int bits_to_right Number of bits right of radix point
|
||||
Return value: none
|
||||
|
||||
*/
|
||||
void disp_binary(double x, int bits_to_left, int bits_to_right) {
|
||||
int i;
|
||||
double diff;
|
||||
|
||||
if (fabs(x) < pow(2.0, ((double) -bits_to_right)) ) {
|
||||
for (i = -bits_to_left + 1; i <= bits_to_right; i++) {
|
||||
printf("0");
|
||||
}
|
||||
if (i == bits_to_right+1)
|
||||
printf(" ");
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
if (x < 0.0)
|
||||
x = pow(2.0, ((double) bits_to_left)) + x;
|
||||
|
||||
for (i = -bits_to_left + 1; i <= bits_to_right; i++) {
|
||||
diff = pow(2.0, ((double) -i) );
|
||||
if (x < diff)
|
||||
printf("0");
|
||||
else {
|
||||
printf("1");
|
||||
x -= diff;
|
||||
}
|
||||
if (i == 0)
|
||||
printf(" ");
|
||||
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
int main() {
|
||||
|
||||
int m;
|
||||
int n;
|
||||
int o;
|
||||
pla.divisor = 0;
|
||||
pla.tot = 0;
|
||||
|
||||
for (o=0; o < pow(2.0, DIVISOR_SIZE); o++) {
|
||||
for (m=0; m < pow(2.0, TOT_SIZE); m++) {
|
||||
disp_binary((double) pla.divisor, DIVISOR_SIZE, 0);
|
||||
disp_binary((double) pla.tot, TOT_SIZE, 0);
|
||||
|
||||
/*
|
||||
4 bits for Radix 4 (a=2)
|
||||
1000 = +2
|
||||
0100 = +1
|
||||
0000 = 0
|
||||
0010 = -1
|
||||
0001 = -2
|
||||
|
||||
*/
|
||||
|
||||
switch (pla.divisor) {
|
||||
|
||||
case 0:
|
||||
if ((pla.tot) >= 12)
|
||||
printf(" 1000");
|
||||
else if ((pla.tot) >= 4)
|
||||
printf(" 0100");
|
||||
else if ((pla.tot) >= -4)
|
||||
printf(" 0000");
|
||||
else if ((pla.tot) >= -13)
|
||||
printf(" 0010");
|
||||
else
|
||||
printf(" 0001");
|
||||
break;
|
||||
case 1:
|
||||
if ((pla.tot) >= 14)
|
||||
printf(" 1000");
|
||||
else if ((pla.tot) >= 4)
|
||||
printf(" 0100");
|
||||
else if ((pla.tot) >= -6)
|
||||
printf(" 0000");
|
||||
else if ((pla.tot) >= -15)
|
||||
printf(" 0010");
|
||||
else
|
||||
printf(" 0001");
|
||||
break;
|
||||
case 2:
|
||||
if ((pla.tot) >= 15)
|
||||
printf(" 1000");
|
||||
else if ((pla.tot) >= 4)
|
||||
printf(" 0100");
|
||||
else if ((pla.tot) >= -6)
|
||||
printf(" 0000");
|
||||
else if ((pla.tot) >= -16)
|
||||
printf(" 0010");
|
||||
else
|
||||
printf(" 0001");
|
||||
break;
|
||||
case 3:
|
||||
if ((pla.tot) >= 16)
|
||||
printf(" 1000");
|
||||
else if ((pla.tot) >= 4)
|
||||
printf(" 0100");
|
||||
else if ((pla.tot) >= -6)
|
||||
printf(" 0000");
|
||||
else if ((pla.tot) >= -18)
|
||||
printf(" 0010");
|
||||
else
|
||||
printf(" 0001");
|
||||
break;
|
||||
case 4:
|
||||
if ((pla.tot) >= 18)
|
||||
printf(" 1000");
|
||||
else if ((pla.tot) >= 6)
|
||||
printf(" 0100");
|
||||
else if ((pla.tot) >= -8)
|
||||
printf(" 0000");
|
||||
else if ((pla.tot) >= -20)
|
||||
printf(" 0010");
|
||||
else
|
||||
printf(" 0001");
|
||||
break;
|
||||
case 5:
|
||||
if ((pla.tot) >= 20)
|
||||
printf(" 1000");
|
||||
else if ((pla.tot) >= 6)
|
||||
printf(" 0100");
|
||||
else if ((pla.tot) >= -8)
|
||||
printf(" 0000");
|
||||
else if ((pla.tot) >= -20)
|
||||
printf(" 0010");
|
||||
else
|
||||
printf(" 0001");
|
||||
break;
|
||||
case 6:
|
||||
if ((pla.tot) >= 20)
|
||||
printf(" 1000");
|
||||
else if ((pla.tot) >= 8)
|
||||
printf(" 0100");
|
||||
else if ((pla.tot) >= -8)
|
||||
printf(" 0000");
|
||||
else if ((pla.tot) >= -22)
|
||||
printf(" 0010");
|
||||
else
|
||||
printf(" 0001");
|
||||
break;
|
||||
case 7:
|
||||
if ((pla.tot) >= 24)
|
||||
printf(" 1000");
|
||||
else if ((pla.tot) >= 8)
|
||||
printf(" 0100");
|
||||
else if ((pla.tot) >= -8)
|
||||
printf(" 0000");
|
||||
else if ((pla.tot) >= -24)
|
||||
printf(" 0010");
|
||||
else
|
||||
printf(" 0001");
|
||||
break;
|
||||
default:
|
||||
printf (" XXX");
|
||||
|
||||
}
|
||||
|
||||
printf("\n");
|
||||
(pla.tot)++;
|
||||
}
|
||||
(pla.divisor)++;
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
1
pipelined/srt/stine/README
Executable file
1
pipelined/srt/stine/README
Executable file
@ -0,0 +1 @@
|
||||
vsim -do iter64.do -c
|
||||
22
pipelined/srt/stine/README.md
Executable file
22
pipelined/srt/stine/README.md
Executable file
@ -0,0 +1,22 @@
|
||||
This is a novel integer divider using r4 division by recurrence. The
|
||||
reference is:
|
||||
|
||||
J. E. Stine and K. Hill, "An Efficient Implementation of Radix-4
|
||||
Integer Division Using Scaling," 2020 IEEE 63rd International Midwest
|
||||
Symposium on Circuits and Systems (MWSCAS), Springfield, MA, USA,
|
||||
2020, pp. 1092-1095, doi: 10.1109/MWSCAS48704.2020.9184631.
|
||||
|
||||
Although this version does not contain scaling, it could do this, if
|
||||
needed. Moreover, a higher radix or overlapped radix can be done
|
||||
easily to expand the the size. Also, the implementations here are
|
||||
initially unsigned but hope to expand for signed, which should be
|
||||
easy.
|
||||
|
||||
There are two types of tests in this directory within each testbench.
|
||||
One tests for 32-bits and the other 64-bits:
|
||||
|
||||
int32div.do and int64div.do = test individual vector for debugging
|
||||
|
||||
iter32.do and iter64.do = do not use any waveform generation and just
|
||||
output lots of tests
|
||||
|
||||
19
pipelined/srt/stine/checkme.sh
Executable file
19
pipelined/srt/stine/checkme.sh
Executable file
@ -0,0 +1,19 @@
|
||||
#!/bin/sh
|
||||
cat iter64_signed.out | grep "0 1$"
|
||||
cat iter64_signed.out | grep "1 0$"
|
||||
cat iter64_signed.out | grep "0 0$"
|
||||
cat iter64_unsigned.out | grep "0 1$"
|
||||
cat iter64_unsigned.out | grep "1 0$"
|
||||
cat iter64_unsigned.out | grep "0 0$"
|
||||
cat iter32_signed.out | grep "0 1$"
|
||||
cat iter32_signed.out | grep "1 0$"
|
||||
cat iter32_signed.out | grep "0 0$"
|
||||
cat iter32_unsigned.out | grep "0 1$"
|
||||
cat iter32_unsigned.out | grep "1 0$"
|
||||
cat iter32_unsigned.out | grep "0 0$"
|
||||
cat iter128_signed.out | grep "0 1$"
|
||||
cat iter128_signed.out | grep "1 0$"
|
||||
cat iter128_signed.out | grep "0 0$"
|
||||
cat iter128_unsigned.out | grep "0 1$"
|
||||
cat iter128_unsigned.out | grep "1 0$"
|
||||
cat iter128_unsigned.out | grep "0 0$"
|
||||
27
pipelined/srt/stine/idiv-config.vh
Normal file
27
pipelined/srt/stine/idiv-config.vh
Normal file
@ -0,0 +1,27 @@
|
||||
//////////////////////////////////////////
|
||||
// wally-config.vh
|
||||
//
|
||||
// Written: james.stine@okstate.edu 9 June 2022
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Specify which features are configured
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
// Integer division tests
|
||||
`define IDIV_TESTS 1048576
|
||||
2802
pipelined/srt/stine/intdiv.sv
Executable file
2802
pipelined/srt/stine/intdiv.sv
Executable file
File diff suppressed because it is too large
Load Diff
50
pipelined/srt/stine/iter128.do
Normal file
50
pipelined/srt/stine/iter128.do
Normal file
@ -0,0 +1,50 @@
|
||||
# Copyright 1991-2007 Mentor Graphics Corporation
|
||||
#
|
||||
# Modification by Oklahoma State University
|
||||
# Use with Testbench
|
||||
# James Stine, 2008
|
||||
# Go Cowboys!!!!!!
|
||||
#
|
||||
# All Rights Reserved.
|
||||
#
|
||||
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
|
||||
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
|
||||
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
|
||||
|
||||
# Use this run.do file to run this example.
|
||||
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
|
||||
# do run.do
|
||||
# or, to run from a shell, type the following at the shell prompt:
|
||||
# vsim -do run.do -c
|
||||
# (omit the "-c" to see the GUI while running from the shell)
|
||||
|
||||
onbreak {resume}
|
||||
|
||||
# create library
|
||||
if [file exists work] {
|
||||
vdel -all
|
||||
}
|
||||
vlib work
|
||||
|
||||
# compile source files
|
||||
vlog mux.sv lod.sv shift.sv intdiv.sv test_iter128.sv
|
||||
|
||||
# start and run simulation
|
||||
vsim -voptargs=+acc work.tb
|
||||
|
||||
|
||||
-- Set Wave Output Items
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreZoom {0 ps} {75 ns}
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
|
||||
-- Run the Simulation
|
||||
run 999586700ns
|
||||
quit
|
||||
50
pipelined/srt/stine/iter128S.do
Normal file
50
pipelined/srt/stine/iter128S.do
Normal file
@ -0,0 +1,50 @@
|
||||
# Copyright 1991-2007 Mentor Graphics Corporation
|
||||
#
|
||||
# Modification by Oklahoma State University
|
||||
# Use with Testbench
|
||||
# James Stine, 2008
|
||||
# Go Cowboys!!!!!!
|
||||
#
|
||||
# All Rights Reserved.
|
||||
#
|
||||
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
|
||||
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
|
||||
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
|
||||
|
||||
# Use this run.do file to run this example.
|
||||
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
|
||||
# do run.do
|
||||
# or, to run from a shell, type the following at the shell prompt:
|
||||
# vsim -do run.do -c
|
||||
# (omit the "-c" to see the GUI while running from the shell)
|
||||
|
||||
onbreak {resume}
|
||||
|
||||
# create library
|
||||
if [file exists work] {
|
||||
vdel -all
|
||||
}
|
||||
vlib work
|
||||
|
||||
# compile source files
|
||||
vlog mux.sv lod.sv shift.sv intdiv.sv test_iter128S.sv
|
||||
|
||||
# start and run simulation
|
||||
vsim -voptargs=+acc work.tb
|
||||
|
||||
|
||||
-- Set Wave Output Items
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreZoom {0 ps} {75 ns}
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
|
||||
-- Run the Simulation
|
||||
run 999586700ns
|
||||
quit
|
||||
50
pipelined/srt/stine/iter32.do
Executable file
50
pipelined/srt/stine/iter32.do
Executable file
@ -0,0 +1,50 @@
|
||||
# Copyright 1991-2007 Mentor Graphics Corporation
|
||||
#
|
||||
# Modification by Oklahoma State University
|
||||
# Use with Testbench
|
||||
# James Stine, 2008
|
||||
# Go Cowboys!!!!!!
|
||||
#
|
||||
# All Rights Reserved.
|
||||
#
|
||||
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
|
||||
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
|
||||
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
|
||||
|
||||
# Use this run.do file to run this example.
|
||||
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
|
||||
# do run.do
|
||||
# or, to run from a shell, type the following at the shell prompt:
|
||||
# vsim -do run.do -c
|
||||
# (omit the "-c" to see the GUI while running from the shell)
|
||||
|
||||
onbreak {resume}
|
||||
|
||||
# create library
|
||||
if [file exists work] {
|
||||
vdel -all
|
||||
}
|
||||
vlib work
|
||||
|
||||
# compile source files
|
||||
vlog mux.sv lod.sv shift.sv intdiv.sv test_iter32.sv
|
||||
|
||||
# start and run simulation
|
||||
vsim -voptargs=+acc work.tb
|
||||
|
||||
|
||||
-- Set Wave Output Items
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreZoom {0 ps} {75 ns}
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
|
||||
-- Run the Simulation
|
||||
run 999586700ns
|
||||
quit
|
||||
50
pipelined/srt/stine/iter32S.do
Normal file
50
pipelined/srt/stine/iter32S.do
Normal file
@ -0,0 +1,50 @@
|
||||
# Copyright 1991-2007 Mentor Graphics Corporation
|
||||
#
|
||||
# Modification by Oklahoma State University
|
||||
# Use with Testbench
|
||||
# James Stine, 2008
|
||||
# Go Cowboys!!!!!!
|
||||
#
|
||||
# All Rights Reserved.
|
||||
#
|
||||
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
|
||||
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
|
||||
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
|
||||
|
||||
# Use this run.do file to run this example.
|
||||
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
|
||||
# do run.do
|
||||
# or, to run from a shell, type the following at the shell prompt:
|
||||
# vsim -do run.do -c
|
||||
# (omit the "-c" to see the GUI while running from the shell)
|
||||
|
||||
onbreak {resume}
|
||||
|
||||
# create library
|
||||
if [file exists work] {
|
||||
vdel -all
|
||||
}
|
||||
vlib work
|
||||
|
||||
# compile source files
|
||||
vlog mux.sv lod.sv shift.sv intdiv.sv test_iter32S.sv
|
||||
|
||||
# start and run simulation
|
||||
vsim -voptargs=+acc work.tb
|
||||
|
||||
|
||||
-- Set Wave Output Items
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreZoom {0 ps} {75 ns}
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
|
||||
-- Run the Simulation
|
||||
run 999586700ns
|
||||
quit
|
||||
50
pipelined/srt/stine/iter64.do
Executable file
50
pipelined/srt/stine/iter64.do
Executable file
@ -0,0 +1,50 @@
|
||||
# Copyright 1991-2007 Mentor Graphics Corporation
|
||||
#
|
||||
# Modification by Oklahoma State University
|
||||
# Use with Testbench
|
||||
# James Stine, 2008
|
||||
# Go Cowboys!!!!!!
|
||||
#
|
||||
# All Rights Reserved.
|
||||
#
|
||||
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
|
||||
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
|
||||
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
|
||||
|
||||
# Use this run.do file to run this example.
|
||||
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
|
||||
# do run.do
|
||||
# or, to run from a shell, type the following at the shell prompt:
|
||||
# vsim -do run.do -c
|
||||
# (omit the "-c" to see the GUI while running from the shell)
|
||||
|
||||
onbreak {resume}
|
||||
|
||||
# create library
|
||||
if [file exists work] {
|
||||
vdel -all
|
||||
}
|
||||
vlib work
|
||||
|
||||
# compile source files
|
||||
vlog mux.sv lod.sv shift.sv intdiv.sv test_iter64.sv
|
||||
|
||||
# start and run simulation
|
||||
vsim -voptargs=+acc work.tb
|
||||
|
||||
|
||||
-- Set Wave Output Items
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreZoom {0 ps} {75 ns}
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
|
||||
-- Run the Simulation
|
||||
run 999586700ns
|
||||
quit
|
||||
50
pipelined/srt/stine/iter64S.do
Normal file
50
pipelined/srt/stine/iter64S.do
Normal file
@ -0,0 +1,50 @@
|
||||
# Copyright 1991-2007 Mentor Graphics Corporation
|
||||
#
|
||||
# Modification by Oklahoma State University
|
||||
# Use with Testbench
|
||||
# James Stine, 2008
|
||||
# Go Cowboys!!!!!!
|
||||
#
|
||||
# All Rights Reserved.
|
||||
#
|
||||
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
|
||||
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
|
||||
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
|
||||
|
||||
# Use this run.do file to run this example.
|
||||
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
|
||||
# do run.do
|
||||
# or, to run from a shell, type the following at the shell prompt:
|
||||
# vsim -do run.do -c
|
||||
# (omit the "-c" to see the GUI while running from the shell)
|
||||
|
||||
onbreak {resume}
|
||||
|
||||
# create library
|
||||
if [file exists work] {
|
||||
vdel -all
|
||||
}
|
||||
vlib work
|
||||
|
||||
# compile source files
|
||||
vlog mux.sv lod.sv shift.sv intdiv.sv test_iter64S.sv
|
||||
|
||||
# start and run simulation
|
||||
vsim -voptargs=+acc work.tb
|
||||
|
||||
|
||||
-- Set Wave Output Items
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreZoom {0 ps} {75 ns}
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
|
||||
-- Run the Simulation
|
||||
run 999586700ns
|
||||
quit
|
||||
182
pipelined/srt/stine/lod.sv
Executable file
182
pipelined/srt/stine/lod.sv
Executable file
@ -0,0 +1,182 @@
|
||||
///////////////////////////////////////////
|
||||
// lod.sv
|
||||
//
|
||||
// Written: James.Stine@okstate.edu 1 February 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Integer Divide instructions
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
module lod2 (P, V, B);
|
||||
|
||||
input logic [1:0] B;
|
||||
|
||||
output logic P;
|
||||
output logic V;
|
||||
|
||||
assign V = B[0] | B[1];
|
||||
assign P = B[0] & ~B[1];
|
||||
|
||||
endmodule // lo2
|
||||
|
||||
module lod_hier #(parameter WIDTH=8)
|
||||
(input logic [WIDTH-1:0] B,
|
||||
output logic [$clog2(WIDTH)-1:0] ZP,
|
||||
output logic ZV);
|
||||
|
||||
if (WIDTH == 128)
|
||||
lod128 lod128 (ZP, ZV, B);
|
||||
else if (WIDTH == 64)
|
||||
lod64 lod64 (ZP, ZV, B);
|
||||
else if (WIDTH == 32)
|
||||
lod32 lod32 (ZP, ZV, B);
|
||||
else if (WIDTH == 16)
|
||||
lod16 lod16 (ZP, ZV, B);
|
||||
else if (WIDTH == 8)
|
||||
lod8 lod8 (ZP, ZV, B);
|
||||
else if (WIDTH == 4)
|
||||
lod4 lod4 (ZP, ZV, B);
|
||||
|
||||
endmodule // lod_hier
|
||||
|
||||
module lod4 (ZP, ZV, B);
|
||||
|
||||
input logic [3:0] B;
|
||||
|
||||
logic ZPa;
|
||||
logic ZPb;
|
||||
logic ZVa;
|
||||
logic ZVb;
|
||||
|
||||
output logic [1:0] ZP;
|
||||
output logic ZV;
|
||||
|
||||
lod2 l1(ZPa, ZVa, B[1:0]);
|
||||
lod2 l2(ZPb, ZVb, B[3:2]);
|
||||
|
||||
assign ZP[0:0] = ZVb ? ZPb : ZPa;
|
||||
assign ZP[1] = ~ZVb;
|
||||
assign ZV = ZVa | ZVb;
|
||||
|
||||
endmodule // lod4
|
||||
|
||||
module lod8 (ZP, ZV, B);
|
||||
|
||||
input logic [7:0] B;
|
||||
|
||||
logic [1:0] ZPa;
|
||||
logic [1:0] ZPb;
|
||||
logic ZVa;
|
||||
logic ZVb;
|
||||
|
||||
output logic [2:0] ZP;
|
||||
output logic ZV;
|
||||
|
||||
lod4 l1(ZPa, ZVa, B[3:0]);
|
||||
lod4 l2(ZPb, ZVb, B[7:4]);
|
||||
|
||||
assign ZP[1:0] = ZVb ? ZPb : ZPa;
|
||||
assign ZP[2] = ~ZVb;
|
||||
assign ZV = ZVa | ZVb;
|
||||
|
||||
endmodule // lod8
|
||||
|
||||
module lod16 (ZP, ZV, B);
|
||||
|
||||
input logic [15:0] B;
|
||||
|
||||
logic [2:0] ZPa;
|
||||
logic [2:0] ZPb;
|
||||
logic ZVa;
|
||||
logic ZVb;
|
||||
|
||||
output logic [3:0] ZP;
|
||||
output logic ZV;
|
||||
|
||||
lod8 l1(ZPa, ZVa, B[7:0]);
|
||||
lod8 l2(ZPb, ZVb, B[15:8]);
|
||||
|
||||
assign ZP[2:0] = ZVb ? ZPb : ZPa;
|
||||
assign ZP[3] = ~ZVb;
|
||||
assign ZV = ZVa | ZVb;
|
||||
|
||||
endmodule // lod16
|
||||
|
||||
module lod32 (ZP, ZV, B);
|
||||
|
||||
input logic [31:0] B;
|
||||
|
||||
logic [3:0] ZPa;
|
||||
logic [3:0] ZPb;
|
||||
logic ZVa;
|
||||
logic ZVb;
|
||||
|
||||
output logic [4:0] ZP;
|
||||
output logic ZV;
|
||||
|
||||
lod16 l1(ZPa, ZVa, B[15:0]);
|
||||
lod16 l2(ZPb, ZVb, B[31:16]);
|
||||
|
||||
assign ZP[3:0] = ZVb ? ZPb : ZPa;
|
||||
assign ZP[4] = ~ZVb;
|
||||
assign ZV = ZVa | ZVb;
|
||||
|
||||
endmodule // lod32
|
||||
|
||||
module lod64 (ZP, ZV, B);
|
||||
|
||||
input logic [63:0] B;
|
||||
|
||||
logic [4:0] ZPa;
|
||||
logic [4:0] ZPb;
|
||||
logic ZVa;
|
||||
logic ZVb;
|
||||
|
||||
output logic [5:0] ZP;
|
||||
output logic ZV;
|
||||
|
||||
lod32 l1(ZPa, ZVa, B[31:0]);
|
||||
lod32 l2(ZPb, ZVb, B[63:32]);
|
||||
|
||||
assign ZP[4:0] = ZVb ? ZPb : ZPa;
|
||||
assign ZP[5] = ~ZVb;
|
||||
assign ZV = ZVa | ZVb;
|
||||
|
||||
endmodule // lod64
|
||||
|
||||
module lod128 (ZP, ZV, B);
|
||||
|
||||
input logic [127:0] B;
|
||||
|
||||
logic [5:0] ZPa;
|
||||
logic [5:0] ZPb;
|
||||
logic ZVa;
|
||||
logic ZVb;
|
||||
|
||||
output logic [6:0] ZP;
|
||||
output logic ZV;
|
||||
|
||||
lod64 l1(ZPa, ZVa, B[63:0]);
|
||||
lod64 l2(ZPb, ZVb, B[127:64]);
|
||||
|
||||
assign ZP[5:0] = ZVb ? ZPb : ZPa;
|
||||
assign ZP[6] = ~ZVb;
|
||||
assign ZV = ZVa | ZVb;
|
||||
|
||||
endmodule // lod128
|
||||
55
pipelined/srt/stine/lzd.do
Executable file
55
pipelined/srt/stine/lzd.do
Executable file
@ -0,0 +1,55 @@
|
||||
# Copyright 1991-2016 Mentor Graphics Corporation
|
||||
#
|
||||
# Modification by Oklahoma State University
|
||||
# Use with Testbench
|
||||
# James Stine, 2008
|
||||
# Go Cowboys!!!!!!
|
||||
#
|
||||
# All Rights Reserved.
|
||||
#
|
||||
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
|
||||
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
|
||||
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
|
||||
|
||||
# Use this run.do file to run this example.
|
||||
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
|
||||
# do run.do
|
||||
# or, to run from a shell, type the following at the shell prompt:
|
||||
# vsim -do run.do -c
|
||||
# (omit the "-c" to see the GUI while running from the shell)
|
||||
|
||||
onbreak {resume}
|
||||
|
||||
# create library
|
||||
if [file exists work] {
|
||||
vdel -all
|
||||
}
|
||||
vlib work
|
||||
|
||||
# compile source files
|
||||
vlog lod.sv lzd_tb.sv
|
||||
|
||||
# start and run simulation
|
||||
vsim -voptargs=+acc work.stimulus
|
||||
|
||||
view wave
|
||||
|
||||
-- display input and output signals as hexidecimal values
|
||||
# Diplays All Signals recursively
|
||||
add wave -hex -r /stimulus/*
|
||||
|
||||
-- Set Wave Output Items
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreZoom {0 ps} {75 ns}
|
||||
configure wave -namecolwidth 350
|
||||
configure wave -valuecolwidth 200
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
|
||||
-- Run the Simulation
|
||||
run 800ns
|
||||
quit
|
||||
182
pipelined/srt/stine/lzd.sv
Executable file
182
pipelined/srt/stine/lzd.sv
Executable file
@ -0,0 +1,182 @@
|
||||
///////////////////////////////////////////
|
||||
// lzd.sv
|
||||
//
|
||||
// Written: James.Stine@okstate.edu 1 February 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Integer Divide instructions
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
module lzd2 (P, V, B);
|
||||
|
||||
input logic [1:0] B;
|
||||
|
||||
output logic P;
|
||||
output logic V;
|
||||
|
||||
assign V = ~(B[0] & B[1]);
|
||||
assign P = B[1];
|
||||
|
||||
endmodule // lzd2
|
||||
|
||||
module lzd_hier #(parameter WIDTH=8)
|
||||
(input logic [WIDTH-1:0] B,
|
||||
output logic [$clog2(WIDTH)-1:0] ZP,
|
||||
output logic ZV);
|
||||
|
||||
if (WIDTH == 128)
|
||||
lzd128 lzd127 (ZP, ZV, B);
|
||||
else if (WIDTH == 64)
|
||||
lzd64 lzd64 (ZP, ZV, B);
|
||||
else if (WIDTH == 32)
|
||||
lzd32 lzd32 (ZP, ZV, B);
|
||||
else if (WIDTH == 16)
|
||||
lzd16 lzd16 (ZP, ZV, B);
|
||||
else if (WIDTH == 8)
|
||||
lzd8 lzd8 (ZP, ZV, B);
|
||||
else if (WIDTH == 4)
|
||||
lzd4 lzd4 (ZP, ZV, B);
|
||||
|
||||
endmodule // lzd_hier
|
||||
|
||||
module lzd4 (ZP, ZV, B);
|
||||
|
||||
input logic [3:0] B;
|
||||
|
||||
logic ZPa;
|
||||
logic ZPb;
|
||||
logic ZVa;
|
||||
logic ZVb;
|
||||
|
||||
output logic [1:0] ZP;
|
||||
output logic ZV;
|
||||
|
||||
lzd2 l1 (ZPa, ZVa, B[1:0]);
|
||||
lzd2 l2 (ZPb, ZVb, B[3:2]);
|
||||
|
||||
assign ZP[0:0] = ZVb ? ZPb : ZPa;
|
||||
assign ZP[1] = ~ZVb;
|
||||
assign ZV = ZVa | ZVb;
|
||||
|
||||
endmodule // lzd4
|
||||
|
||||
module lzd8 (ZP, ZV, B);
|
||||
|
||||
input logic [7:0] B;
|
||||
|
||||
logic [1:0] ZPa;
|
||||
logic [1:0] ZPb;
|
||||
logic ZVa;
|
||||
logic ZVb;
|
||||
|
||||
output logic [2:0] ZP;
|
||||
output logic ZV;
|
||||
|
||||
lzd4 l1 (ZPa, ZVa, B[3:0]);
|
||||
lzd4 l2 (ZPb, ZVb, B[7:4]);
|
||||
|
||||
assign ZP[1:0] = ZVb ? ZPb : ZPa;
|
||||
assign ZP[2] = ~ZVb;
|
||||
assign ZV = ZVa | ZVb;
|
||||
|
||||
endmodule // lzd8
|
||||
|
||||
module lzd16 (ZP, ZV, B);
|
||||
|
||||
input logic [15:0] B;
|
||||
|
||||
logic [2:0] ZPa;
|
||||
logic [2:0] ZPb;
|
||||
logic ZVa;
|
||||
logic ZVb;
|
||||
|
||||
output logic [3:0] ZP;
|
||||
output logic ZV;
|
||||
|
||||
lzd8 l1 (ZPa, ZVa, B[7:0]);
|
||||
lzd8 l2 (ZPb, ZVb, B[15:8]);
|
||||
|
||||
assign ZP[2:0] = ZVb ? ZPb : ZPa;
|
||||
assign ZP[3] = ~ZVb;
|
||||
assign ZV = ZVa | ZVb;
|
||||
|
||||
endmodule // lzd16
|
||||
|
||||
module lzd32 (ZP, ZV, B);
|
||||
|
||||
input logic [31:0] B;
|
||||
|
||||
logic [3:0] ZPa;
|
||||
logic [3:0] ZPb;
|
||||
logic ZVa;
|
||||
logic ZVb;
|
||||
|
||||
output logic [4:0] ZP;
|
||||
output logic ZV;
|
||||
|
||||
lzd16 l1 (ZPa, ZVa, B[15:0]);
|
||||
lzd16 l2 (ZPb, ZVb, B[31:16]);
|
||||
|
||||
assign ZP[3:0] = ZVb ? ZPb : ZPa;
|
||||
assign ZP[4] = ~ZVb;
|
||||
assign ZV = ZVa | ZVb;
|
||||
|
||||
endmodule // lzd32
|
||||
|
||||
module lzd64 (ZP, ZV, B);
|
||||
|
||||
input logic [63:0] B;
|
||||
|
||||
logic [4:0] ZPa;
|
||||
logic [4:0] ZPb;
|
||||
logic ZVa;
|
||||
logic ZVb;
|
||||
|
||||
output logic [5:0] ZP;
|
||||
output logic ZV;
|
||||
|
||||
lzd32 l1 (ZPa, ZVa, B[31:0]);
|
||||
lzd32 l2 (ZPb, ZVb, B[63:32]);
|
||||
|
||||
assign ZP[4:0] = ZVb ? ZPb : ZPa;
|
||||
assign ZP[5] = ~ZVb;
|
||||
assign ZV = ZVa | ZVb;
|
||||
|
||||
endmodule // lzd64
|
||||
|
||||
module lzd128 (ZP, ZV, B);
|
||||
|
||||
input logic [127:0] B;
|
||||
|
||||
logic [5:0] ZPa;
|
||||
logic [5:0] ZPb;
|
||||
logic ZVa;
|
||||
logic ZVb;
|
||||
|
||||
output logic [6:0] ZP;
|
||||
output logic ZV;
|
||||
|
||||
lzd64 l1 (ZPa, ZVa, B[64:0]);
|
||||
lzd64 l2 (ZPb, ZVb, B[127:63]);
|
||||
|
||||
assign ZP[5:0] = ZVb ? ZPb : ZPa;
|
||||
assign ZP[6] = ~ZVb;
|
||||
assign ZV = ZVa | ZVb;
|
||||
|
||||
endmodule // lzd128
|
||||
59
pipelined/srt/stine/lzd_tb.sv
Executable file
59
pipelined/srt/stine/lzd_tb.sv
Executable file
@ -0,0 +1,59 @@
|
||||
//
|
||||
// File name : tb
|
||||
// Title : test
|
||||
// project : HW3
|
||||
// Library : test
|
||||
// Purpose : definition of modules for testbench
|
||||
// notes :
|
||||
//
|
||||
// Copyright Oklahoma State University
|
||||
//
|
||||
|
||||
// Top level stimulus module
|
||||
|
||||
`timescale 1ns/1ps
|
||||
module stimulus;
|
||||
|
||||
logic [7:0] B;
|
||||
logic [2:0] ZP;
|
||||
logic ZV;
|
||||
|
||||
logic clk;
|
||||
|
||||
integer handle3;
|
||||
integer desc3;
|
||||
integer i;
|
||||
|
||||
// instatiate part to test
|
||||
lzd_hier #(8) dut (B, ZP, ZV);
|
||||
|
||||
initial
|
||||
begin
|
||||
clk = 1'b1;
|
||||
forever #5 clk = ~clk;
|
||||
end
|
||||
|
||||
initial
|
||||
begin
|
||||
handle3 = $fopen("lzd.out");
|
||||
desc3 = handle3;
|
||||
end
|
||||
|
||||
initial
|
||||
begin
|
||||
for (i=0; i < 256; i=i+1)
|
||||
begin
|
||||
// Put vectors before beginning of clk
|
||||
@(posedge clk)
|
||||
begin
|
||||
B = $random;
|
||||
end
|
||||
@(negedge clk)
|
||||
begin
|
||||
$fdisplay(desc3, "%b || %b %b", B, ZP, ZV);
|
||||
end
|
||||
end // for (i=0; i < 256; i=i+1)
|
||||
$finish;//
|
||||
end // initial begin
|
||||
|
||||
endmodule // stimulus
|
||||
51
pipelined/srt/stine/mux.sv
Executable file
51
pipelined/srt/stine/mux.sv
Executable file
@ -0,0 +1,51 @@
|
||||
module mux2 #(parameter WIDTH = 8)
|
||||
(input logic [WIDTH-1:0] d0, d1,
|
||||
input logic s,
|
||||
output logic [WIDTH-1:0] y);
|
||||
|
||||
assign y = s ? d1 : d0;
|
||||
|
||||
endmodule // mux2
|
||||
|
||||
module mux3 #(parameter WIDTH = 8)
|
||||
(input logic [WIDTH-1:0] d0, d1, d2,
|
||||
input logic [1:0] s,
|
||||
output logic [WIDTH-1:0] y);
|
||||
|
||||
assign y = s[1] ? d2 : (s[0] ? d1 : d0);
|
||||
|
||||
endmodule // mux3
|
||||
|
||||
module mux4 #(parameter WIDTH = 8)
|
||||
(input logic [WIDTH-1:0] d0, d1, d2, d3,
|
||||
input logic [1:0] s,
|
||||
output logic [WIDTH-1:0] y);
|
||||
|
||||
assign y = s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0);
|
||||
|
||||
endmodule // mux4
|
||||
|
||||
module mux21x32 (Z, A, B, Sel);
|
||||
|
||||
input logic [31:0] A;
|
||||
input logic [31:0] B;
|
||||
input logic Sel;
|
||||
|
||||
output logic [31:0] Z;
|
||||
|
||||
assign Z = Sel ? B : A;
|
||||
|
||||
endmodule // mux21x32
|
||||
|
||||
module mux21x64 (Z, A, B, Sel);
|
||||
|
||||
input logic [63:0] A;
|
||||
input logic [63:0] B;
|
||||
input logic Sel;
|
||||
|
||||
output logic [63:0] Z;
|
||||
|
||||
assign Z = Sel ? B : A;
|
||||
|
||||
endmodule // mux21x64
|
||||
|
||||
23
pipelined/srt/stine/otf4.in
Normal file
23
pipelined/srt/stine/otf4.in
Normal file
@ -0,0 +1,23 @@
|
||||
.i 4
|
||||
.o 6
|
||||
.ilb quot[3] quot[2] quot[1] quot[0]
|
||||
.ob Qin[1] Qin[0] QMin[1] QMin[0] CshiftQ CshiftQM
|
||||
|
||||
0000 001100
|
||||
0001 100110
|
||||
0010 111010
|
||||
0011 ------
|
||||
0100 010001
|
||||
0101 ------
|
||||
0110 ------
|
||||
0111 ------
|
||||
1000 100101
|
||||
1001 ------
|
||||
1010 ------
|
||||
1011 ------
|
||||
1100 ------
|
||||
1101 ------
|
||||
1110 ------
|
||||
1111 ------
|
||||
|
||||
.e
|
||||
BIN
pipelined/srt/stine/qslc_r4a2
Executable file
BIN
pipelined/srt/stine/qslc_r4a2
Executable file
Binary file not shown.
198
pipelined/srt/stine/qslc_r4a2.c
Normal file
198
pipelined/srt/stine/qslc_r4a2.c
Normal file
@ -0,0 +1,198 @@
|
||||
/*
|
||||
Program: qslc_r4a2.c
|
||||
Description: Prints out Quotient Selection Table (assumes CPA is utilized to reduce memory)
|
||||
User: James E. Stine
|
||||
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
#include <math.h>
|
||||
|
||||
#define DIVISOR_SIZE 3
|
||||
#define CARRY_SIZE 7
|
||||
#define SUM_SIZE 7
|
||||
#define TOT_SIZE 7
|
||||
|
||||
void disp_binary(double, int, int);
|
||||
|
||||
struct bits {
|
||||
unsigned int divisor : DIVISOR_SIZE;
|
||||
int tot : TOT_SIZE;
|
||||
} pla;
|
||||
|
||||
/*
|
||||
|
||||
Function: disp_binary
|
||||
Description: This function displays a Double-Precision number into
|
||||
four 16 bit integers using the global union variable
|
||||
dp_number
|
||||
Argument List: double x The value to be converted
|
||||
int bits_to_left Number of bits left of radix point
|
||||
int bits_to_right Number of bits right of radix point
|
||||
Return value: none
|
||||
|
||||
*/
|
||||
void disp_binary(double x, int bits_to_left, int bits_to_right) {
|
||||
int i;
|
||||
double diff;
|
||||
|
||||
if (fabs(x) < pow(2.0, ((double) -bits_to_right)) ) {
|
||||
for (i = -bits_to_left + 1; i <= bits_to_right; i++) {
|
||||
printf("0");
|
||||
}
|
||||
if (i == bits_to_right+1)
|
||||
;
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
if (x < 0.0)
|
||||
x = pow(2.0, ((double) bits_to_left)) + x;
|
||||
|
||||
for (i = -bits_to_left + 1; i <= bits_to_right; i++) {
|
||||
diff = pow(2.0, ((double) -i) );
|
||||
if (x < diff)
|
||||
printf("0");
|
||||
else {
|
||||
printf("1");
|
||||
x -= diff;
|
||||
}
|
||||
if (i == 0)
|
||||
;
|
||||
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
int main() {
|
||||
int m;
|
||||
int n;
|
||||
int o;
|
||||
pla.divisor = 0;
|
||||
pla.tot = 0;
|
||||
printf("\tcase({D[5:3],Wmsbs})\n");
|
||||
for (o=0; o < pow(2.0, DIVISOR_SIZE); o++) {
|
||||
for (m=0; m < pow(2.0, TOT_SIZE); m++) {
|
||||
printf("\t\t10'b");
|
||||
disp_binary((double) pla.divisor, DIVISOR_SIZE, 0);
|
||||
printf("_");
|
||||
disp_binary((double) pla.tot, TOT_SIZE, 0);
|
||||
printf(": q = 4'b");
|
||||
|
||||
/*
|
||||
4 bits for Radix 4 (a=2)
|
||||
1000 = +2
|
||||
0100 = +1
|
||||
0000 = 0
|
||||
0010 = -1
|
||||
0001 = -2
|
||||
*/
|
||||
switch (pla.divisor) {
|
||||
case 0:
|
||||
if ((pla.tot) >= 12)
|
||||
printf("1000");
|
||||
else if ((pla.tot) >= 4)
|
||||
printf("0100");
|
||||
else if ((pla.tot) >= -4)
|
||||
printf("0000");
|
||||
else if ((pla.tot) >= -13)
|
||||
printf("0010");
|
||||
else
|
||||
printf("0001");
|
||||
break;
|
||||
case 1:
|
||||
if ((pla.tot) >= 14)
|
||||
printf("1000");
|
||||
else if ((pla.tot) >= 4)
|
||||
printf("0100");
|
||||
else if ((pla.tot) >= -6)
|
||||
printf("0000");
|
||||
else if ((pla.tot) >= -15)
|
||||
printf("0010");
|
||||
else
|
||||
printf("0001");
|
||||
break;
|
||||
case 2:
|
||||
if ((pla.tot) >= 15)
|
||||
printf("1000");
|
||||
else if ((pla.tot) >= 4)
|
||||
printf("0100");
|
||||
else if ((pla.tot) >= -6)
|
||||
printf("0000");
|
||||
else if ((pla.tot) >= -16)
|
||||
printf("0010");
|
||||
else
|
||||
printf("0001");
|
||||
break;
|
||||
case 3:
|
||||
if ((pla.tot) >= 16)
|
||||
printf("1000");
|
||||
else if ((pla.tot) >= 4)
|
||||
printf("0100");
|
||||
else if ((pla.tot) >= -6)
|
||||
printf("0000");
|
||||
else if ((pla.tot) >= -18)
|
||||
printf("0010");
|
||||
else
|
||||
printf("0001");
|
||||
break;
|
||||
case 4:
|
||||
if ((pla.tot) >= 18)
|
||||
printf("1000");
|
||||
else if ((pla.tot) >= 6)
|
||||
printf("0100");
|
||||
else if ((pla.tot) >= -8)
|
||||
printf("0000");
|
||||
else if ((pla.tot) >= -20)
|
||||
printf("0010");
|
||||
else
|
||||
printf("0001");
|
||||
break;
|
||||
case 5:
|
||||
if ((pla.tot) >= 20)
|
||||
printf("1000");
|
||||
else if ((pla.tot) >= 6)
|
||||
printf("0100");
|
||||
else if ((pla.tot) >= -8)
|
||||
printf("0000");
|
||||
else if ((pla.tot) >= -20)
|
||||
printf("0010");
|
||||
else
|
||||
printf("0001");
|
||||
break;
|
||||
case 6:
|
||||
if ((pla.tot) >= 20)
|
||||
printf("1000");
|
||||
else if ((pla.tot) >= 8)
|
||||
printf("0100");
|
||||
else if ((pla.tot) >= -8)
|
||||
printf("0000");
|
||||
else if ((pla.tot) >= -22)
|
||||
printf("0010");
|
||||
else
|
||||
printf("0001");
|
||||
break;
|
||||
case 7:
|
||||
if ((pla.tot) >= 24)
|
||||
printf("1000");
|
||||
else if ((pla.tot) >= 8)
|
||||
printf("0100");
|
||||
else if ((pla.tot) >= -8)
|
||||
printf("0000");
|
||||
else if ((pla.tot) >= -24)
|
||||
printf("0010");
|
||||
else
|
||||
printf("0001");
|
||||
break;
|
||||
default: printf ("XXX");
|
||||
|
||||
}
|
||||
|
||||
printf(";\n");
|
||||
(pla.tot)++;
|
||||
}
|
||||
(pla.divisor)++;
|
||||
}
|
||||
printf("\tendcase\n");
|
||||
|
||||
}
|
||||
8
pipelined/srt/stine/run.sh
Executable file
8
pipelined/srt/stine/run.sh
Executable file
@ -0,0 +1,8 @@
|
||||
#!/bin/sh
|
||||
vsim -do iter32S.do -c
|
||||
vsim -do iter32.do -c
|
||||
vsim -do iter64.do -c
|
||||
vsim -do iter64S.do -c
|
||||
vsim -do iter128.do -c
|
||||
vsim -do iter128S.do -c
|
||||
|
||||
73
pipelined/srt/stine/shift.sv
Executable file
73
pipelined/srt/stine/shift.sv
Executable file
@ -0,0 +1,73 @@
|
||||
///////////////////////////////////////////
|
||||
// shifters.sv
|
||||
//
|
||||
// Written: James.Stine@okstate.edu 1 February 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Integer Divide instructions
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
module shift_right #(parameter WIDTH=8)
|
||||
(input logic [WIDTH-1:0] A,
|
||||
input logic [$clog2(WIDTH)-1:0] Shift,
|
||||
output logic [WIDTH-1:0] Z);
|
||||
|
||||
logic [WIDTH-1:0] stage [$clog2(WIDTH):0];
|
||||
logic sign;
|
||||
genvar i;
|
||||
|
||||
assign stage[0] = A;
|
||||
generate
|
||||
for (i=0;i<$clog2(WIDTH);i=i+1)
|
||||
begin : genbit
|
||||
mux2 #(WIDTH) mux_inst (stage[i],
|
||||
{{(WIDTH/(2**(i+1))){1'b0}}, stage[i][WIDTH-1:WIDTH/(2**(i+1))]},
|
||||
Shift[$clog2(WIDTH)-i-1],
|
||||
stage[i+1]);
|
||||
end
|
||||
endgenerate
|
||||
assign Z = stage[$clog2(WIDTH)];
|
||||
|
||||
endmodule // shift_right
|
||||
|
||||
module shift_left #(parameter WIDTH=8)
|
||||
(input logic [WIDTH-1:0] A,
|
||||
input logic [$clog2(WIDTH)-1:0] Shift,
|
||||
output logic [WIDTH-1:0] Z);
|
||||
|
||||
logic [WIDTH-1:0] stage [$clog2(WIDTH):0];
|
||||
genvar i;
|
||||
|
||||
assign stage[0] = A;
|
||||
generate
|
||||
for (i=0;i<$clog2(WIDTH);i=i+1)
|
||||
begin : genbit
|
||||
mux2 #(WIDTH) mux_inst (stage[i],
|
||||
{stage[i][WIDTH-1-WIDTH/(2**(i+1)):0], {(WIDTH/(2**(i+1))){1'b0}}},
|
||||
Shift[$clog2(WIDTH)-i-1],
|
||||
stage[i+1]);
|
||||
end
|
||||
endgenerate
|
||||
assign Z = stage[$clog2(WIDTH)];
|
||||
|
||||
endmodule // shift_left
|
||||
|
||||
|
||||
|
||||
|
||||
55
pipelined/srt/stine/shift_left.do
Executable file
55
pipelined/srt/stine/shift_left.do
Executable file
@ -0,0 +1,55 @@
|
||||
# Copyright 1991-2016 Mentor Graphics Corporation
|
||||
#
|
||||
# Modification by Oklahoma State University
|
||||
# Use with Testbench
|
||||
# James Stine, 2008
|
||||
# Go Cowboys!!!!!!
|
||||
#
|
||||
# All Rights Reserved.
|
||||
#
|
||||
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
|
||||
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
|
||||
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
|
||||
|
||||
# Use this run.do file to run this example.
|
||||
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
|
||||
# do run.do
|
||||
# or, to run from a shell, type the following at the shell prompt:
|
||||
# vsim -do run.do -c
|
||||
# (omit the "-c" to see the GUI while running from the shell)
|
||||
|
||||
onbreak {resume}
|
||||
|
||||
# create library
|
||||
if [file exists work] {
|
||||
vdel -all
|
||||
}
|
||||
vlib work
|
||||
|
||||
# compile source files
|
||||
vlog mux.sv shift.sv shift_left_tb.sv
|
||||
|
||||
# start and run simulation
|
||||
vsim -voptargs=+acc work.stimulus
|
||||
|
||||
view wave
|
||||
|
||||
-- display input and output signals as hexidecimal values
|
||||
# Diplays All Signals recursively
|
||||
add wave -hex -r /stimulus/*
|
||||
|
||||
-- Set Wave Output Items
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreZoom {0 ps} {75 ns}
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
|
||||
-- Run the Simulation
|
||||
run 800ns
|
||||
quit
|
||||
71
pipelined/srt/stine/shift_left_tb.sv
Executable file
71
pipelined/srt/stine/shift_left_tb.sv
Executable file
@ -0,0 +1,71 @@
|
||||
//
|
||||
// File name : tb
|
||||
// Title : test
|
||||
// project : HW3
|
||||
// Library : test
|
||||
// Purpose : definition of modules for testbench
|
||||
// notes :
|
||||
//
|
||||
// Copyright Oklahoma State University
|
||||
//
|
||||
|
||||
// Top level stimulus module
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
`define XLEN 32
|
||||
module stimulus;
|
||||
|
||||
logic [`XLEN-1:0] A;
|
||||
logic [$clog2(`XLEN)-1:0] Shift;
|
||||
logic [`XLEN-1:0] Z;
|
||||
logic [`XLEN-1:0] Z_corr;
|
||||
|
||||
//logic [63:0] A;
|
||||
//logic [5:0] Shift;
|
||||
//logic [63:0] Z;
|
||||
//logic [63:0] Z_corr;
|
||||
//logic [63:0] Z_orig;
|
||||
|
||||
|
||||
logic clk;
|
||||
|
||||
integer handle3;
|
||||
integer desc3;
|
||||
integer i;
|
||||
|
||||
// instatiate part to test
|
||||
shift_left dut1 (A, Shift, Z);
|
||||
assign Z_corr = (A << Shift);
|
||||
|
||||
initial
|
||||
begin
|
||||
clk = 1'b1;
|
||||
forever #5 clk = ~clk;
|
||||
end
|
||||
|
||||
initial
|
||||
begin
|
||||
handle3 = $fopen("shift_left.out");
|
||||
desc3 = handle3;
|
||||
end
|
||||
|
||||
initial
|
||||
begin
|
||||
for (i=0; i < 256; i=i+1)
|
||||
begin
|
||||
// Put vectors before beginning of clk
|
||||
@(posedge clk)
|
||||
begin
|
||||
A = $random;
|
||||
Shift = $random;
|
||||
end
|
||||
@(negedge clk)
|
||||
begin
|
||||
$fdisplay(desc3, "%h %h || %h %h | %b", A, Shift, Z, Z_corr, (Z == Z_corr));
|
||||
end
|
||||
end // for (i=0; i < 256; i=i+1)
|
||||
$finish;//
|
||||
end // initial begin
|
||||
|
||||
endmodule // stimulus
|
||||
55
pipelined/srt/stine/shift_right.do
Executable file
55
pipelined/srt/stine/shift_right.do
Executable file
@ -0,0 +1,55 @@
|
||||
# Copyright 1991-2016 Mentor Graphics Corporation
|
||||
#
|
||||
# Modification by Oklahoma State University
|
||||
# Use with Testbench
|
||||
# James Stine, 2008
|
||||
# Go Cowboys!!!!!!
|
||||
#
|
||||
# All Rights Reserved.
|
||||
#
|
||||
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
|
||||
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
|
||||
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
|
||||
|
||||
# Use this run.do file to run this example.
|
||||
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
|
||||
# do run.do
|
||||
# or, to run from a shell, type the following at the shell prompt:
|
||||
# vsim -do run.do -c
|
||||
# (omit the "-c" to see the GUI while running from the shell)
|
||||
|
||||
onbreak {resume}
|
||||
|
||||
# create library
|
||||
if [file exists work] {
|
||||
vdel -all
|
||||
}
|
||||
vlib work
|
||||
|
||||
# compile source files
|
||||
vlog mux.sv shift.sv shift_right_tb.sv
|
||||
|
||||
# start and run simulation
|
||||
vsim -voptargs=+acc work.stimulus
|
||||
|
||||
view wave
|
||||
|
||||
-- display input and output signals as hexidecimal values
|
||||
# Diplays All Signals recursively
|
||||
add wave -hex -r /stimulus/*
|
||||
|
||||
-- Set Wave Output Items
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreZoom {0 ps} {75 ns}
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
|
||||
-- Run the Simulation
|
||||
run 800ns
|
||||
quit
|
||||
64
pipelined/srt/stine/shift_right_tb.sv
Executable file
64
pipelined/srt/stine/shift_right_tb.sv
Executable file
@ -0,0 +1,64 @@
|
||||
//
|
||||
// File name : tb
|
||||
// Title : test
|
||||
// project : HW3
|
||||
// Library : test
|
||||
// Purpose : definition of modules for testbench
|
||||
// notes :
|
||||
//
|
||||
// Copyright Oklahoma State University
|
||||
//
|
||||
|
||||
// Top level stimulus module
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
`define XLEN 32
|
||||
module stimulus;
|
||||
|
||||
logic [`XLEN-1:0] A;
|
||||
logic [$clog2(`XLEN)-1:0] Shift;
|
||||
logic [`XLEN-1:0] Z;
|
||||
logic [`XLEN-1:0] Z_corr;
|
||||
|
||||
logic clk;
|
||||
|
||||
integer handle3;
|
||||
integer desc3;
|
||||
integer i;
|
||||
|
||||
// instatiate part to test
|
||||
shift_right dut1 (A, Shift, Z);
|
||||
assign Z_corr = (A >> Shift);
|
||||
|
||||
initial
|
||||
begin
|
||||
clk = 1'b1;
|
||||
forever #5 clk = ~clk;
|
||||
end
|
||||
|
||||
initial
|
||||
begin
|
||||
handle3 = $fopen("shift_right.out");
|
||||
desc3 = handle3;
|
||||
#250 $finish;
|
||||
end
|
||||
|
||||
initial
|
||||
begin
|
||||
for (i=0; i < 128; i=i+1)
|
||||
begin
|
||||
// Put vectors before beginning of clk
|
||||
@(posedge clk)
|
||||
begin
|
||||
A = $random;
|
||||
Shift = $random;
|
||||
end
|
||||
@(negedge clk)
|
||||
begin
|
||||
$fdisplay(desc3, "%h %h || %h %h | %b", A, Shift, Z, Z_corr, (Z == Z_corr));
|
||||
end
|
||||
end // @(negedge clk)
|
||||
end // for (j=0; j < 32; j=j+1)
|
||||
|
||||
endmodule // stimulus
|
||||
18
pipelined/srt/stine/shifter.sv
Executable file
18
pipelined/srt/stine/shifter.sv
Executable file
@ -0,0 +1,18 @@
|
||||
module shifter_right(input logic signed [63:0] a,
|
||||
input logic [ 5:0] shamt,
|
||||
output logic signed [63:0] y);
|
||||
|
||||
|
||||
y = a >> shamt;
|
||||
|
||||
endmodule // shifter_right
|
||||
|
||||
module shifter_left(input logic signed [63:0] a,
|
||||
input logic [ 5:0] shamt,
|
||||
output logic signed [63:0] y);
|
||||
|
||||
|
||||
y = a << shamt;
|
||||
|
||||
endmodule // shifter_right
|
||||
|
||||
79
pipelined/srt/stine/test_iter128.sv
Normal file
79
pipelined/srt/stine/test_iter128.sv
Normal file
@ -0,0 +1,79 @@
|
||||
`include "idiv-config.vh"
|
||||
|
||||
module tb;
|
||||
|
||||
logic [127:0] N, D;
|
||||
logic clk;
|
||||
logic reset;
|
||||
logic start;
|
||||
logic S;
|
||||
|
||||
logic [127:0] Q;
|
||||
logic [127:0] rem0;
|
||||
logic div0;
|
||||
logic done;
|
||||
|
||||
integer handle3;
|
||||
integer desc3;
|
||||
integer i;
|
||||
|
||||
logic [127:0] Ncomp;
|
||||
logic [127:0] Dcomp;
|
||||
logic [127:0] Qcomp;
|
||||
logic [127:0] Rcomp;
|
||||
|
||||
logic [31:0] vectornum;
|
||||
logic [31:0] errors;
|
||||
|
||||
intdiv #(128) dut (Q, done, rem0, div0, N, D, clk, reset, start, S);
|
||||
|
||||
initial
|
||||
begin
|
||||
clk = 1'b0;
|
||||
forever #5 clk = ~clk;
|
||||
end
|
||||
|
||||
initial
|
||||
begin
|
||||
vectornum = 0;
|
||||
errors = 0;
|
||||
handle3 = $fopen("iter128_unsigned.out");
|
||||
end
|
||||
|
||||
always @(posedge clk, posedge reset)
|
||||
begin
|
||||
desc3 = handle3;
|
||||
#0 start = 1'b0;
|
||||
#0 S = 1'b0;
|
||||
#0 reset = 1'b1;
|
||||
#30 reset = 1'b0;
|
||||
#30 N = 128'h0;
|
||||
#0 D = 128'h0;
|
||||
for (i=0; i<`IDIV_TESTS; i=i+1)
|
||||
begin
|
||||
N = {$urandom(), $urandom(), $urandom(), $urandom()};
|
||||
D = {$urandom(), $urandom(), $urandom(), $urandom()};
|
||||
start <= 1'b1;
|
||||
// Wait 2 cycles (to be sure)
|
||||
repeat (2)
|
||||
@(posedge clk);
|
||||
start <= 1'b0;
|
||||
repeat (41)
|
||||
@(posedge clk);
|
||||
Ncomp = N;
|
||||
Dcomp = D;
|
||||
Qcomp = Ncomp/Dcomp;
|
||||
Rcomp = Ncomp%Dcomp;
|
||||
vectornum = vectornum + 1;
|
||||
if ((Q !== Qcomp)) begin
|
||||
errors = errors + 1;
|
||||
end
|
||||
$fdisplay(desc3, "%h %h %h %h || %h %h || %b %b",
|
||||
N, D, Q, rem0, Qcomp, Rcomp,
|
||||
(Q==Qcomp), (rem0==Rcomp));
|
||||
end // for (i=0; i<2, i=i+1)
|
||||
$display("%d tests completed, %d errors", vectornum, errors);
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule // tb
|
||||
90
pipelined/srt/stine/test_iter128S.sv
Normal file
90
pipelined/srt/stine/test_iter128S.sv
Normal file
@ -0,0 +1,90 @@
|
||||
`include "idiv-config.vh"
|
||||
|
||||
module tb;
|
||||
|
||||
logic [127:0] N, D;
|
||||
logic clk;
|
||||
logic reset;
|
||||
logic start;
|
||||
logic S;
|
||||
|
||||
logic [127:0] Q;
|
||||
logic [127:0] rem0;
|
||||
logic div0;
|
||||
logic done;
|
||||
|
||||
integer handle3;
|
||||
integer desc3;
|
||||
integer i;
|
||||
|
||||
logic [31:0] rnd1;
|
||||
logic [31:0] rnd2;
|
||||
logic [127:0] Ncomp;
|
||||
logic [127:0] Dcomp;
|
||||
logic [127:0] Qcomp;
|
||||
logic [127:0] Rcomp;
|
||||
|
||||
logic [31:0] vectornum;
|
||||
logic [31:0] errors;
|
||||
|
||||
intdiv #(128) dut (Q, done, rem0, div0, N, D, clk, reset, start, S);
|
||||
|
||||
initial
|
||||
begin
|
||||
clk = 1'b0;
|
||||
forever #5 clk = ~clk;
|
||||
end
|
||||
|
||||
initial
|
||||
begin
|
||||
vectornum = 0;
|
||||
errors = 0;
|
||||
handle3 = $fopen("iter128_signed.out");
|
||||
end
|
||||
|
||||
/*
|
||||
// VCD generation for power estimation
|
||||
initial
|
||||
begin
|
||||
$dumpfile("iter128_signed.vcd");
|
||||
$dumpvars (0,tb.dut);
|
||||
end
|
||||
*/
|
||||
|
||||
always @(posedge clk, posedge reset)
|
||||
begin
|
||||
desc3 = handle3;
|
||||
#0 start = 1'b0;
|
||||
#0 S = 1'b1;
|
||||
#0 reset = 1'b1;
|
||||
#30 reset = 1'b0;
|
||||
#30 N = 128'h0;
|
||||
#0 D = 128'h0;
|
||||
for (i=0; i<`IDIV_TESTS; i=i+1)
|
||||
begin
|
||||
N = {$urandom(), $urandom(), $urandom(), $urandom()};
|
||||
D = {$urandom(), $urandom(), $urandom(), $urandom()};
|
||||
start <= 1'b1;
|
||||
// Wait 2 cycles (to be sure)
|
||||
repeat (1)
|
||||
@(posedge clk);
|
||||
start <= 1'b0;
|
||||
repeat (65)
|
||||
@(posedge clk);
|
||||
Ncomp = N;
|
||||
Dcomp = D;
|
||||
Qcomp = $signed(Ncomp)/$signed(Dcomp);
|
||||
Rcomp = $signed(Ncomp)%$signed(Dcomp);
|
||||
vectornum = vectornum + 1;
|
||||
if ((Q !== Qcomp)) begin
|
||||
errors = errors + 1;
|
||||
end
|
||||
$fdisplay(desc3, "%h %h %h %h || %h %h || %b %b",
|
||||
N, D, Q, rem0, Qcomp, Rcomp,
|
||||
(Q==Qcomp), (rem0==Rcomp));
|
||||
end
|
||||
$display("%d tests completed, %d errors", vectornum, errors);
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule // tb
|
||||
85
pipelined/srt/stine/test_iter32.sv
Executable file
85
pipelined/srt/stine/test_iter32.sv
Executable file
@ -0,0 +1,85 @@
|
||||
`include "idiv-config.vh"
|
||||
|
||||
module tb;
|
||||
|
||||
logic [31:0] N, D;
|
||||
logic clk;
|
||||
logic reset;
|
||||
logic start;
|
||||
logic S;
|
||||
|
||||
logic [31:0] Q;
|
||||
logic [31:0] rem0;
|
||||
logic div0;
|
||||
logic done;
|
||||
|
||||
integer handle3;
|
||||
integer desc3;
|
||||
integer i;
|
||||
|
||||
logic [31:0] Ncomp;
|
||||
logic [31:0] Dcomp;
|
||||
logic [31:0] Qcomp;
|
||||
logic [31:0] Rcomp;
|
||||
|
||||
logic [31:0] vectornum;
|
||||
logic [31:0] errors;
|
||||
|
||||
intdiv #(32) dut (Q, done, rem0, div0, N, D, clk, reset, start, S);
|
||||
|
||||
initial
|
||||
begin
|
||||
clk = 1'b0;
|
||||
forever #5 clk = ~clk;
|
||||
end
|
||||
|
||||
initial
|
||||
begin
|
||||
vectornum = 0;
|
||||
errors = 0;
|
||||
handle3 = $fopen("iter32_unsigned.out");
|
||||
end
|
||||
|
||||
always @(posedge clk, posedge reset)
|
||||
begin
|
||||
desc3 = handle3;
|
||||
#0 start = 1'b0;
|
||||
#0 S = 1'b0;
|
||||
#0 reset = 1'b1;
|
||||
#30 reset = 1'b0;
|
||||
#30 N = 32'h0;
|
||||
#0 D = 32'h0;
|
||||
for (i=0; i<`IDIV_TESTS; i=i+1)
|
||||
begin
|
||||
N = $urandom;
|
||||
D = $urandom;
|
||||
start <= 1'b1;
|
||||
// Wait 2 cycles (to be sure)
|
||||
repeat (2)
|
||||
@(posedge clk);
|
||||
start <= 1'b0;
|
||||
repeat (41)
|
||||
@(posedge clk);
|
||||
Ncomp = N;
|
||||
Dcomp = D;
|
||||
Qcomp = Ncomp/Dcomp;
|
||||
Rcomp = Ncomp%Dcomp;
|
||||
if ((Q !== Qcomp)) begin
|
||||
errors = errors + 1;
|
||||
end
|
||||
vectornum = vectornum + 1;
|
||||
$fdisplay(desc3, "%h %h %h %h || %h %h || %b %b",
|
||||
N, D, Q, rem0, Qcomp, Rcomp,
|
||||
(Q==Qcomp), (rem0==Rcomp));
|
||||
end // for (i=0; i<2, i=i+1)
|
||||
$display("%d tests completed, %d errors", vectornum, errors);
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule // tb
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
79
pipelined/srt/stine/test_iter32S.sv
Normal file
79
pipelined/srt/stine/test_iter32S.sv
Normal file
@ -0,0 +1,79 @@
|
||||
`include "idiv-config.vh"
|
||||
|
||||
module tb;
|
||||
|
||||
logic [31:0] N, D;
|
||||
logic clk;
|
||||
logic reset;
|
||||
logic start;
|
||||
logic S;
|
||||
|
||||
logic [31:0] Q;
|
||||
logic [31:0] rem0;
|
||||
logic div0;
|
||||
logic done;
|
||||
|
||||
integer handle3;
|
||||
integer desc3;
|
||||
integer i;
|
||||
|
||||
logic [31:0] Ncomp;
|
||||
logic [31:0] Dcomp;
|
||||
logic [31:0] Qcomp;
|
||||
logic [31:0] Rcomp;
|
||||
|
||||
logic [31:0] vectornum;
|
||||
logic [31:0] errors;
|
||||
|
||||
intdiv #(32) dut (Q, done, rem0, div0, N, D, clk, reset, start, S);
|
||||
|
||||
initial
|
||||
begin
|
||||
clk = 1'b0;
|
||||
forever #5 clk = ~clk;
|
||||
end
|
||||
|
||||
initial
|
||||
begin
|
||||
vectornum = 0;
|
||||
errors = 0;
|
||||
handle3 = $fopen("iter32_signed.out");
|
||||
end
|
||||
|
||||
always @(posedge clk, posedge reset)
|
||||
begin
|
||||
desc3 = handle3;
|
||||
#0 start = 1'b0;
|
||||
#0 S = 1'b1;
|
||||
#0 reset = 1'b1;
|
||||
#30 reset = 1'b0;
|
||||
#30 N = 32'h0;
|
||||
#0 D = 32'h0;
|
||||
for (i=0; i<`IDIV_TESTS; i=i+1)
|
||||
begin
|
||||
N = $urandom;
|
||||
D = $urandom;
|
||||
start <= 1'b1;
|
||||
// Wait 2 cycles (to be sure)
|
||||
repeat (2)
|
||||
@(posedge clk);
|
||||
start <= 1'b0;
|
||||
repeat (41)
|
||||
@(posedge clk);
|
||||
Ncomp = N;
|
||||
Dcomp = D;
|
||||
Qcomp = $signed(Ncomp)/$signed(Dcomp);
|
||||
Rcomp = $signed(Ncomp)%$signed(Dcomp);
|
||||
if ((Q !== Qcomp)) begin
|
||||
errors = errors + 1;
|
||||
end
|
||||
vectornum = vectornum + 1;
|
||||
$fdisplay(desc3, "%h %h %h %h || %h %h || %b %b",
|
||||
N, D, Q, rem0, Qcomp, Rcomp,
|
||||
(Q==Qcomp), (rem0==Rcomp));
|
||||
end // for (i=0; i<2, i=i+1)
|
||||
$display("%d tests completed, %d errors", vectornum, errors);
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule // tb
|
||||
79
pipelined/srt/stine/test_iter64.sv
Executable file
79
pipelined/srt/stine/test_iter64.sv
Executable file
@ -0,0 +1,79 @@
|
||||
`include "idiv-config.vh"
|
||||
|
||||
module tb;
|
||||
|
||||
logic [63:0] N, D;
|
||||
logic clk;
|
||||
logic reset;
|
||||
logic start;
|
||||
logic S;
|
||||
|
||||
logic [63:0] Q;
|
||||
logic [63:0] rem0;
|
||||
logic div0;
|
||||
logic done;
|
||||
|
||||
integer handle3;
|
||||
integer desc3;
|
||||
integer i;
|
||||
|
||||
logic [63:0] Ncomp;
|
||||
logic [63:0] Dcomp;
|
||||
logic [63:0] Qcomp;
|
||||
logic [63:0] Rcomp;
|
||||
|
||||
logic [31:0] vectornum;
|
||||
logic [31:0] errors;
|
||||
|
||||
intdiv #(64) dut (Q, done, rem0, div0, N, D, clk, reset, start, S);
|
||||
|
||||
initial
|
||||
begin
|
||||
clk = 1'b0;
|
||||
forever #5 clk = ~clk;
|
||||
end
|
||||
|
||||
initial
|
||||
begin
|
||||
vectornum = 0;
|
||||
errors = 0;
|
||||
handle3 = $fopen("iter64_unsigned.out");
|
||||
end
|
||||
|
||||
always @(posedge clk, posedge reset)
|
||||
begin
|
||||
desc3 = handle3;
|
||||
#0 start = 1'b0;
|
||||
#0 S = 1'b0;
|
||||
#0 reset = 1'b1;
|
||||
#30 reset = 1'b0;
|
||||
#30 N = 64'h0;
|
||||
#0 D = 64'h0;
|
||||
for (i=0; i<`IDIV_TESTS; i=i+1)
|
||||
begin
|
||||
N = {$urandom(), $urandom()};
|
||||
D = {$urandom(), $urandom()};
|
||||
start <= 1'b1;
|
||||
// Wait 2 cycles (to be sure)
|
||||
repeat (2)
|
||||
@(posedge clk);
|
||||
start <= 1'b0;
|
||||
repeat (41)
|
||||
@(posedge clk);
|
||||
Ncomp = N;
|
||||
Dcomp = D;
|
||||
Qcomp = Ncomp/Dcomp;
|
||||
Rcomp = Ncomp%Dcomp;
|
||||
vectornum = vectornum + 1;
|
||||
if ((Q !== Qcomp)) begin
|
||||
errors = errors + 1;
|
||||
end
|
||||
$fdisplay(desc3, "%h %h %h %h || %h %h || %b %b",
|
||||
N, D, Q, rem0, Qcomp, Rcomp,
|
||||
(Q==Qcomp), (rem0==Rcomp));
|
||||
end // for (i=0; i<2, i=i+1)
|
||||
$display("%d tests completed, %d errors", vectornum, errors);
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule // tb
|
||||
79
pipelined/srt/stine/test_iter64S.sv
Normal file
79
pipelined/srt/stine/test_iter64S.sv
Normal file
@ -0,0 +1,79 @@
|
||||
`include "idiv-config.vh"
|
||||
|
||||
module tb;
|
||||
|
||||
logic [63:0] N, D;
|
||||
logic clk;
|
||||
logic reset;
|
||||
logic start;
|
||||
logic S;
|
||||
|
||||
logic [63:0] Q;
|
||||
logic [63:0] rem0;
|
||||
logic div0;
|
||||
logic done;
|
||||
|
||||
integer handle3;
|
||||
integer desc3;
|
||||
integer i;
|
||||
|
||||
logic [63:0] Ncomp;
|
||||
logic [63:0] Dcomp;
|
||||
logic [63:0] Qcomp;
|
||||
logic [63:0] Rcomp;
|
||||
|
||||
logic [31:0] vectornum;
|
||||
logic [31:0] errors;
|
||||
|
||||
intdiv #(64) dut (Q, done, rem0, div0, N, D, clk, reset, start, S);
|
||||
|
||||
initial
|
||||
begin
|
||||
clk = 1'b0;
|
||||
forever #5 clk = ~clk;
|
||||
end
|
||||
|
||||
initial
|
||||
begin
|
||||
vectornum = 0;
|
||||
errors = 0;
|
||||
handle3 = $fopen("iter64_signed.out");
|
||||
end
|
||||
|
||||
always @(posedge clk, posedge reset)
|
||||
begin
|
||||
desc3 = handle3;
|
||||
#0 start = 1'b0;
|
||||
#0 S = 1'b1;
|
||||
#0 reset = 1'b1;
|
||||
#30 reset = 1'b0;
|
||||
#30 N = 64'h0;
|
||||
#0 D = 64'h0;
|
||||
for (i=0; i<`IDIV_TESTS; i=i+1)
|
||||
begin
|
||||
N = {$urandom(), $urandom()};
|
||||
D = {$urandom(), $urandom()};
|
||||
start <= 1'b1;
|
||||
// Wait 2 cycles (to be sure)
|
||||
repeat (2)
|
||||
@(posedge clk);
|
||||
start <= 1'b0;
|
||||
repeat (41)
|
||||
@(posedge clk);
|
||||
Ncomp = N;
|
||||
Dcomp = D;
|
||||
Qcomp = $signed(Ncomp)/$signed(Dcomp);
|
||||
Rcomp = $signed(Ncomp)%$signed(Dcomp);
|
||||
if ((Q !== Qcomp)) begin
|
||||
errors = errors + 1;
|
||||
end
|
||||
vectornum = vectornum + 1;
|
||||
$fdisplay(desc3, "%h %h %h %h || %h %h || %b %b",
|
||||
N, D, Q, rem0, Qcomp, Rcomp,
|
||||
(Q==Qcomp), (rem0==Rcomp));
|
||||
end // for (i=0; i<2, i=i+1)
|
||||
$display("%d tests completed, %d errors", vectornum, errors);
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule // tb
|
||||
1026
pipelined/srt/stine/tmp
Normal file
1026
pipelined/srt/stine/tmp
Normal file
File diff suppressed because it is too large
Load Diff
@ -197,6 +197,8 @@ def oneMetricPlot(module, var, freq=None, ax=None, fits='clsgn', norm=True, colo
|
||||
allMetrics = []
|
||||
|
||||
ale = (var != 'delay') # if not delay, must be area, leakage, or energy
|
||||
modFit = fitDict[mod]
|
||||
fits = modFit[ale]
|
||||
|
||||
for spec in techSpecs:
|
||||
metric = getVals(spec.tech, module, var, freq=freq)
|
||||
@ -207,8 +209,8 @@ def oneMetricPlot(module, var, freq=None, ax=None, fits='clsgn', norm=True, colo
|
||||
metric = [m/norm for m in metric]
|
||||
|
||||
if len(metric) == 5: # don't include the spec if we don't have points for all widths
|
||||
xp, pred, leg = regress(widths, metric, spec, fits, ale=ale)
|
||||
fullLeg += leg
|
||||
xp, pred, coefs, r2 = regress(widths, metric, fits)
|
||||
fullLeg += genLegend(fits, coefs, r2, spec, ale=ale)
|
||||
c = color if color else spec.color
|
||||
ax.scatter(widths, metric, color=c, marker=spec.shape)
|
||||
ax.plot(xp, pred, color=c)
|
||||
@ -216,7 +218,8 @@ def oneMetricPlot(module, var, freq=None, ax=None, fits='clsgn', norm=True, colo
|
||||
allMetrics += metric
|
||||
|
||||
combined = TechSpec('combined', 'red', '_', 0, 0, 0, 0)
|
||||
xp, pred, leg = regress(allWidths, allMetrics, combined, fits, ale=ale)
|
||||
xp, pred, coefs, r2 = regress(allWidths, allMetrics, fits)
|
||||
leg = genLegend(fits, coefs, r2, combined, ale=ale)
|
||||
fullLeg += leg
|
||||
ax.plot(xp, pred, color='red')
|
||||
|
||||
@ -232,14 +235,17 @@ def oneMetricPlot(module, var, freq=None, ax=None, fits='clsgn', norm=True, colo
|
||||
|
||||
if (module in ['flop', 'csa']) & (var == 'delay'):
|
||||
ax.set_ylim(ymin=0)
|
||||
ytop = ax.get_ylim()[1]
|
||||
ax.set_ylim(ymax=1.1*ytop)
|
||||
|
||||
if singlePlot:
|
||||
titleStr = " (target " + str(freq)+ "MHz)" if freq != None else " (best achievable delay)"
|
||||
ax.set_title(module + titleStr)
|
||||
plt.savefig('./plots/PPA/'+ module + '_' + var + '.png')
|
||||
# plt.show()
|
||||
return fullLeg
|
||||
|
||||
def regress(widths, var, spec, fits='clsgn', ale=False):
|
||||
def regress(widths, var, fits='clsgn'):
|
||||
''' fits a curve to the given points
|
||||
returns lists of x and y values to plot that curve and legend elements with the equation
|
||||
'''
|
||||
@ -267,28 +273,41 @@ def regress(widths, var, spec, fits='clsgn', ale=False):
|
||||
for x in xp:
|
||||
n = [func(x/normAddWidth) for func in funcArr]
|
||||
pred += [sum(np.multiply(coefs, n))]
|
||||
|
||||
leg = genLegend(fits, coefs, r2, spec, ale=ale)
|
||||
|
||||
return xp, pred, leg
|
||||
return xp, pred, coefs, r2
|
||||
|
||||
def makeCoefTable(tech):
|
||||
''' not currently in use, may salvage later
|
||||
def makeCoefTable():
|
||||
'''
|
||||
writes CSV with each line containing the coefficients for a regression fit
|
||||
to a particular combination of module, metric, and target frequency
|
||||
to a particular combination of module, metric (including both techs, normalized)
|
||||
'''
|
||||
file = open("ppaFitting.csv", "w")
|
||||
writer = csv.writer(file)
|
||||
writer.writerow(['Module', 'Metric', 'Freq', '1', 'N', 'N^2', 'log2(N)', 'Nlog2(N)', 'R^2'])
|
||||
writer.writerow(['Module', 'Metric', '1', 'N', 'N^2', 'log2(N)', 'Nlog2(N)', 'R^2'])
|
||||
|
||||
for mod in ['add', 'mult', 'comparator', 'shifter']:
|
||||
for comb in [['delay', 5000], ['area', 5000], ['area', 10]]:
|
||||
var = comb[0]
|
||||
freq = comb[1]
|
||||
metric = getVals(tech, mod, freq, var)
|
||||
global widths
|
||||
coefs, r2, funcArr = regress(widths, metric)
|
||||
row = [mod] + comb + np.ndarray.tolist(coefs) + [r2]
|
||||
for module in modules:
|
||||
for var in ['delay', 'area', 'lpower', 'denergy']:
|
||||
ale = (var != 'delay')
|
||||
metL = []
|
||||
modFit = fitDict[module]
|
||||
fits = modFit[ale]
|
||||
|
||||
for spec in techSpecs:
|
||||
metric = getVals(spec.tech, module, var)
|
||||
techdict = spec._asdict()
|
||||
norm = techdict[var]
|
||||
metL += [m/norm for m in metric]
|
||||
|
||||
xp, pred, coefs, r2 = regress(widths*2, metL, fits)
|
||||
coefs = np.ndarray.tolist(coefs)
|
||||
coefsToWrite = [None]*5
|
||||
fitTerms = 'clsgn'
|
||||
ind = 0
|
||||
for i in range(len(fitTerms)):
|
||||
if fitTerms[i] in fits:
|
||||
coefsToWrite[i] = coefs[ind]
|
||||
ind += 1
|
||||
row = [module, var] + coefsToWrite + [r2]
|
||||
writer.writerow(row)
|
||||
|
||||
file.close()
|
||||
@ -341,8 +360,8 @@ def freqPlot(tech, mod, width):
|
||||
|
||||
median = np.median(list(flatten(freqsL)))
|
||||
|
||||
f, (ax1, ax2, ax3, ax4) = plt.subplots(4, 1, sharex=True)
|
||||
for ax in (ax1, ax2, ax3, ax4):
|
||||
f, (ax1, ax2) = plt.subplots(2, 1, sharex=True)
|
||||
for ax in (ax1, ax2): #, ax3, ax4):
|
||||
ax.ticklabel_format(useOffset=False, style='plain')
|
||||
|
||||
for ind in [0,1]:
|
||||
@ -353,23 +372,23 @@ def freqPlot(tech, mod, width):
|
||||
freqs, delays, areas = noOutliers(median, freqs, delays, areas) # comment out to see all syntheses
|
||||
|
||||
c = 'blue' if ind else 'green'
|
||||
adprod = adprodpow(areas, delays, 1)
|
||||
adpow = adprodpow(areas, delays, 2)
|
||||
# adprod = adprodpow(areas, delays, 1)
|
||||
# adpow = adprodpow(areas, delays, 2)
|
||||
ax1.scatter(freqs, delays, color=c)
|
||||
ax2.scatter(freqs, areas, color=c)
|
||||
ax3.scatter(freqs, adprod, color=c)
|
||||
ax4.scatter(freqs, adpow, color=c)
|
||||
# ax3.scatter(freqs, adprod, color=c)
|
||||
# ax4.scatter(freqs, adpow, color=c)
|
||||
|
||||
legend_elements = [lines.Line2D([0], [0], color='green', ls='', marker='o', label='timing achieved'),
|
||||
lines.Line2D([0], [0], color='blue', ls='', marker='o', label='slack violated')]
|
||||
|
||||
ax1.legend(handles=legend_elements)
|
||||
|
||||
ax4.set_xlabel("Target Freq (MHz)")
|
||||
ax2.set_xlabel("Target Freq (MHz)")
|
||||
ax1.set_ylabel('Delay (ns)')
|
||||
ax2.set_ylabel('Area (sq microns)')
|
||||
ax3.set_ylabel('Area * Delay')
|
||||
ax4.set_ylabel('Area * $Delay^2$')
|
||||
# ax3.set_ylabel('Area * Delay')
|
||||
# ax4.set_ylabel('Area * $Delay^2$')
|
||||
ax1.set_title(mod + '_' + str(width))
|
||||
plt.savefig('./plots/freqBuckshot/' + tech + '/' + mod + '/' + str(width) + '.png')
|
||||
# plt.show()
|
||||
@ -464,23 +483,31 @@ def plotPPA(mod, freq=None, norm=True, aleOpt=False):
|
||||
if no freq specified, uses the synthesis with best achievable delay for each width
|
||||
overlays data from both techs
|
||||
'''
|
||||
plt.rcParams["figure.figsize"] = (12,8)
|
||||
plt.rcParams["figure.figsize"] = (10,7)
|
||||
fig, axs = plt.subplots(2, 2)
|
||||
modFit = fitDict[mod]
|
||||
# fig, axs = plt.subplots(4, 1)
|
||||
|
||||
oneMetricPlot(mod, 'delay', ax=axs[0,0], fits=modFit[0], freq=freq, norm=norm)
|
||||
oneMetricPlot(mod, 'area', ax=axs[0,1], fits=modFit[1], freq=freq, norm=norm)
|
||||
oneMetricPlot(mod, 'lpower', ax=axs[1,0], fits=modFit[1], freq=freq, norm=norm)
|
||||
oneMetricPlot(mod, 'denergy', ax=axs[1,1], fits=modFit[1], freq=freq, norm=norm)
|
||||
# oneMetricPlot(mod, 'delay', ax=axs[0], fits=modFit[0], freq=freq, norm=norm)
|
||||
# oneMetricPlot(mod, 'area', ax=axs[1], fits=modFit[1], freq=freq, norm=norm)
|
||||
# oneMetricPlot(mod, 'lpower', ax=axs[2], fits=modFit[1], freq=freq, norm=norm)
|
||||
# oneMetricPlot(mod, 'denergy', ax=axs[3], fits=modFit[1], freq=freq, norm=norm)
|
||||
oneMetricPlot(mod, 'delay', ax=axs[0,0], freq=freq, norm=norm)
|
||||
oneMetricPlot(mod, 'area', ax=axs[0,1], freq=freq, norm=norm)
|
||||
oneMetricPlot(mod, 'lpower', ax=axs[1,0], freq=freq, norm=norm)
|
||||
fullLeg = oneMetricPlot(mod, 'denergy', ax=axs[1,1], freq=freq, norm=norm)
|
||||
|
||||
if aleOpt:
|
||||
oneMetricPlot(mod, 'area', ax=axs[0,1], fits=modFit[1], freq=10, norm=norm, color='black')
|
||||
oneMetricPlot(mod, 'lpower', ax=axs[1,0], fits=modFit[1], freq=10, norm=norm, color='black')
|
||||
oneMetricPlot(mod, 'denergy', ax=axs[1,1], fits=modFit[1], freq=10, norm=norm, color='black')
|
||||
oneMetricPlot(mod, 'area', ax=axs[0,1], freq=10, norm=norm, color='black')
|
||||
oneMetricPlot(mod, 'lpower', ax=axs[1,0], freq=10, norm=norm, color='black')
|
||||
oneMetricPlot(mod, 'denergy', ax=axs[1,1], freq=10, norm=norm, color='black')
|
||||
|
||||
titleStr = " (target " + str(freq)+ "MHz)" if freq != None else " (best achievable delay)"
|
||||
n = 'normalized' if norm else 'unnormalized'
|
||||
saveStr = './plots/PPA/'+ n + '/' + mod + '.png'
|
||||
plt.suptitle(mod + titleStr)
|
||||
|
||||
# fig.legend(handles=fullLeg, ncol=3, loc='center', bbox_to_anchor=(0.3, 0.82, 0.4, 0.2))
|
||||
|
||||
if freq != 10: plt.savefig(saveStr)
|
||||
# plt.show()
|
||||
|
||||
@ -511,7 +538,7 @@ if __name__ == '__main__':
|
||||
|
||||
fitDict = {'add': ['cg', 'l', 'l'], 'mult': ['cg', 's', 'ls'], 'comparator': ['cg', 'l', 'l'], 'csa': ['c', 'l', 'l'], 'shiftleft': ['cg', 'l', 'ln'], 'flop': ['c', 'l', 'l'], 'priorityencoder': ['cg', 'l', 'l']}
|
||||
fitDict.update(dict.fromkeys(['mux2', 'mux4', 'mux8'], ['cg', 'l', 'l']))
|
||||
leftblue = [['mux2', 'sky90', 32], ['mux2', 'sky90', 64], ['mux2', 'sky90', 128], ['mux2', 'tsmc28', 16], ['mux2', 'tsmc28', 8], ['mux8', 'sky90', 32]]
|
||||
leftblue = [['mux2', 'sky90', 32], ['mux2', 'sky90', 64], ['mux2', 'sky90', 128], ['mux8', 'sky90', 32], ['mux2', 'tsmc28', 8], ['mux2', 'tsmc28', 64]]
|
||||
|
||||
TechSpec = namedtuple("TechSpec", "tech color shape delay area lpower denergy")
|
||||
techSpecs = [['sky90', 'green', 'o', 43.2e-3, 1330.84, 582.81, 520.66], ['tsmc28', 'blue', '^', 12.2e-3, 209.29, 1060, 81.43]]
|
||||
@ -529,12 +556,13 @@ if __name__ == '__main__':
|
||||
# squareAreaDelay('sky90', 'add', 32)
|
||||
# oneMetricPlot('add', 'delay')
|
||||
# freqPlot('sky90', 'mux4', 16)
|
||||
# makeCoefTable()
|
||||
|
||||
for mod in modules:
|
||||
# plotPPA(mod, norm=False)
|
||||
plotPPA(mod, aleOpt=True)
|
||||
plotBestAreas(mod)
|
||||
for w in [8, 16, 32, 64, 128]:
|
||||
freqPlot('sky90', mod, w)
|
||||
freqPlot('tsmc28', mod, w)
|
||||
for mod in ['mux2']: #modules:
|
||||
plotPPA(mod, norm=False)
|
||||
plotPPA(mod) #, aleOpt=True)
|
||||
# plotBestAreas(mod)
|
||||
# for w in [8, 16, 32, 64, 128]:
|
||||
# freqPlot('sky90', mod, w)
|
||||
# freqPlot('tsmc28', mod, w)
|
||||
plt.close('all')
|
||||
@ -1,13 +1,41 @@
|
||||
Module,Metric,Freq,1,N,N^2,log2(N),Nlog2(N),R^2
|
||||
add,delay,5000,-0.038978555556527635,-0.08911531250030817,-0.00012953428819478948,0.2083593333340971,0.013950093750045424,1.0
|
||||
add,area,5000,-1913.1778463362505,-268.21377075092175,-0.4100347526051751,1046.9667200022955,47.59125331263557,1.0
|
||||
add,area,10,-13.720001333167332,14.700000312552621,1.3021426840869221e-09,-1.3062278840780171e-10,-9.375775472819561e-08,1.0
|
||||
mult,delay,5000,-0.2915958888891911,-0.02828693750009581,-3.445876736121953e-05,0.32169033333357117,0.0044735312500140964,1.0
|
||||
mult,area,5000,27780.605184113756,10418.196477973508,26.857274703166343,-24448.387256089416,-1468.2850310678027,1.0
|
||||
mult,area,10,-6472.791005245042,-2075.5787013197305,8.20962684330778,5345.246556351299,313.5693677823146,1.0
|
||||
comparator,delay,5000,0.1903951111111219,0.000987500000002994,3.427951388890516e-06,3.333333324460974e-06,-0.00012593750000039925,1.0
|
||||
comparator,area,5000,-508.51109056188875,-579.7924890645068,-1.0888888741341944,969.5466443383111,101.5524983752957,1.0
|
||||
comparator,area,10,-155.6022268893253,-40.3637507501383,-0.07230902908001494,132.9533363336765,8.452500156270371,1.0
|
||||
shifter,delay,5000,0.06953233333235516,-0.08957893750031035,-0.00015877864583368578,0.16727300000076853,0.014763625000045773,1.0
|
||||
shifter,area,5000,-237.48663487568587,1208.7075255666841,1.5708073263938906,-1678.7400476770383,-166.69187856311666,1.0
|
||||
shifter,area,10,-1079.4155736731122,-591.3687615645423,-0.877491337241916,1211.9333560050677,103.11437703155087,1.0
|
||||
Module,Metric,1,N,N^2,log2(N),Nlog2(N),R^2
|
||||
priorityencoder,delay,4.865032478368464,,,1.0346781590203091,,0.990533246983837
|
||||
priorityencoder,area,,0.3296349181169891,,,,0.9718942704677337
|
||||
priorityencoder,lpower,,0.2508481588069769,,,,0.9418329012771585
|
||||
priorityencoder,denergy,,0.09327161156406552,,,,0.8065924672945542
|
||||
add,delay,8.961254531683414,,,1.4310340215065527,,0.9564367595740637
|
||||
add,area,,1.0710989265923485,,,,0.988580182173048
|
||||
add,lpower,,0.9470245397661955,,,,0.9951383820581323
|
||||
add,denergy,,0.9954952282287014,,,,0.9928308616130285
|
||||
csa,delay,3.590384717869601,,,,,0.0
|
||||
csa,area,,0.9312877569527923,,,,0.999393942859829
|
||||
csa,lpower,,1.5320774877598933,,,,0.9400384192534433
|
||||
csa,denergy,,1.1454135769936609,,,,0.9735205275004183
|
||||
shiftleft,delay,8.66019468793489,,,1.6351711913499432,,0.9873681453602638
|
||||
shiftleft,area,,1.9102134686740575,,,,0.9466461680123697
|
||||
shiftleft,lpower,,2.277088275290811,,,,0.9624044038708768
|
||||
shiftleft,denergy,,1.4931073444617051,,,,0.9454881696599784
|
||||
comparator,delay,6.680678539086959,,,0.9397668550976327,,0.98789326603378
|
||||
comparator,area,,0.6003877936704982,,,,0.9672416909621802
|
||||
comparator,lpower,,0.46756802348373877,,,,0.8609362596824635
|
||||
comparator,denergy,,0.3089180049610159,,,,0.8267293340232036
|
||||
flop,delay,3.3270503187614153,,,,,0.0
|
||||
flop,area,,0.34478305655859876,,,,0.9433629202566682
|
||||
flop,lpower,,0.3707856336608904,,,,0.9170347531086821
|
||||
flop,denergy,,0.0011765517257429892,,,,0.688648230209356
|
||||
mux2,delay,4.732514086885074,,,0.38138175938205005,,0.5638177354804589
|
||||
mux2,area,,0.19794547955000782,,,,0.9753613114571431
|
||||
mux2,lpower,,0.1881638557015794,,,,0.7572248871637561
|
||||
mux2,denergy,,0.16278100836605952,,,,0.9811112115671446
|
||||
mux4,delay,5.67790744523475,,,0.5081925137582493,,0.8316415055210026
|
||||
mux4,area,,0.35778033738856435,,,,0.9880049722019894
|
||||
mux4,lpower,,0.32236674794207065,,,,0.8279138454959137
|
||||
mux4,denergy,,0.28073375091037084,,,,0.9943662618662574
|
||||
mux8,delay,7.252700330388384,,,0.45254210999717837,,0.8464368692304263
|
||||
mux8,area,,0.7614128432326613,,,,0.9863118376555963
|
||||
mux8,lpower,,0.6570734849206145,,,,0.9855956038468652
|
||||
mux8,denergy,,0.4496346388149245,,,,0.9785597135426944
|
||||
mult,delay,29.562138166420393,,,6.711916207386673,,0.9833266087176287
|
||||
mult,area,,,13.838943348894976,,,0.9875861886135875
|
||||
mult,lpower,,,14.380577146903335,,,0.9349609233308782
|
||||
mult,denergy,,,36.51397409545879,,,0.9719012952478829
|
||||
|
||||
|
@ -74,6 +74,9 @@ if { $saifpower == 1 } {
|
||||
if {$drive != "INV"} {
|
||||
set_false_path -from [get_ports reset]
|
||||
}
|
||||
if {(($::env(DESIGN) == "ppa_mux2_1") || ($::env(DESIGN) == "ppa_mux4_1") || ($::env(DESIGN) == "ppa_mux8_1"))} {
|
||||
set_false_path -from {s}
|
||||
}
|
||||
|
||||
# Set Frequency in [MHz] or period in [ns]
|
||||
set my_clock_pin clk
|
||||
|
||||
Loading…
Reference in New Issue
Block a user