mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Added fp tests - doesnpass yet
This commit is contained in:
Katherine Parry
parent
c96f07ad75
commit
738bbf6479
@ -1 +1 @@
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Subproject commit 307c77b26e070ae85ffea665ad9b642b40e33c86
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Subproject commit be67c99bd461742aa1c100bcc0732657faae2230
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@ -38,12 +38,13 @@
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`define IEEE754 1
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// MISA RISC-V configuration per specification
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`define MISA (32'h00000104 | 1 << 5 | 0 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 )
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//16 - quad 3 - double 5 - single
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`define MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 )
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`define ZICSR_SUPPORTED 1
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`define ZIFENCEI_SUPPORTED 1
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`define COUNTERS 32
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`define ZICOUNTERS_SUPPORTED 1
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`define ZFH_SUPPORTED 0
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`define ZFH_SUPPORTED 1
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/// Microarchitectural Features
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`define UARCH_PIPELINED 1
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52
pipelined/regression/fp.do
Normal file
52
pipelined/regression/fp.do
Normal file
@ -0,0 +1,52 @@
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# wally-pipelined.do
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#
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# Modification by Oklahoma State University & Harvey Mudd College
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# Use with Testbench
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# James Stine, 2008; David Harris 2021
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# Go Cowboys!!!!!!
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#
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# Takes 1:10 to run RV64IC tests using gui
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# run with vsim -do "do wally-pipelined.do rv64ic riscvarchtest-64m"
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# Use this wally-pipelined.do file to run this example.
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# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
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# do wally-pipelined.do
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# or, to run from a shell, type the following at the shell prompt:
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# vsim -do wally-pipelined.do -c
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# (omit the "-c" to see the GUI while running from the shell)
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onbreak {resume}
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# create library
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if [file exists work] {
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vdel -all
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}
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vlib work
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# compile source files
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# suppress spurious warnngs about
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# "Extra checking for conflicts with always_comb done at vopt time"
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# because vsim will run vopt
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# start and run simulation
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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# $num = the added words after the call
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vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-fp.sv ../src/fpu/*.sv -suppress 2583,7063,8607,2697
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vsim -voptargs=+acc work.testbenchfp -G TEST=$2
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view wave
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#-- display input and output signals as hexidecimal values
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#do ./wave-dos/peripheral-waves.do
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#add log -recursive /*
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#do wave.do deal with when ready
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do wave-fpu.do
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#-- Run the Simulation
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#run 3600
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run -all
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noview testbench-fp.sv
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view wave
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11
pipelined/regression/sim-fp
Executable file
11
pipelined/regression/sim-fp
Executable file
@ -0,0 +1,11 @@
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# cvtint - test integer conversion unit (fcvtint)
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# cvtfp - test floating-point conversion unit (fcvtfp)
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# cmp - test comparison unit's LT, LE, EQ opperations (fcmp)
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# add - test addition
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# sub - test subtraction
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# div - test division
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# sqrt - test square root
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# all - test everything
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vsim -do "do fp.do rv64fp mul"
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10
pipelined/regression/sim-fp-batch
Executable file
10
pipelined/regression/sim-fp-batch
Executable file
@ -0,0 +1,10 @@
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# cvtint - test integer conversion unit (fcvtint)
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# cvtfp - test floating-point conversion unit (fcvtfp)
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# cmp - test comparison unit's LT, LE, EQ opperations (fcmp)
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# add - test addition
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# sub - test subtraction
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# div - test division
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# sqrt - test square root
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# all - test everything
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vsim -c -do "do fp.do rv64fp fma"
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102
pipelined/regression/wave-fpu.do
Normal file
102
pipelined/regression/wave-fpu.do
Normal file
@ -0,0 +1,102 @@
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add wave -noupdate /testbenchfp/clk
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add wave -noupdate -radix decimal /testbenchfp/VectorNum
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add wave -group Other -noupdate /testbenchfp/FrmNum
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add wave -group Other -noupdate /testbenchfp/X
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add wave -group Other -noupdate /testbenchfp/Y
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add wave -group Other -noupdate /testbenchfp/Z
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add wave -group Other -noupdate /testbenchfp/Res
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add wave -group Other -noupdate /testbenchfp/Ans
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add wave -group Rne -noupdate /testbenchfp/FmaRneX
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add wave -group Rne -noupdate /testbenchfp/FmaRneY
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add wave -group Rne -noupdate /testbenchfp/FmaRneZ
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add wave -group Rne -noupdate /testbenchfp/FmaRneRes
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add wave -group Rne -noupdate /testbenchfp/FmaRneAns
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add wave -group Rz -noupdate /testbenchfp/FmaRzX
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add wave -group Rz -noupdate /testbenchfp/FmaRzY
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add wave -group Rz -noupdate /testbenchfp/FmaRzZ
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add wave -group Rz -noupdate /testbenchfp/FmaRzRes
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add wave -group Rz -noupdate /testbenchfp/FmaRzAns
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add wave -group Ru -noupdate /testbenchfp/FmaRuX
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add wave -group Ru -noupdate /testbenchfp/FmaRuY
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add wave -group Ru -noupdate /testbenchfp/FmaRuZ
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add wave -group Ru -noupdate /testbenchfp/FmaRuRes
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add wave -group Ru -noupdate /testbenchfp/FmaRuAns
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add wave -group Rd -noupdate /testbenchfp/FmaRdX
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add wave -group Rd -noupdate /testbenchfp/FmaRdY
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add wave -group Rd -noupdate /testbenchfp/FmaRdZ
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add wave -group Rd -noupdate /testbenchfp/FmaRdRes
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add wave -group Rd -noupdate /testbenchfp/FmaRdAns
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add wave -group Rnm -noupdate /testbenchfp/FmaRnmX
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add wave -group Rnm -noupdate /testbenchfp/FmaRnmY
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add wave -group Rnm -noupdate /testbenchfp/FmaRnmZ
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add wave -group Rnm -noupdate /testbenchfp/FmaRnmRes
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add wave -group Rnm -noupdate /testbenchfp/FmaRnmAns
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add wave -group AllSignals -noupdate /*
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add wave -group AllSignals -noupdate /testbenchfp/*
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add wave -group AllSignals -noupdate /testbenchfp/fma1rne/*
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add wave -group AllSignals -noupdate /testbenchfp/fma1rne/expadd/*
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add wave -group AllSignals -noupdate /testbenchfp/fma1rne/mult/*
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add wave -group AllSignals -noupdate /testbenchfp/fma1rne/align/*
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add wave -group AllSignals -noupdate /testbenchfp/fma1rne/sign/*
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add wave -group AllSignals -noupdate /testbenchfp/fma1rne/add/*
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add wave -group AllSignals -noupdate /testbenchfp/fma1rne/loa/*
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add wave -group AllSignals -noupdate /testbenchfp/fma2rne/*
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add wave -group AllSignals -noupdate /testbenchfp/fma2rne/normalize/*
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add wave -group AllSignals -noupdate /testbenchfp/fma2rne/fmaround/*
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add wave -group AllSignals -noupdate /testbenchfp/fma2rne/resultsign/*
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add wave -group AllSignals -noupdate /testbenchfp/fma2rne/fmaflags/*
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add wave -group AllSignals -noupdate /testbenchfp/fma2rne/resultselect/*
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add wave -group AllSignals -noupdate /testbenchfp/fma1rz/*
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add wave -group AllSignals -noupdate /testbenchfp/fma1rz/expadd/*
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add wave -group AllSignals -noupdate /testbenchfp/fma1rz/mult/*
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add wave -group AllSignals -noupdate /testbenchfp/fma1rz/align/*
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add wave -group AllSignals -noupdate /testbenchfp/fma1rz/sign/*
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add wave -group AllSignals -noupdate /testbenchfp/fma1rz/add/*
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add wave -group AllSignals -noupdate /testbenchfp/fma1rz/loa/*
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add wave -group AllSignals -noupdate /testbenchfp/fma2rz/*
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add wave -group AllSignals -noupdate /testbenchfp/fma2rz/normalize/*
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add wave -group AllSignals -noupdate /testbenchfp/fma2rz/fmaround/*
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add wave -group AllSignals -noupdate /testbenchfp/fma2rz/resultsign/*
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add wave -group AllSignals -noupdate /testbenchfp/fma2rz/fmaflags/*
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add wave -group AllSignals -noupdate /testbenchfp/fma2rz/resultselect/*
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add wave -group AllSignals -noupdate /testbenchfp/fma1ru/*
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add wave -group AllSignals -noupdate /testbenchfp/fma1ru/expadd/*
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add wave -group AllSignals -noupdate /testbenchfp/fma1ru/mult/*
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add wave -group AllSignals -noupdate /testbenchfp/fma1ru/align/*
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add wave -group AllSignals -noupdate /testbenchfp/fma1ru/sign/*
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add wave -group AllSignals -noupdate /testbenchfp/fma1ru/add/*
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add wave -group AllSignals -noupdate /testbenchfp/fma1ru/loa/*
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add wave -group AllSignals -noupdate /testbenchfp/fma2ru/*
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add wave -group AllSignals -noupdate /testbenchfp/fma2ru/normalize/*
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add wave -group AllSignals -noupdate /testbenchfp/fma2ru/fmaround/*
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add wave -group AllSignals -noupdate /testbenchfp/fma2ru/resultsign/*
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add wave -group AllSignals -noupdate /testbenchfp/fma2ru/fmaflags/*
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add wave -group AllSignals -noupdate /testbenchfp/fma2ru/resultselect/*
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add wave -group AllSignals -noupdate /testbenchfp/fma1rd/*
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add wave -group AllSignals -noupdate /testbenchfp/fma1rd/expadd/*
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add wave -group AllSignals -noupdate /testbenchfp/fma1rd/mult/*
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add wave -group AllSignals -noupdate /testbenchfp/fma1rd/align/*
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add wave -group AllSignals -noupdate /testbenchfp/fma1rd/sign/*
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add wave -group AllSignals -noupdate /testbenchfp/fma1rd/add/*
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add wave -group AllSignals -noupdate /testbenchfp/fma1rd/loa/*
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add wave -group AllSignals -noupdate /testbenchfp/fma2rd/*
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add wave -group AllSignals -noupdate /testbenchfp/fma2rd/normalize/*
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add wave -group AllSignals -noupdate /testbenchfp/fma2rd/fmaround/*
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add wave -group AllSignals -noupdate /testbenchfp/fma2rd/resultsign/*
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add wave -group AllSignals -noupdate /testbenchfp/fma2rd/fmaflags/*
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add wave -group AllSignals -noupdate /testbenchfp/fma2rd/resultselect/*
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add wave -group AllSignals -noupdate /testbenchfp/fma1rnm/*
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add wave -group AllSignals -noupdate /testbenchfp/fma1rnm/expadd/*
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add wave -group AllSignals -noupdate /testbenchfp/fma1rnm/mult/*
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add wave -group AllSignals -noupdate /testbenchfp/fma1rnm/align/*
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add wave -group AllSignals -noupdate /testbenchfp/fma1rnm/sign/*
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add wave -group AllSignals -noupdate /testbenchfp/fma1rnm/add/*
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add wave -group AllSignals -noupdate /testbenchfp/fma1rnm/loa/*
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add wave -group AllSignals -noupdate /testbenchfp/fma2rnm/*
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add wave -group AllSignals -noupdate /testbenchfp/fma2rnm/normalize/*
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add wave -group AllSignals -noupdate /testbenchfp/fma2rnm/fmaround/*
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add wave -group AllSignals -noupdate /testbenchfp/fma2rnm/resultsign/*
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add wave -group AllSignals -noupdate /testbenchfp/fma2rnm/fmaflags/*
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add wave -group AllSignals -noupdate /testbenchfp/fma2rnm/resultselect/*
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@ -1,6 +1,6 @@
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`include "wally-config.vh"
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module cvtfp (
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module fcvtfp (
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input logic [10:0] XExpE, // input's exponent
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input logic [52:0] XManE, // input's mantissa
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input logic XSgnE, // input's sign
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@ -2,7 +2,7 @@
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`include "wally-config.vh"
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// `include "../../config/rv64icfd/wally-config.vh"
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// `define XLEN 64
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module fcvt (
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module fcvtint (
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input logic XSgnE, // X's sign
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input logic [10:0] XExpE, // X's exponent
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input logic [52:0] XManE, // X's fraction
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@ -213,12 +213,12 @@ module fpu (
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.FDivBusyE, .done(FDivSqrtDoneE), .AS_Result(FDivResM), .Flags(FDivFlgM));
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// other FP execution units
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cvtfp cvtfp (.XExpE, .XManE, .XSgnE, .XZeroE, .XDenormE, .XInfE, .XNaNE, .XSNaNE, .FrmE, .FmtE, .CvtFpResE, .CvtFpFlgE);
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fcvtfp fcvtfp (.XExpE, .XManE, .XSgnE, .XZeroE, .XDenormE, .XInfE, .XNaNE, .XSNaNE, .FrmE, .FmtE, .CvtFpResE, .CvtFpFlgE);
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fcmp fcmp (.FmtE, .FOpCtrlE, .XSgnE, .YSgnE, .XExpE, .YExpE, .XManE, .YManE,
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.XZeroE, .YZeroE, .XNaNE, .YNaNE, .XSNaNE, .YSNaNE, .FSrcXE, .FSrcYE, .CmpNVE, .CmpResE);
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fsgn fsgn (.SgnOpCodeE(FOpCtrlE[1:0]), .XSgnE, .YSgnE, .FSrcXE, .FmtE, .SgnResE);
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fclassify fclassify (.XSgnE, .XDenormE, .XZeroE, .XNaNE, .XInfE, .XNormE, .XSNaNE, .ClassResE);
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fcvt fcvt (.XSgnE, .XExpE, .XManE, .XZeroE, .XNaNE, .XInfE, .XDenormE, .ForwardedSrcAE, .FOpCtrlE, .FmtE, .FrmE,
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fcvtint fcvtint (.XSgnE, .XExpE, .XManE, .XZeroE, .XNaNE, .XInfE, .XDenormE, .ForwardedSrcAE, .FOpCtrlE, .FmtE, .FrmE,
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.CvtResE, .CvtFlgE);
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// data to be stored in memory - to IEU
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@ -2,7 +2,7 @@
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module unpack (
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input logic [`FLEN-1:0] X, Y, Z, // inputs from register file
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input logic [`FPSIZES/3:0] FmtE, // format signal 00 - single 10 - double 11 - quad 10 - half
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input logic [`FPSIZES/3:0] FmtE, // format signal 00 - single 01 - double 11 - quad 10 - half
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output logic XSgnE, YSgnE, ZSgnE, // sign bits of XYZ
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output logic [`NE-1:0] XExpE, YExpE, ZExpE, // exponents of XYZ (converted to largest supported precision)
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output logic [`NF:0] XManE, YManE, ZManE, // mantissas of XYZ (converted to largest supported precision)
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@ -50,7 +50,6 @@ module unpack (
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end else if (`FPSIZES == 2) begin // if there are 2 floating point formats supported
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//***need better names for these constants
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// largest format | smaller format
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//----------------------------------
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@ -339,9 +338,9 @@ module unpack (
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ZExpE = {ZLen1[`D_LEN-2], {`Q_NE-`D_NE{~ZLen1[`D_LEN-2]&~ZExpZero|ZExpMaxE}}, ZLen1[`D_LEN-3:`D_NF]};
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// extract the fraction and add the nessesary trailing zeros
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XFracE = {XLen1[`D_NE-1:0], (`Q_NF-`D_NE)'(0)};
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YFracE = {YLen1[`D_NE-1:0], (`Q_NF-`D_NE)'(0)};
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ZFracE = {ZLen1[`D_NE-1:0], (`Q_NF-`D_NE)'(0)};
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XFracE = {XLen1[`D_NF-1:0], (`Q_NF-`D_NF)'(0)};
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YFracE = {YLen1[`D_NF-1:0], (`Q_NF-`D_NF)'(0)};
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ZFracE = {ZLen1[`D_NF-1:0], (`Q_NF-`D_NF)'(0)};
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// is the exponent non-zero
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XExpNonzero = |XLen1[`D_LEN-2:`D_NE];
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1538
pipelined/testbench/testbench-fp.sv
Normal file
1538
pipelined/testbench/testbench-fp.sv
Normal file
File diff suppressed because it is too large
Load Diff
587
pipelined/testbench/tests-fp.vh
Normal file
587
pipelined/testbench/tests-fp.vh
Normal file
@ -0,0 +1,587 @@
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///////////////////////////////////////////
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// tests.vh
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//
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// Written: David_Harris@hmc.edu 7 October 2021
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// Modified:
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//
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// Purpose: List of tests to apply
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`define PATH "../../tests/fp/vectors/"
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`define ADD_OPCTRL 3'b110
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`define MUL_OPCTRL 3'b100
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`define SUB_OPCTRL 3'b111
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`define FADD_OPCTRL 3'b000
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`define DIV_OPCTRL 3'b000
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`define SQRT_OPCTRL 3'b001
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`define LE_OPCTRL 3'b011
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`define LT_OPCTRL 3'b001
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`define EQ_OPCTRL 3'b010
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`define TO_UI_OPCTRL 3'b011
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`define TO_I_OPCTRL 3'b001
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`define TO_UL_OPCTRL 3'b111
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`define TO_L_OPCTRL 3'b101
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`define FROM_UI_OPCTRL 3'b010
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`define FROM_I_OPCTRL 3'b000
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`define FROM_UL_OPCTRL 3'b110
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`define FROM_L_OPCTRL 3'b100
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`define RNE 3'b000
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`define RZ 3'b001
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`define RU 3'b011
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`define RD 3'b010
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`define RNM 3'b100
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`define FMAUNIT 0
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`define DIVUNIT 1
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`define CVTINTUNIT 2
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`define CVTFPUNIT 3
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`define CMPUNIT 4
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string f16rv32cvtint[] = '{
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"f16_to_i32_rne.tv",
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"f16_to_i32_rz.tv",
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"f16_to_i32_ru.tv",
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"f16_to_i32_rd.tv",
|
||||
"f16_to_i32_rnm.tv",
|
||||
"f16_to_ui32_rne.tv",
|
||||
"f16_to_ui32_rz.tv",
|
||||
"f16_to_ui32_ru.tv",
|
||||
"f16_to_ui32_rd.tv",
|
||||
"f16_to_ui32_rnm.tv",
|
||||
"ui32_to_f16_rne.tv",
|
||||
"ui32_to_f16_rz.tv",
|
||||
"ui32_to_f16_ru.tv",
|
||||
"ui32_to_f16_rd.tv",
|
||||
"ui32_to_f16_rnm.tv",
|
||||
"i32_to_f16_rne.tv",
|
||||
"i32_to_f16_rz.tv",
|
||||
"i32_to_f16_ru.tv",
|
||||
"i32_to_f16_rd.tv",
|
||||
"i32_to_f16_rnm.tv"
|
||||
};
|
||||
|
||||
string f16rv64cvtint[] = '{
|
||||
"f16_to_ui64_rne.tv",
|
||||
"f16_to_ui64_rz.tv",
|
||||
"f16_to_ui64_ru.tv",
|
||||
"f16_to_ui64_rd.tv",
|
||||
"f16_to_ui64_rnm.tv",
|
||||
"f16_to_i64_rne.tv",
|
||||
"f16_to_i64_rz.tv",
|
||||
"f16_to_i64_ru.tv",
|
||||
"f16_to_i64_rd.tv",
|
||||
"f16_to_i64_rnm.tv",
|
||||
"ui64_to_f16_rne.tv",
|
||||
"ui64_to_f16_rz.tv",
|
||||
"ui64_to_f16_ru.tv",
|
||||
"ui64_to_f16_rd.tv",
|
||||
"ui64_to_f16_rnm.tv",
|
||||
"i64_to_f16_rne.tv",
|
||||
"i64_to_f16_rz.tv",
|
||||
"i64_to_f16_ru.tv",
|
||||
"i64_to_f16_rd.tv",
|
||||
"i64_to_f16_rnm.tv"
|
||||
};
|
||||
|
||||
string f32rv32cvtint[] = '{
|
||||
"ui32_to_f32_rne.tv",
|
||||
"ui32_to_f32_rz.tv",
|
||||
"ui32_to_f32_ru.tv",
|
||||
"ui32_to_f32_rd.tv",
|
||||
"ui32_to_f32_rnm.tv",
|
||||
"i32_to_f32_rne.tv",
|
||||
"i32_to_f32_rz.tv",
|
||||
"i32_to_f32_ru.tv",
|
||||
"i32_to_f32_rd.tv",
|
||||
"i32_to_f32_rnm.tv",
|
||||
"f32_to_ui32_rne.tv",
|
||||
"f32_to_ui32_rz.tv",
|
||||
"f32_to_ui32_ru.tv",
|
||||
"f32_to_ui32_rd.tv",
|
||||
"f32_to_ui32_rnm.tv",
|
||||
"f32_to_i32_rne.tv",
|
||||
"f32_to_i32_rz.tv",
|
||||
"f32_to_i32_ru.tv",
|
||||
"f32_to_i32_rd.tv",
|
||||
"f32_to_i32_rnm.tv"
|
||||
};
|
||||
|
||||
string f32rv64cvtint[] = '{
|
||||
"ui64_to_f32_rne.tv",
|
||||
"ui64_to_f32_rz.tv",
|
||||
"ui64_to_f32_ru.tv",
|
||||
"ui64_to_f32_rd.tv",
|
||||
"ui64_to_f32_rnm.tv",
|
||||
"i64_to_f32_rne.tv",
|
||||
"i64_to_f32_rz.tv",
|
||||
"i64_to_f32_ru.tv",
|
||||
"i64_to_f32_rd.tv",
|
||||
"i64_to_f32_rnm.tv",
|
||||
"f32_to_ui64_rne.tv",
|
||||
"f32_to_ui64_rz.tv",
|
||||
"f32_to_ui64_ru.tv",
|
||||
"f32_to_ui64_rd.tv",
|
||||
"f32_to_ui64_rnm.tv",
|
||||
"f32_to_i64_rne.tv",
|
||||
"f32_to_i64_rz.tv",
|
||||
"f32_to_i64_ru.tv",
|
||||
"f32_to_i64_rd.tv",
|
||||
"f32_to_i64_rnm.tv"
|
||||
};
|
||||
|
||||
|
||||
string f64rv32cvtint[] = '{
|
||||
"ui32_to_f64_rne.tv",
|
||||
"ui32_to_f64_rz.tv",
|
||||
"ui32_to_f64_ru.tv",
|
||||
"ui32_to_f64_rd.tv",
|
||||
"ui32_to_f64_rnm.tv",
|
||||
"i32_to_f64_rne.tv",
|
||||
"i32_to_f64_rz.tv",
|
||||
"i32_to_f64_ru.tv",
|
||||
"i32_to_f64_rd.tv",
|
||||
"i32_to_f64_rnm.tv",
|
||||
"f64_to_ui32_rne.tv",
|
||||
"f64_to_ui32_rz.tv",
|
||||
"f64_to_ui32_ru.tv",
|
||||
"f64_to_ui32_rd.tv",
|
||||
"f64_to_ui32_rnm.tv",
|
||||
"f64_to_i32_rne.tv",
|
||||
"f64_to_i32_rz.tv",
|
||||
"f64_to_i32_ru.tv",
|
||||
"f64_to_i32_rd.tv",
|
||||
"f64_to_i32_rnm.tv"
|
||||
};
|
||||
|
||||
string f64rv64cvtint[] = '{
|
||||
"ui64_to_f64_rne.tv",
|
||||
"ui64_to_f64_rz.tv",
|
||||
"ui64_to_f64_ru.tv",
|
||||
"ui64_to_f64_rd.tv",
|
||||
"ui64_to_f64_rnm.tv",
|
||||
"i64_to_f64_rne.tv",
|
||||
"i64_to_f64_rz.tv",
|
||||
"i64_to_f64_ru.tv",
|
||||
"i64_to_f64_rd.tv",
|
||||
"i64_to_f64_rnm.tv",
|
||||
"f64_to_ui64_rne.tv",
|
||||
"f64_to_ui64_rz.tv",
|
||||
"f64_to_ui64_ru.tv",
|
||||
"f64_to_ui64_rd.tv",
|
||||
"f64_to_ui64_rnm.tv",
|
||||
"f64_to_i64_rne.tv",
|
||||
"f64_to_i64_rz.tv",
|
||||
"f64_to_i64_ru.tv",
|
||||
"f64_to_i64_rd.tv",
|
||||
"f64_to_i64_rnm.tv"
|
||||
};
|
||||
|
||||
string f128rv64cvtint[] = '{
|
||||
"ui64_to_f128_rne.tv",
|
||||
"ui64_to_f128_rz.tv",
|
||||
"ui64_to_f128_ru.tv",
|
||||
"ui64_to_f128_rd.tv",
|
||||
"ui64_to_f128_rnm.tv",
|
||||
"i64_to_f128_rne.tv",
|
||||
"i64_to_f128_rz.tv",
|
||||
"i64_to_f128_ru.tv",
|
||||
"i64_to_f128_rd.tv",
|
||||
"i64_to_f128_rnm.tv",
|
||||
"f128_to_ui64_rne.tv",
|
||||
"f128_to_ui64_rz.tv",
|
||||
"f128_to_ui64_ru.tv",
|
||||
"f128_to_ui64_rd.tv",
|
||||
"f128_to_ui64_rnm.tv",
|
||||
"f128_to_i64_rne.tv",
|
||||
"f128_to_i64_rz.tv",
|
||||
"f128_to_i64_ru.tv",
|
||||
"f128_to_i64_rd.tv",
|
||||
"f128_to_i64_rnm.tv"
|
||||
};
|
||||
|
||||
string f128rv32cvtint[] = '{
|
||||
"ui32_to_f128_rne.tv",
|
||||
"ui32_to_f128_rz.tv",
|
||||
"ui32_to_f128_ru.tv",
|
||||
"ui32_to_f128_rd.tv",
|
||||
"ui32_to_f128_rnm.tv",
|
||||
"i32_to_f128_rne.tv",
|
||||
"i32_to_f128_rz.tv",
|
||||
"i32_to_f128_ru.tv",
|
||||
"i32_to_f128_rd.tv",
|
||||
"i32_to_f128_rnm.tv",
|
||||
"f128_to_ui32_rne.tv",
|
||||
"f128_to_ui32_rz.tv",
|
||||
"f128_to_ui32_ru.tv",
|
||||
"f128_to_ui32_rd.tv",
|
||||
"f128_to_ui32_rnm.tv",
|
||||
"f128_to_i32_rne.tv",
|
||||
"f128_to_i32_rz.tv",
|
||||
"f128_to_i32_ru.tv",
|
||||
"f128_to_i32_rd.tv",
|
||||
"f128_to_i32_rnm.tv"
|
||||
};
|
||||
|
||||
|
||||
string f32f16cvt[] = '{
|
||||
"f32_to_f16_rne.tv",
|
||||
"f32_to_f16_rz.tv",
|
||||
"f32_to_f16_ru.tv",
|
||||
"f32_to_f16_rd.tv",
|
||||
"f32_to_f16_rnm.tv",
|
||||
"f16_to_f32_rne.tv",
|
||||
"f16_to_f32_rz.tv",
|
||||
"f16_to_f32_ru.tv",
|
||||
"f16_to_f32_rd.tv",
|
||||
"f16_to_f32_rnm.tv"
|
||||
};
|
||||
|
||||
string f64f16cvt[] = '{
|
||||
"f64_to_f16_rne.tv",
|
||||
"f64_to_f16_rz.tv",
|
||||
"f64_to_f16_ru.tv",
|
||||
"f64_to_f16_rd.tv",
|
||||
"f64_to_f16_rnm.tv",
|
||||
"f16_to_f64_rne.tv",
|
||||
"f16_to_f64_rz.tv",
|
||||
"f16_to_f64_ru.tv",
|
||||
"f16_to_f64_rd.tv",
|
||||
"f16_to_f64_rnm.tv"
|
||||
};
|
||||
|
||||
string f128f16cvt[] = '{
|
||||
"f128_to_f16_rne.tv",
|
||||
"f128_to_f16_rz.tv",
|
||||
"f128_to_f16_ru.tv",
|
||||
"f128_to_f16_rd.tv",
|
||||
"f128_to_f16_rnm.tv",
|
||||
"f16_to_f128_rne.tv",
|
||||
"f16_to_f128_rz.tv",
|
||||
"f16_to_f128_ru.tv",
|
||||
"f16_to_f128_rd.tv",
|
||||
"f16_to_f128_rnm.tv"
|
||||
};
|
||||
|
||||
string f64f32cvt[] = '{
|
||||
"f64_to_f32_rne.tv",
|
||||
"f64_to_f32_rz.tv",
|
||||
"f64_to_f32_ru.tv",
|
||||
"f64_to_f32_rd.tv",
|
||||
"f64_to_f32_rnm.tv",
|
||||
"f32_to_f64_rne.tv",
|
||||
"f32_to_f64_rz.tv",
|
||||
"f32_to_f64_ru.tv",
|
||||
"f32_to_f64_rd.tv",
|
||||
"f32_to_f64_rnm.tv"
|
||||
};
|
||||
|
||||
|
||||
string f128f32cvt[] = '{
|
||||
"f128_to_f32_rne.tv",
|
||||
"f128_to_f32_rz.tv",
|
||||
"f128_to_f32_ru.tv",
|
||||
"f128_to_f32_rd.tv",
|
||||
"f128_to_f32_rnm.tv",
|
||||
"f32_to_f128_rne.tv",
|
||||
"f32_to_f128_rz.tv",
|
||||
"f32_to_f128_ru.tv",
|
||||
"f32_to_f128_rd.tv",
|
||||
"f32_to_f128_rnm.tv"
|
||||
};
|
||||
|
||||
|
||||
string f128f64cvt[] = '{
|
||||
"f64_to_f128_rne.tv",
|
||||
"f64_to_f128_rz.tv",
|
||||
"f64_to_f128_ru.tv",
|
||||
"f64_to_f128_rd.tv",
|
||||
"f64_to_f128_rnm.tv",
|
||||
"f128_to_f64_rne.tv",
|
||||
"f128_to_f64_rz.tv",
|
||||
"f128_to_f64_ru.tv",
|
||||
"f128_to_f64_rd.tv",
|
||||
"f128_to_f64_rnm.tv"
|
||||
};
|
||||
|
||||
string f16add[] = '{
|
||||
"f16_add_rne.tv",
|
||||
"f16_add_rz.tv",
|
||||
"f16_add_ru.tv",
|
||||
"f16_add_rd.tv",
|
||||
"f16_add_rnm.tv"
|
||||
};
|
||||
|
||||
string f32add[] = '{
|
||||
"f32_add_rne.tv",
|
||||
"f32_add_rz.tv",
|
||||
"f32_add_ru.tv",
|
||||
"f32_add_rd.tv",
|
||||
"f32_add_rnm.tv"
|
||||
};
|
||||
|
||||
string f64add[] = '{
|
||||
"f64_add_rne.tv",
|
||||
"f64_add_rz.tv",
|
||||
"f64_add_ru.tv",
|
||||
"f64_add_rd.tv",
|
||||
"f64_add_rnm.tv"
|
||||
};
|
||||
|
||||
string f128add[] = '{
|
||||
"f128_add_rne.tv",
|
||||
"f128_add_rz.tv",
|
||||
"f128_add_ru.tv",
|
||||
"f128_add_rd.tv",
|
||||
"f128_add_rnm.tv"
|
||||
};
|
||||
|
||||
string f16sub[] = '{
|
||||
"f16_sub_rne.tv",
|
||||
"f16_sub_rz.tv",
|
||||
"f16_sub_ru.tv",
|
||||
"f16_sub_rd.tv",
|
||||
"f16_sub_rnm.tv"
|
||||
};
|
||||
|
||||
string f32sub[] = '{
|
||||
"f32_sub_rne.tv",
|
||||
"f32_sub_rz.tv",
|
||||
"f32_sub_ru.tv",
|
||||
"f32_sub_rd.tv",
|
||||
"f32_sub_rnm.tv"
|
||||
};
|
||||
|
||||
string f64sub[] = '{
|
||||
"f64_sub_rne.tv",
|
||||
"f64_sub_rz.tv",
|
||||
"f64_sub_ru.tv",
|
||||
"f64_sub_rd.tv",
|
||||
"f64_sub_rnm.tv"
|
||||
};
|
||||
|
||||
string f128sub[] = '{
|
||||
"f128_sub_rne.tv",
|
||||
"f128_sub_rz.tv",
|
||||
"f128_sub_ru.tv",
|
||||
"f128_sub_rd.tv",
|
||||
"f128_sub_rnm.tv"
|
||||
};
|
||||
|
||||
string f16mul[] = '{
|
||||
"f16_mul_rne.tv",
|
||||
"f16_mul_rz.tv",
|
||||
"f16_mul_ru.tv",
|
||||
"f16_mul_rd.tv",
|
||||
"f16_mul_rnm.tv"
|
||||
};
|
||||
|
||||
string f32mul[] = '{
|
||||
"f32_mul_rne.tv",
|
||||
"f32_mul_rz.tv",
|
||||
"f32_mul_ru.tv",
|
||||
"f32_mul_rd.tv",
|
||||
"f32_mul_rnm.tv"
|
||||
};
|
||||
|
||||
string f64mul[] = '{
|
||||
"f64_mul_rne.tv",
|
||||
"f64_mul_rz.tv",
|
||||
"f64_mul_ru.tv",
|
||||
"f64_mul_rd.tv",
|
||||
"f64_mul_rnm.tv"
|
||||
};
|
||||
|
||||
string f128mul[] = '{
|
||||
"f128_mul_rne.tv",
|
||||
"f128_mul_rz.tv",
|
||||
"f128_mul_ru.tv",
|
||||
"f128_mul_rd.tv",
|
||||
"f128_mul_rnm.tv"
|
||||
};
|
||||
|
||||
string f16div[] = '{
|
||||
"f16_div_rne.tv",
|
||||
"f16_div_rz.tv",
|
||||
"f16_div_ru.tv",
|
||||
"f16_div_rd.tv",
|
||||
"f16_div_rnm.tv"
|
||||
};
|
||||
|
||||
string f32div[] = '{
|
||||
"f32_div_rne.tv",
|
||||
"f32_div_rz.tv",
|
||||
"f32_div_ru.tv",
|
||||
"f32_div_rd.tv",
|
||||
"f32_div_rnm.tv"
|
||||
};
|
||||
|
||||
string f64div[] = '{
|
||||
"f64_div_rne.tv",
|
||||
"f64_div_rz.tv",
|
||||
"f64_div_ru.tv",
|
||||
"f64_div_rd.tv",
|
||||
"f64_div_rnm.tv"
|
||||
};
|
||||
|
||||
string f128div[] = '{
|
||||
"f128_div_rne.tv",
|
||||
"f128_div_rz.tv",
|
||||
"f128_div_ru.tv",
|
||||
"f128_div_rd.tv",
|
||||
"f128_div_rnm.tv"
|
||||
};
|
||||
|
||||
string f16sqrt[] = '{
|
||||
"f16_sqrt_rne.tv",
|
||||
"f16_sqrt_rz.tv",
|
||||
"f16_sqrt_ru.tv",
|
||||
"f16_sqrt_rd.tv",
|
||||
"f16_sqrt_rnm.tv"
|
||||
};
|
||||
|
||||
string f32sqrt[] = '{
|
||||
"f32_sqrt_rne.tv",
|
||||
"f32_sqrt_rz.tv",
|
||||
"f32_sqrt_ru.tv",
|
||||
"f32_sqrt_rd.tv",
|
||||
"f32_sqrt_rnm.tv"
|
||||
};
|
||||
|
||||
string f64sqrt[] = '{
|
||||
"f64_sqrt_rne.tv",
|
||||
"f64_sqrt_rz.tv",
|
||||
"f64_sqrt_ru.tv",
|
||||
"f64_sqrt_rd.tv",
|
||||
"f64_sqrt_rnm.tv"
|
||||
};
|
||||
|
||||
string f128sqrt[] = '{
|
||||
"f128_sqrt_rne.tv",
|
||||
"f128_sqrt_rz.tv",
|
||||
"f128_sqrt_ru.tv",
|
||||
"f128_sqrt_rd.tv",
|
||||
"f128_sqrt_rnm.tv"
|
||||
};
|
||||
|
||||
string f16cmp[] = '{
|
||||
"f16_eq_rne.tv",
|
||||
"f16_eq_rz.tv",
|
||||
"f16_eq_ru.tv",
|
||||
"f16_eq_rd.tv",
|
||||
"f16_eq_rnm.tv",
|
||||
"f16_le_rne.tv",
|
||||
"f16_le_rz.tv",
|
||||
"f16_le_ru.tv",
|
||||
"f16_le_rd.tv",
|
||||
"f16_le_rnm.tv",
|
||||
"f16_lt_rne.tv",
|
||||
"f16_lt_rz.tv",
|
||||
"f16_lt_ru.tv",
|
||||
"f16_lt_rd.tv",
|
||||
"f16_lt_rnm.tv"
|
||||
};
|
||||
|
||||
string f32cmp[] = '{
|
||||
"f32_eq_rne.tv",
|
||||
"f32_eq_rz.tv",
|
||||
"f32_eq_ru.tv",
|
||||
"f32_eq_rd.tv",
|
||||
"f32_eq_rnm.tv",
|
||||
"f32_le_rne.tv",
|
||||
"f32_le_rz.tv",
|
||||
"f32_le_ru.tv",
|
||||
"f32_le_rd.tv",
|
||||
"f32_le_rnm.tv",
|
||||
"f32_lt_rne.tv",
|
||||
"f32_lt_rz.tv",
|
||||
"f32_lt_ru.tv",
|
||||
"f32_lt_rd.tv",
|
||||
"f32_lt_rnm.tv"
|
||||
};
|
||||
|
||||
string f64cmp[] = '{
|
||||
"f64_eq_rne.tv",
|
||||
"f64_eq_rz.tv",
|
||||
"f64_eq_ru.tv",
|
||||
"f64_eq_rd.tv",
|
||||
"f64_eq_rnm.tv",
|
||||
"f64_le_rne.tv",
|
||||
"f64_le_rz.tv",
|
||||
"f64_le_ru.tv",
|
||||
"f64_le_rd.tv",
|
||||
"f64_le_rnm.tv",
|
||||
"f64_lt_rne.tv",
|
||||
"f64_lt_rz.tv",
|
||||
"f64_lt_ru.tv",
|
||||
"f64_lt_rd.tv",
|
||||
"f64_lt_rnm.tv"
|
||||
};
|
||||
|
||||
string f128cmp[] = '{
|
||||
"f128_eq_rne.tv",
|
||||
"f128_eq_rz.tv",
|
||||
"f128_eq_ru.tv",
|
||||
"f128_eq_rd.tv",
|
||||
"f128_eq_rnm.tv",
|
||||
"f128_le_rne.tv",
|
||||
"f128_le_rz.tv",
|
||||
"f128_le_ru.tv",
|
||||
"f128_le_rd.tv",
|
||||
"f128_le_rnm.tv",
|
||||
"f128_lt_rne.tv",
|
||||
"f128_lt_rz.tv",
|
||||
"f128_lt_ru.tv",
|
||||
"f128_lt_rd.tv",
|
||||
"f128_lt_rnm.tv"
|
||||
};
|
||||
|
||||
string f16fma[] = '{
|
||||
"f16_mulAdd_rne.tv",
|
||||
"f16_mulAdd_rz.tv",
|
||||
"f16_mulAdd_ru.tv",
|
||||
"f16_mulAdd_rd.tv",
|
||||
"f16_mulAdd_rnm.tv"
|
||||
};
|
||||
|
||||
string f32fma[] = '{
|
||||
"f32_mulAdd_rne.tv",
|
||||
"f32_mulAdd_rz.tv",
|
||||
"f32_mulAdd_ru.tv",
|
||||
"f32_mulAdd_rd.tv",
|
||||
"f32_mulAdd_rnm.tv"
|
||||
};
|
||||
|
||||
string f64fma[] = '{
|
||||
"f64_mulAdd_rne.tv",
|
||||
"f64_mulAdd_rz.tv",
|
||||
"f64_mulAdd_ru.tv",
|
||||
"f64_mulAdd_rd.tv",
|
||||
"f64_mulAdd_rnm.tv"
|
||||
};
|
||||
|
||||
string f128fma[] = '{
|
||||
"f128_mulAdd_rne.tv",
|
||||
"f128_mulAdd_rz.tv",
|
||||
"f128_mulAdd_ru.tv",
|
||||
"f128_mulAdd_rd.tv",
|
||||
"f128_mulAdd_rnm.tv"
|
||||
};
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user