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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main

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This commit is contained in:
DTowersM 2022-06-07 06:03:19 +00:00
commit df330961b8
101 changed files with 4455 additions and 118958 deletions
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2
.gitignore vendored
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@ -68,6 +68,8 @@ synthDC/alib-52
synthDC/*.log
synthDC/*.svf
synthDC/runs/
synthDC/plots/
synthDC/runArchive
synthDC/hdl
/pipelined/regression/power.saif
tests/fp/vectors/*.tv

2
addins/riscv-arch-test

@ -1 +1 @@
Subproject commit be67c99bd461742aa1c100bcc0732657faae2230
Subproject commit 307c77b26e070ae85ffea665ad9b642b40e33c86

11
fpga/constraints/debug2.xdc
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@ -327,7 +327,7 @@ connect_debug_port u_ila_0/probe72 [get_nets [list wallypipelinedsoc/core/hzu/BP
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe73]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe73]
connect_debug_port u_ila_0/probe73 [get_nets [list wallypipelinedsoc/core/hzu/CSRWritePendingDEM ]]
connect_debug_port u_ila_0/probe73 [get_nets [list wallypipelinedsoc/core/hzu/CSRWriteFencePendingDEM ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe74]
@ -402,7 +402,7 @@ connect_debug_port u_ila_0/probe87 [get_nets [list wallypipelinedsoc/core/hzu/Br
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe88]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe88]
connect_debug_port u_ila_0/probe88 [get_nets [list wallypipelinedsoc/core/hzu/InvalidateICacheM ]]
connect_debug_port u_ila_0/probe88 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/RXerrIP} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe89]
@ -433,7 +433,8 @@ connect_debug_port u_ila_0/probe93 [get_nets [list wallypipelinedsoc/core/hzu/St
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe94]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe94]
connect_debug_port u_ila_0/probe94 [get_nets [list wallypipelinedsoc/core/hzu/FlushF ]]
connect_debug_port u_ila_0/probe94 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/RXerrIP} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe95]
@ -835,8 +836,4 @@ set_property port_width 4 [get_debug_ports u_ila_0/probe171]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe171]
connect_debug_port u_ila_0/probe171 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/rxfifotail[0]} {wallypipelinedsoc/uncore/uart.uart/u/rxfifotail[1]} {wallypipelinedsoc/uncore/uart.uart/u/rxfifotail[2]} {wallypipelinedsoc/uncore/uart.uart/u/rxfifotail[3]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe172]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe172]
connect_debug_port u_ila_0/probe172 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/RXerrIP} ]]

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pipelined/config/buildroot/BTBPredictor.txt
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pipelined/config/buildroot/twoBitPredictor.txt
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pipelined/config/fpga/BTBPredictor.txt
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pipelined/config/fpga/twoBitPredictor.txt
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pipelined/config/rv32e/BTBPredictor.txt
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pipelined/config/rv32e/twoBitPredictor.txt
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pipelined/config/rv32gc/BTBPredictor.txt
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pipelined/config/rv32gc/twoBitPredictor.txt
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pipelined/config/rv32i/BTBPredictor.txt
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pipelined/config/rv32i/twoBitPredictor.txt
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pipelined/config/rv32ic/BTBPredictor.txt
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pipelined/config/rv32ic/twoBitPredictor.txt
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pipelined/config/rv64BP/BTBPredictor.txt
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pipelined/config/rv64BP/twoBitPredictor.txt
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pipelined/config/rv64fp/BTBPredictor.txt
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pipelined/config/rv64fp/twoBitPredictor.txt
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23
pipelined/config/rv64fp/wally-config.vh
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@ -35,16 +35,16 @@
`define XLEN 64
// IEEE 754 compliance
`define IEEE754 1
`define IEEE754 0
// MISA RISC-V configuration per specification
//16 - quad 3 - double 5 - single
`define MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 )
// ZYXWVUTSRQPONMLKJIHGFEDCBA
`define MISA 32'b0000000000101000001000100101101
`define ZICSR_SUPPORTED 1
`define ZIFENCEI_SUPPORTED 1
`define COUNTERS 32
`define ZICOUNTERS_SUPPORTED 1
`define ZFH_SUPPORTED 1
`define ZFH_SUPPORTED 0
/// Microarchitectural Features
`define UARCH_PIPELINED 1
@ -52,9 +52,11 @@
`define UARCH_SINGLECYCLE 0
`define DMEM `MEM_CACHE
`define IMEM `MEM_CACHE
`define DBUS 1
`define IBUS 1
`define VIRTMEM_SUPPORTED 1
`define VECTORED_INTERRUPTS_SUPPORTED 1
`define BIGENDIAN_SUPPORTED 0
`define BIGENDIAN_SUPPORTED 1
// TLB configuration. Entries should be a power of 2
`define ITLB_ENTRIES 32
@ -82,13 +84,13 @@
// Bus Interface width
`define AHBW 64
// WFI Timeout Wait
`define WFI_TIMEOUT_BIT 16
// Peripheral Physiccal Addresses
// Peripheral memory space extends from BASE to BASE+RANGE
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
// WFI Timeout Wait
`define WFI_TIMEOUT_BIT 16
// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
`define BOOTROM_SUPPORTED 1'b1
`define BOOTROM_BASE 56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
@ -130,13 +132,12 @@
`define PLIC_GPIO_ID 3
`define PLIC_UART_ID 10
`define TWO_BIT_PRELOAD "../config/rv64ic/twoBitPredictor.txt"
`define BTB_PRELOAD "../config/rv64ic/BTBPredictor.txt"
`define TWO_BIT_PRELOAD "../config/shared/twoBitPredictor.txt"
`define BTB_PRELOAD "../config/shared/BTBPredictor.txt"
`define BPRED_ENABLED 1
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
`define TESTSBP 0
`define BPRED_SIZE 10
`define REPLAY 0
`define HPTW_WRITES_SUPPORTED 0

109
synthDC/nm_500_MHz_2022-03-22-20-43_2947df5b/wally-config.vh → pipelined/config/rv64fpquad/wally-config.vh
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@ -32,33 +32,34 @@
`define DESIGN_COMPILER 0
// RV32 or RV64: XLEN = 32 or 64
`define XLEN 32
`define XLEN 64
// IEEE 754 compliance
`define IEEE754 0
// E
`define MISA (32'h00000010)
`define ZICSR_SUPPORTED 0
`define ZIFENCEI_SUPPORTED 0
`define COUNTERS 0
`define ZICOUNTERS_SUPPORTED 0
// MISA RISC-V configuration per specification
`define MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 )
`define ZICSR_SUPPORTED 1
`define ZIFENCEI_SUPPORTED 1
`define COUNTERS 32
`define ZICOUNTERS_SUPPORTED 1
`define ZFH_SUPPORTED 1
// Microarchitectural Features
/// Microarchitectural Features
`define UARCH_PIPELINED 1
`define UARCH_SUPERSCALR 0
`define UARCH_SINGLECYCLE 0
// *** replace with MEM_BUS
`define DMEM `MEM_NONE
`define IMEM `MEM_NONE
`define DMEM `MEM_CACHE
`define IMEM `MEM_CACHE
`define DBUS 1
`define IBUS 1
`define VIRTMEM_SUPPORTED 0
`define VECTORED_INTERRUPTS_SUPPORTED 0
`define VIRTMEM_SUPPORTED 1
`define VECTORED_INTERRUPTS_SUPPORTED 1
`define BIGENDIAN_SUPPORTED 1
// TLB configuration. Entries should be a power of 2
`define ITLB_ENTRIES 0
`define DTLB_ENTRIES 0
`define ITLB_ENTRIES 32
`define DTLB_ENTRIES 32
// Cache configuration. Sizes should be a power of two
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
@ -71,44 +72,49 @@
// Integer Divider Configuration
// DIV_BITSPERCYCLE must be 1, 2, or 4
`define DIV_BITSPERCYCLE 1
`define DIV_BITSPERCYCLE 4
// Legal number of PMP entries are 0, 16, or 64
`define PMP_ENTRIES 0
`define PMP_ENTRIES 64
// Address space
`define RESET_VECTOR 32'h80000000
// Peripheral Addresses
// Peripheral memory space extends from BASE to BASE+RANGE
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
`define BOOTROM_SUPPORTED 1'b1
`define BOOTROM_BASE 34'h00001000
`define BOOTROM_RANGE 34'h00000FFF
`define RAM_SUPPORTED 1'b1
`define RAM_BASE 34'h80000000
`define RAM_RANGE 34'h07FFFFFF
`define EXT_MEM_SUPPORTED 1'b0
`define EXT_MEM_BASE 34'h80000000
`define EXT_MEM_RANGE 34'h07FFFFFF
`define CLINT_SUPPORTED 1'b0
`define CLINT_BASE 34'h02000000
`define CLINT_RANGE 34'h0000FFFF
`define GPIO_SUPPORTED 1'b0
`define GPIO_BASE 34'h10060000
`define GPIO_RANGE 34'h000000FF
`define UART_SUPPORTED 1'b0
`define UART_BASE 34'h10000000
`define UART_RANGE 34'h00000007
`define PLIC_SUPPORTED 1'b0
`define PLIC_BASE 34'h0C000000
`define PLIC_RANGE 34'h03FFFFFF
`define SDC_SUPPORTED 1'b0
`define SDC_BASE 34'h00012100
`define SDC_RANGE 34'h0000001F
`define RESET_VECTOR 64'h0000000080000000
// Bus Interface width
`define AHBW 32
`define AHBW 64
// WFI Timeout Wait
`define WFI_TIMEOUT_BIT 16
// Peripheral Physiccal Addresses
// Peripheral memory space extends from BASE to BASE+RANGE
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
`define BOOTROM_SUPPORTED 1'b1
`define BOOTROM_BASE 56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
`define BOOTROM_RANGE 56'h00000FFF
`define RAM_SUPPORTED 1'b1
`define RAM_BASE 56'h80000000
`define RAM_RANGE 56'h7FFFFFFF
`define EXT_MEM_SUPPORTED 1'b0
`define EXT_MEM_BASE 56'h80000000
`define EXT_MEM_RANGE 56'h07FFFFFF
`define CLINT_SUPPORTED 1'b1
`define CLINT_BASE 56'h02000000
`define CLINT_RANGE 56'h0000FFFF
`define GPIO_SUPPORTED 1'b1
`define GPIO_BASE 56'h10060000
`define GPIO_RANGE 56'h000000FF
`define UART_SUPPORTED 1'b1
`define UART_BASE 56'h10000000
`define UART_RANGE 56'h00000007
`define PLIC_SUPPORTED 1'b1
`define PLIC_BASE 56'h0C000000
`define PLIC_RANGE 56'h03FFFFFF
`define SDC_SUPPORTED 1'b0
`define SDC_BASE 56'h00012100
`define SDC_RANGE 56'h0000001F
// Test modes
@ -119,17 +125,18 @@
`define UART_PRESCALE 1
// Interrupt configuration
`define PLIC_NUM_SRC 10
`define PLIC_NUM_SRC 10
// comment out the following if >=32 sources
`define PLIC_NUM_SRC_LT_32
`define PLIC_GPIO_ID 3
`define PLIC_UART_ID 10
`define TWO_BIT_PRELOAD "../config/rv32ic/twoBitPredictor.txt"
`define BTB_PRELOAD "../config/rv32ic/BTBPredictor.txt"
`define BPRED_ENABLED 0
`define TWO_BIT_PRELOAD "../config/shared/twoBitPredictor.txt"
`define BTB_PRELOAD "../config/shared/BTBPredictor.txt"
`define BPRED_ENABLED 1
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
`define TESTSBP 0
`define BPRED_SIZE 10
`define REPLAY 0
`define HPTW_WRITES_SUPPORTED 0

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pipelined/config/rv64gc/twoBitPredictor.txt
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pipelined/config/rv64i/BTBPredictor.txt
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pipelined/config/rv64i/twoBitPredictor.txt
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pipelined/config/rv64ic/BTBPredictor.txt
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pipelined/config/rv64ic/twoBitPredictor.txt
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pipelined/config/shared/wally-shared.vh
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@ -51,42 +51,45 @@
`define PMPCFG_ENTRIES (`PMP_ENTRIES/8)
// Floating point constants for Quad, Double, Single, and Half precisions
`define Q_LEN 128
`define Q_NE 15
`define Q_NF 112
`define Q_BIAS 16383
`define D_LEN 64
`define D_NE 11
`define D_NF 52
`define D_BIAS 1023
`define S_LEN 32
`define S_NE 8
`define S_NF 23
`define S_BIAS 127
`define H_LEN 16
`define H_NE 5
`define H_NF 10
`define H_BIAS 15
`define Q_LEN 32'd128
`define Q_NE 32'd15
`define Q_NF 32'd112
`define Q_BIAS 32'd16383
`define D_LEN 32'd64
`define D_NE 32'd11
`define D_NF 32'd52
`define D_BIAS 32'd1023
`define D_FMT 32'd1
`define S_LEN 32'd32
`define S_NE 32'd8
`define S_NF 32'd23
`define S_BIAS 32'd127
`define S_FMT 32'd1
`define H_LEN 32'd16
`define H_NE 32'd5
`define H_NF 32'd10
`define H_BIAS 32'd15
// Floating point length FLEN and number of exponent (NE) and fraction (NF) bits
`define FLEN (`Q_SUPPORTED ? `Q_LEN : `D_SUPPORTED ? `D_LEN : `F_SUPPORTED ? `S_LEN : `H_LEN)
`define NE (`Q_SUPPORTED ? `Q_NE : `D_SUPPORTED ? `D_NE : `F_SUPPORTED ? `S_NE : `H_NE)
`define NF (`Q_SUPPORTED ? `Q_NF : `D_SUPPORTED ? `D_NF : `F_SUPPORTED ? `S_NF : `H_NF)
`define FMT (`Q_SUPPORTED ? 3 : `D_SUPPORTED ? 1 : `F_SUPPORTED ? 0 : 2)
`define FMT (`Q_SUPPORTED ? 2'd3 : `D_SUPPORTED ? 2'd1 : `F_SUPPORTED ? 2'd0 : 2'd2)
`define BIAS (`Q_SUPPORTED ? `Q_BIAS : `D_SUPPORTED ? `D_BIAS : `F_SUPPORTED ? `S_BIAS : `H_BIAS)
// Floating point constants needed for FPU paramerterization
`define FPSIZES (`Q_SUPPORTED+`D_SUPPORTED+`F_SUPPORTED+`ZFH_SUPPORTED)
`define LEN1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_LEN : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_LEN : `H_LEN)
`define NE1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NE : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NE : `H_NE)
`define NF1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NF : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NF : `H_NF)
`define FMT1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? 1 : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? 0 : 2)
`define BIAS1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_BIAS : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_BIAS : `H_BIAS)
`define LEN2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_LEN : `H_LEN)
`define FPSIZES ((32)'(`Q_SUPPORTED)+(32)'(`D_SUPPORTED)+(32)'(`F_SUPPORTED)+(32)'(`ZFH_SUPPORTED))
`define FMTBITS ((`FPSIZES>=3)+1)
`define LEN1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_LEN : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_LEN : `H_LEN)
`define NE1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NE : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NE : `H_NE)
`define NF1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NF : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NF : `H_NF)
`define FMT1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? 2'd1 : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? 2'd0 : 2'd2)
`define BIAS1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_BIAS : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_BIAS : `H_BIAS)
`define LEN2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_LEN : `H_LEN)
`define NE2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NE : `H_NE)
`define NF2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NF : `H_NF)
`define FMT2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? 0 : 2)
`define BIAS2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_BIAS : `H_BIAS)
`define NF2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NF : `H_NF)
`define FMT2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? 2'd0 : 2'd2)
`define BIAS2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_BIAS : `H_BIAS)
// Disable spurious Verilator warnings

2
pipelined/regression/lint-wally
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@ -5,7 +5,7 @@ export PATH=$PATH:/usr/local/bin/
verilator=`which verilator`
basepath=$(dirname $0)/..
for config in rv32e rv64gc rv32gc rv32ic ; do
for config in rv64fp rv64fpquad rv32e rv64gc rv32gc rv32ic; do
echo "$config linting..."
if !($verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes); then
echo "Exiting after $config lint due to errors or warnings"

1
pipelined/regression/sim-fp64
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@ -1 +0,0 @@
vsim -do wally-fp64.do

3
pipelined/regression/sim-fp64-batch
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@ -1,3 +0,0 @@
vsim -c <<!
do wally-fp64-batch.do rv64gc imperas64d
!

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pipelined/regression/sim-fp → pipelined/regression/sim-testfloat
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@ -3,9 +3,10 @@
# cvtfp - test floating-point conversion unit (fcvtfp)
# cmp - test comparison unit's LT, LE, EQ opperations (fcmp)
# add - test addition
# fma - test fma
# sub - test subtraction
# div - test division
# sqrt - test square ro
# all - test everything
vsim -do "do fp.do rv64fp cmp"
vsim -do "do testfloat.do rv64fpquad cmp"

2
pipelined/regression/sim-fp-batch → pipelined/regression/sim-testfloat-batch
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@ -7,4 +7,4 @@
# sqrt - test square root
# all - test everything
vsim -c -do "do fp.do rv64fp cvtfp"
vsim -c -do "do testfloat.do rv64fpquad all"

2
pipelined/regression/sim-wally
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@ -1,2 +1,2 @@
vsim -do "do wally-pipelined.do rv64gc imperas64d"
vsim -do "do wally-pipelined.do rv32gc arch32f"

0
pipelined/regression/fp.do → pipelined/regression/testfloat.do
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50
pipelined/regression/wally-fp64-batch.do
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@ -1,50 +0,0 @@
# wally-pipelined-batch.do
#
# Modification by Oklahoma State University & Harvey Mudd College
# Use with Testbench
# James Stine, 2008; David Harris 2021
# Go Cowboys!!!!!!
#
# Takes 1:10 to run RV64IC tests using gui
# Usage: do wally-pipelined-batch.do <config> <testcases>
# Example: do wally-pipelined-batch.do rv32ic imperas-32i
# Use this wally-pipelined-batch.do file to run this example.
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
# do wally-pipelined-batch.do
# or, to run from a shell, type the following at the shell prompt:
# vsim -do wally-pipelined-batch.do -c
# (omit the "-c" to see the GUI while running from the shell)
onbreak {resume}
# create library
if [file exists work_${1}_${2}] {
vdel -lib work_${1}_${2} -all
}
vlib work_${1}_${2}
# compile source files
# suppress spurious warnngs about
# "Extra checking for conflicts with always_comb done at vopt time"
# because vsim will run vopt
# default to config/rv64ic, but allow this to be overridden at the command line. For example:
# do wally-pipelined-batch.do ../config/rv32ic rv32ic
vlog -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-f64.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583
# start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
vopt work_${1}_${2}.testbench -work work_${1}_${2} -G TEST=$2 -o testbenchopt
vsim -lib work_${1}_${2} testbenchopt
# Adding coverage increases runtime from 2:00 to 4:29. Can't run it all the time
#vopt work_$2.testbench -work work_$2 -o workopt_$2 +cover=sbectf
#vsim -coverage -lib work_$2 workopt_$2
run -all
#coverage report -file wally-pipelined-coverage.txt
# These aren't doing anything helpful
#coverage report -memory
#profile report -calltree -file wally-pipelined-calltree.rpt -cutoff 2
quit

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pipelined/regression/wally-fp64.do
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@ -1,54 +0,0 @@
# wally-pipelined.do
#
# Modification by Oklahoma State University & Harvey Mudd College
# Use with Testbench
# James Stine, 2008; David Harris 2021
# Go Cowboys!!!!!!
#
# Takes 1:10 to run RV64IC tests using gui
# run with vsim -do "do wally-pipelined.do rv64ic riscvarchtest-64m"
# Use this wally-pipelined.do file to run this example.
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
# do wally-pipelined.do
# or, to run from a shell, type the following at the shell prompt:
# vsim -do wally-pipelined.do -c
# (omit the "-c" to see the GUI while running from the shell)
onbreak {resume}
# create library
if [file exists work] {
vdel -all
}
vlib work
# compile source files
# suppress spurious warnngs about
# "Extra checking for conflicts with always_comb done at vopt time"
# because vsim will run vopt
# default to config/rv64ic, but allow this to be overridden at the command line. For example:
# do wally-pipelined.do ../config/rv32ic
#switch $argc {
# 0 {vlog +incdir+../config/rv64ic +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
# 1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
#}
# start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
vlog +incdir+../config/rv64gc +incdir+../config/shared ../testbench/testbench-f64.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583
vopt +acc work.testbench -G TEST=imperas64d -o workopt
vsim workopt
view wave
-- display input and output signals as hexidecimal values
do ./wave-dos/generic.do
-- Run the Simulation
#run 3600
run -all
#quit
#noview ../testbench/testbench-imperas.sv
noview ../testbench/testbench.sv
view wave

2
pipelined/regression/wally-pipelined-batch.do
View File

@ -35,7 +35,7 @@ vlib wkdir/work_${1}_${2}
if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
# start and run simulation
vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -G DEBUG_TRACE=1 -o testbenchopt
vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -o testbenchopt
vsim -lib wkdir/work_${1}_${2} testbenchopt -suppress 8852,12070,3084
run -all

8
pipelined/regression/wally-pipelined.do
View File

@ -34,7 +34,7 @@ vlib work
if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
# start and run simulation
vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -G DEBUG_TRACE=1 -o testbenchopt
vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -G NO_SPOOFING=0 -o testbenchopt
vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829
#-- Run the Simulation
@ -48,11 +48,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
} elseif {$2 eq "buildroot-no-trace"} {
vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
# start and run simulation
<<<<<<< HEAD
vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=0 -G INSTR_WAVEON=0 -G CHECKPOINT=0 -G NO_IE_MTIME_CHECKPOINT=1 -G DEBUG_TRACE=0 -o testbenchopt
=======
vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=0 -G INSTR_WAVEON=0 -G CHECKPOINT=0 -G NO_IE_MTIME_CHECKPOINT=1 -o testbenchopt
>>>>>>> parent of 9eb374b6... Changed NO_IE_MTIME_CHECKPOINT so it uses the new parameter name
vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=0 -G INSTR_WAVEON=0 -G CHECKPOINT=0 -G NO_SPOOFING=1 -o testbenchopt
vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829
#-- Run the Simulation

23
pipelined/src/fma/Makefile
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@ -1,23 +0,0 @@
# Makefile
CC = gcc
CFLAGS = -O3
LIBS = -lm
LFLAGS = -L.
# Link against the riscv-isa-sim version of SoftFloat rather than
# the regular version to get RISC-V NaN behavior
IFLAGS = -I$(RISCV)/riscv-isa-sim/softfloat
LIBS = $(RISCV)/riscv-isa-sim/build/libsoftfloat.a
#IFLAGS = -I../../../addins/SoftFloat-3e/source/include/
#LIBS = ../../../addins/SoftFloat-3e/build/Linux-x86_64-GCC/softfloat.a
SRCS = $(wildcard *.c)
PROGS = $(patsubst %.c,%,$(SRCS))
all: $(PROGS)
%: %.c
$(CC) $(CFLAGS) $(IFLAGS) $(LFLAGS) -o $@ $< $(LIBS)
clean:
rm -f $(PROGS)

4225
pipelined/src/fma/baby_torture.tv
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File diff suppressed because it is too large Load Diff

1057
pipelined/src/fma/baby_torture_rz.tv
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File diff suppressed because it is too large Load Diff

23
pipelined/src/fma/fma.do
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@ -1,23 +0,0 @@
# fma.do
#
# run with vsim -do "do fma.do"
# add -c before -do for batch simulation
onbreak {resume}
# create library
vlib worklib
vlog -lint -sv -work worklib fma16.v testbench.v
vopt +acc worklib.testbench_fma16 -work worklib -o testbenchopt
vsim -lib worklib testbenchopt
add wave sim:/testbench_fma16/clk
add wave sim:/testbench_fma16/reset
add wave sim:/testbench_fma16/x
add wave sim:/testbench_fma16/y
add wave sim:/testbench_fma16/z
add wave sim:/testbench_fma16/result
add wave sim:/testbench_fma16/rexpected
run -all

268
pipelined/src/fma/fma16.v
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@ -1,268 +0,0 @@
// fma16.sv
// David_Harris@hmc.edu 26 February 2022
// 16-bit floating-point multiply-accumulate
// Operation: general purpose multiply, add, fma, with optional negation
// If mul=1, p = x * y. Else p = x.
// If add=1, result = p + z. Else result = p.
// If negr or negz = 1, negate result or z to handle negations and subtractions
// fadd: mul = 0, add = 1, negr = negz = 0
// fsub: mul = 0, add = 1, negr = 0, negz = 1
// fmul: mul = 1, add = 0, negr = 0, negz = 0
// fmadd: mul = 1, add = 1, negr = 0, negz = 0
// fmsub: mul = 1, add = 1, negr = 0, negz = 1
// fnmadd: mul = 1, add = 1, negr = 1, negz = 0
// fnmsub: mul = 1, add = 1, negr = 1, negz = 1
`define FFLEN 16
`define Nf 10
`define Ne 5
`define BIAS 15
`define EMIN (-(2**(`Ne-1)-1))
`define EMAX (2**(`Ne-1)-1)
`define NaN 16'h7E00
`define INF 15'h7C00
// rounding modes *** update
`define RZ 3'b00
`define RNE 3'b01
`define RM 3'b10
`define RP 3'b11
module fma16(
input logic [`FFLEN-1:0] x, y, z,
input logic mul, add, negr, negz,
input logic [1:0] roundmode, // 00: rz, 01: rne, 10: rp, 11: rn
output logic [`FFLEN-1:0] result);
logic [`Nf:0] xm, ym, zm; // U1.Nf
logic [`Ne-1:0] xe, ye, ze; // B_Ne
logic xs, ys, zs;
logic zs1; // sign before optional negation
logic [2*`Nf+1:0] pm; // U2.2Nf
logic [`Ne:0] pe; // B_Ne+1
logic ps; // sign of product
logic [22:0] rm;
logic [`Ne+1:0] re;
logic rs;
logic xzero, yzero, zzero, xinf, yinf, zinf, xnan, ynan, znan;
logic [`Ne+1:0] re2;
unpack16 unpack(x, y, z, xm, ym, zm, xe, ye, ze, xs, ys, zs1, xzero, yzero, zzero, xinf, yinf, zinf, xnan, ynan, znan); // unpack inputs
//signadj16 signadj(negr, negz, xs, ys, zs1, ps, zs); // handle negations
mult16 mult16(mul, xm, ym, xe, ye, xs, ys, pm, pe, ps); // p = x * y
add16 add16(add, pm, zm, pe, ze, ps, zs, negz, rm, re, re2, rs); // r = z + p
postproc16 post(roundmode, xzero, yzero, zzero, xinf, yinf, zinf, xnan, ynan, znan, rm, zm, re, ze, rs, zs, ps, re2, result); // normalize, round, pack
endmodule
module mult16(
input logic mul,
input logic [`Nf:0] xm, ym,
input logic [`Ne-1:0] xe, ye,
input logic xs, ys,
output logic [2*`Nf+1:0] pm,
output logic [`Ne:0] pe,
output logic ps);
// only multiply if mul = 1
assign pm = mul ? xm * ym : {1'b0, xm, 10'b0}; // multiply mantiassas
assign pe = mul ? xe + ye - `BIAS : {1'b0, xe}; // add exponents, account for bias
assign ps = xs ^ ys; // negative if X xor Y are negative
endmodule
module add16(
input logic add,
input logic [2*`Nf+1:0] pm, // U2.2Nf
input logic [`Nf:0] zm, // U1.Nf
input logic [`Ne:0] pe, // B_Ne+1
input logic [`Ne-1:0] ze, // B_Ne
input logic ps, zs,
input logic negz,
output logic [22:0] rm,
output logic [`Ne+1:0] re, // B_Ne+2
output logic [`Ne+1:0] re2,
output logic rs);
logic [`Nf*3+7:0] paligned, zaligned, zalignedaddsub, r, r2, rnormed, rnormed2; // U(Nf+6).(2Nf+2) aligned significands
logic signed [`Ne:0] ExpDiff; // Q(Ne+2).0
logic [`Ne:0] AlignCnt; // U(Ne+3) bits to right shift Z for alignment *** check size.
logic [`Nf-1:0] prezsticky;
logic zsticky;
logic effectivesub;
logic rs0;
logic [`Ne:0] leadingzeros, NormCnt; // *** should paramterize size
logic [`Ne:0] re1;
// Alignment shift
assign paligned = {{(`Nf+4){1'b0}}, pm, 2'b00}; // constant shift to prepend leading and trailing 0s.
assign ExpDiff = pe - {1'b0, ze}; // Compute exponent difference as signed number
always_comb // AlignCount mux; see Muller page 254
if (ExpDiff <= (-2*`Nf - 1)) begin AlignCnt = 3*`Nf + 7; re = {1'b0, pe}; end
else if (ExpDiff <= 2) begin AlignCnt = `Nf + 4 - ExpDiff; re = {1'b0, pe}; end
else if (ExpDiff <= `Nf+3) begin AlignCnt = `Nf + 4 - ExpDiff; re = {2'b0, ze}; end
else begin AlignCnt = 0; re = {2'b0, ze}; end
// Shift Zm right by AlignCnt. Produce 3Nf+8 bits of Zaligned in U(Nf+6).(2Nf+2) and Nf bits becoming sticky
assign {zaligned, prezsticky} = {zm, {(3*`Nf+7){1'b0}}} >> AlignCnt; //Right shift
assign zsticky = |prezsticky; // Sticky bit if any of the discarded bits were 1
// Effective subtraction
assign effectivesub = ps ^ zs ^ negz; // subtract |z| from |p|
assign zalignedaddsub = effectivesub ? ~zaligned : zaligned; // invert zaligned for subtraction
// Adder
assign r = paligned + zalignedaddsub + {{`Nf*3+7{1'b0}}, effectivesub}; // add aligned significands
assign rs0 = r[`Nf*3+7]; // sign of the initial result
assign r2 = rs0 ? ~r+1 : r; // invert sum if negative; could optimize with end-around carry?
// Sign Logic
assign rs = ps ^ rs0; // flip the sign if necessary
// Leading zero counter
lzc lzc(r2, leadingzeros); // count number of leading zeros in 2Nf+5 lower digits of r2
assign re1 = pe +2 - leadingzeros; // *** declare, # of bits
// Normalization shift
always_comb // NormCount mux
if (ExpDiff < 3) begin
if (re1 >= `EMIN) begin NormCnt = `Nf + 3 + leadingzeros; re2 = {1'b0, re1}; end
else begin NormCnt = `Nf + 5 + pe - `EMIN; re2 = `EMIN; end
end else begin NormCnt = AlignCnt; re = {2'b00, ze}; end
assign rnormed = r2 << NormCnt; // *** update sticky
/* temporarily comment out to start synth
// One-bit secondary normalization
if (ExpDiff <= 2) begin rnormed2 = rnormed; re2 = re; end // no secondary normalization
else begin // *** handle sticky
if (rnormed[***]) begin rnormed2 = rnormed >> 1; re2 = re+1; end
else if (rnormed[***-1]) begin rnormed2 = rnormed; re2 = re; end
else begin rnormed2 = rnormed << 1; re2 = re-1; end
end
// round
assign l = rnormed2[***]; // least significant bit
assign r = rnormed2[***-1]; // rounding bit
assign s = ***; // sticky bit
always_comb
case (roundmode)
RZ: roundup = 0;
RP: roundup = ~rs & (r | s);
RM: roundup = rs & (r | s);
RNE: roundup = r & (s | l);
default: roundup = 0;
endcase
assign {re3, rrounded} = {re2, rnormed2[***]} + roundup; // increment if necessary
*/
// *** need to handle rounding to MAXNUM vs. INFINITY
// add or pass product through
/* assign rm = add ? arm : {1'b0, pm};
assign re = add ? are : {1'b0, pe};
assign rs = add ? ars : ps; */
endmodule
module lzc(
input logic [`Nf*3+7:0] r2,
output logic [`Ne:0] leadingzeros
);
endmodule
module postproc16(
input logic [1:0] roundmode,
input logic xzero, yzero, zzero, xinf, yinf, zinf, xnan, ynan, znan,
input logic [22:0] rm,
input logic [`Nf:0] zm, // U1.Nf
input logic [6:0] re,
input logic [`Ne-1:0] ze, // B_Ne
input logic rs, zs, ps,
input logic [`Ne+1:0] re2,
output logic [15:0] result);
logic [9:0] uf, uff;
logic [6:0] ue;
logic [6:0] ueb, uebiased;
logic invalid;
// Special cases
// *** not handling signaling NaN
// *** also add overflow/underflow/inexact
always_comb begin
if (xnan | ynan | znan) begin result = `NaN; invalid = 0; end // propagate NANs
else if ((xinf | yinf) & zinf & (ps ^ zs)) begin result = `NaN; invalid = 1; end // infinity - infinity
else if (xzero & yinf | xinf & yzero) begin result = `NaN; invalid = 1; end // zero times infinity
else if (xinf | yinf) begin result = {ps, `INF}; invalid = 0; end // X or Y
else if (zinf) begin result = {zs, `INF}; invalid = 0; end // infinite Z
else if (xzero | yzero) begin result = {zs, ze, zm[`Nf-1:0]}; invalid = 0; end
else if (re2 >= `EMAX) begin result = {rs, `INF}; invalid = 0; end
else begin result = {rs, re[`Ne-1:0], rm[`Nf-1:0]}; invalid = 0; end
end
always_comb
if (rm[21]) begin // normalization right shift by 1 and bump up exponent;
ue = re + 7'b1;
uf = rm[20:11];
end else begin // no normalization shift needed
ue = re;
uf = rm[19:10];
end
// overflow
always_comb begin
ueb = ue-7'd15;
if (ue >= 7'd46) begin // overflow
/* uebiased = 7'd30;
uff = 10'h3ff; */
end else begin
uebiased = ue-7'd15;
uff = uf;
end
end
assign result = {rs, uebiased[4:0], uff};
// add special case handling for zeros, NaN, Infinity
endmodule
module signadj16(
input logic negr, negz,
input logic xs, ys, zs1,
output logic ps, zs);
assign ps = xs ^ ys; // sign of product
assign zs = zs1 ^ negz; // sign of addend
endmodule
module unpack16(
input logic [15:0] x, y, z,
output logic [10:0] xm, ym, zm,
output logic [4:0] xe, ye, ze,
output logic xs, ys, zs,
output logic xzero, yzero, zzero, xinf, yinf, zinf, xnan, ynan, znan);
unpacknum16 upx(x, xm, xe, xs, xzero, xinf, xnan);
unpacknum16 upy(y, ym, ye, ys, yzero, yinf, ynan);
unpacknum16 upz(z, zm, ze, zs, zzero, zinf, znan);
endmodule
module unpacknum16(
input logic [15:0] num,
output logic [10:0] m,
output logic [4:0] e,
output logic s,
output logic zero, inf, nan);
logic [9:0] f; // fraction without leading 1
logic [4:0] eb; // biased exponent
assign {s, eb, f} = num; // pull bit fields out of floating-point number
assign m = {1'b1, f}; // prepend leading 1 to fraction
assign e = eb; // leave bias in exponent ***
assign zero = (e == 0 && f == 0);
assign inf = (e == 31 && f == 0);
assign nan = (e == 31 && f != 0);
endmodule

24
pipelined/src/fma/fma16_template.v
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@ -1,24 +0,0 @@
// fma16.sv
// David_Harris@hmc.edu 26 February 2022
// 16-bit floating-point multiply-accumulate
// Operation: general purpose multiply, add, fma, with optional negation
// If mul=1, p = x * y. Else p = x.
// If add=1, result = p + z. Else result = p.
// If negr or negz = 1, negate result or z to handle negations and subtractions
// fadd: mul = 0, add = 1, negr = negz = 0
// fsub: mul = 0, add = 1, negr = 0, negz = 1
// fmul: mul = 1, add = 0, negr = 0, negz = 0
// fmadd: mul = 1, add = 1, negr = 0, negz = 0
// fmsub: mul = 1, add = 1, negr = 0, negz = 1
// fnmadd: mul = 1, add = 1, negr = 1, negz = 0
// fnmsub: mul = 1, add = 1, negr = 1, negz = 1
module fma16(
input logic [15:0] x, y, z,
input logic mul, add, negr, negz,
input logic [1:0] roundmode, // 00: rz, 01: rne, 10: rp, 11: rn
output logic [15:0] result);
endmodule

240
pipelined/src/fma/fma16_testgen.c
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@ -1,240 +0,0 @@
#include <stdio.h>
#include <stdint.h>
#include "softfloat.h"
#include "softfloat_types.h"
typedef union sp {
float32_t v;
float f;
} sp;
// lists of tests, terminated with 0x8000
uint16_t easyExponents[] = {15, 0x8000};
uint16_t medExponents[] = {1, 14, 15, 16, 20, 30, 0x8000};
uint16_t allExponents[] = {1, 15, 16, 30, 31, 0x8000};
uint16_t easyFracts[] = {0, 0x200, 0x8000}; // 1.0 and 1.1
uint16_t medFracts[] = {0, 0x200, 0x001, 0x3FF, 0x8000};
uint16_t zeros[] = {0x0000, 0x8000};
uint16_t infs[] = {0x7C00, 0xFC00};
uint16_t nans[] = {0x7D00, 0x7D01};
void softfloatInit(void) {
softfloat_roundingMode = softfloat_round_minMag;
softfloat_exceptionFlags = 0;
softfloat_detectTininess = softfloat_tininess_beforeRounding;
}
float convFloat(float16_t f16) {
float32_t f32;
float res;
sp r;
f32 = f16_to_f32(f16);
r.v = f32;
res = r.f;
return res;
}
void genCase(FILE *fptr, float16_t x, float16_t y, float16_t z, int mul, int add, int negp, int negz, int roundingMode, int zeroAllowed, int infAllowed, int nanAllowed) {
float16_t result;
int op, flagVals;
char calc[80], flags[80];
float32_t x32, y32, z32, r32;
float xf, yf, zf, rf;
float16_t smallest;
if (!mul) y.v = 0x3C00; // force y to 1 to avoid multiply
if (!add) z.v = 0x0000; // force z to 0 to avoid add
if (negp) x.v ^= 0x8000; // flip sign of x to negate p
if (negz) z.v ^= 0x8000; // flip sign of z to negate z
op = roundingMode << 4 | mul<<3 | add<<2 | negp<<1 | negz;
// printf("op = %02x rm %d mul %d add %d negp %d negz %d\n", op, roundingMode, mul, add, negp, negz);
softfloat_exceptionFlags = 0; // clear exceptions
result = f16_mulAdd(x, y, z);
sprintf(flags, "NV: %d OF: %d UF: %d NX: %d",
(softfloat_exceptionFlags >> 4) % 2,
(softfloat_exceptionFlags >> 2) % 2,
(softfloat_exceptionFlags >> 1) % 2,
(softfloat_exceptionFlags) % 2);
// pack these four flags into one nibble, discarding DZ flag
flagVals = softfloat_exceptionFlags & 0x7 | ((softfloat_exceptionFlags >> 1) & 0x8);
// convert to floats for printing
xf = convFloat(x);
yf = convFloat(y);
zf = convFloat(z);
rf = convFloat(result);
if (mul)
if (add) sprintf(calc, "%f * %f + %f = %f", xf, yf, zf, rf);
else sprintf(calc, "%f * %f = %f", xf, yf, rf);
else sprintf(calc, "%f + %f = %f", xf, zf, rf);
// omit denorms, which aren't required for this project
smallest.v = 0x0400;
float16_t resultmag = result;
resultmag.v &= 0x7FFF; // take absolute value
if (f16_lt(resultmag, smallest) && (resultmag.v != 0x0000)) fprintf (fptr, "// skip denorm: ");
if (resultmag.v == 0x0000 && !zeroAllowed) fprintf(fptr, "// skip zero: ");
if ((resultmag.v == 0x7C00 || resultmag.v == 0x7BFF) && !infAllowed) fprintf(fptr, "// Skip inf: ");
if (resultmag.v > 0x7C00 && !nanAllowed) fprintf(fptr, "// Skip NaN: ");
fprintf(fptr, "%04x_%04x_%04x_%02x_%04x_%01x // %s %s\n", x.v, y.v, z.v, op, result.v, flagVals, calc, flags);
}
void prepTests(uint16_t *e, uint16_t *f, char *testName, char *desc, float16_t *cases,
FILE *fptr, int *numCases) {
int i, j;
fprintf(fptr, desc); fprintf(fptr, "\n");
*numCases=0;
for (i=0; e[i] != 0x8000; i++)
for (j=0; f[j] != 0x8000; j++) {
cases[*numCases].v = f[j] | e[i]<<10;
*numCases = *numCases + 1;
}
}
void genMulTests(uint16_t *e, uint16_t *f, int sgn, char *testName, char *desc, int roundingMode, int zeroAllowed, int infAllowed, int nanAllowed) {
int i, j, k, numCases;
float16_t x, y, z;
float16_t cases[100000];
FILE *fptr;
char fn[80];
sprintf(fn, "work/%s.tv", testName);
fptr = fopen(fn, "w");
prepTests(e, f, testName, desc, cases, fptr, &numCases);
z.v = 0x0000;
for (i=0; i < numCases; i++) {
x.v = cases[i].v;
for (j=0; j<numCases; j++) {
y.v = cases[j].v;
for (k=0; k<=sgn; k++) {
y.v ^= (k<<15);
genCase(fptr, x, y, z, 1, 0, 0, 0, roundingMode, zeroAllowed, infAllowed, nanAllowed);
}
}
}
fclose(fptr);
}
void genAddTests(uint16_t *e, uint16_t *f, int sgn, char *testName, char *desc, int roundingMode, int zeroAllowed, int infAllowed, int nanAllowed) {
int i, j, k, numCases;
float16_t x, y, z;
float16_t cases[100000];
FILE *fptr;
char fn[80];
sprintf(fn, "work/%s.tv", testName);
fptr = fopen(fn, "w");
prepTests(e, f, testName, desc, cases, fptr, &numCases);
y.v = 0x0000;
for (i=0; i < numCases; i++) {
x.v = cases[i].v;
for (j=0; j<numCases; j++) {
z.v = cases[j].v;
for (k=0; k<=sgn; k++) {
z.v ^= (k<<15);
genCase(fptr, x, y, z, 0, 1, 0, 0, roundingMode, zeroAllowed, infAllowed, nanAllowed);
}
}
}
fclose(fptr);
}
void genFMATests(uint16_t *e, uint16_t *f, int sgn, char *testName, char *desc, int roundingMode, int zeroAllowed, int infAllowed, int nanAllowed) {
int i, j, k, l, numCases;
float16_t x, y, z;
float16_t cases[100000];
FILE *fptr;
char fn[80];
sprintf(fn, "work/%s.tv", testName);
fptr = fopen(fn, "w");
prepTests(e, f, testName, desc, cases, fptr, &numCases);
for (i=0; i < numCases; i++) {
x.v = cases[i].v;
for (j=0; j<numCases; j++) {
y.v = cases[j].v;
for (k=0; k<numCases; k++) {
z.v = cases[k].v;
for (l=0; l<=sgn; l++) {
z.v ^= (l<<15);
genCase(fptr, x, y, z, 1, 1, 0, 0, roundingMode, zeroAllowed, infAllowed, nanAllowed);
}
}
}
}
fclose(fptr);
}
void genSpecialTests(uint16_t *e, uint16_t *f, int sgn, char *testName, char *desc, int roundingMode, int zeroAllowed, int infAllowed, int nanAllowed) {
int i, j, k, sx, sy, sz, numCases;
float16_t x, y, z;
float16_t cases[100000];
FILE *fptr;
char fn[80];
sprintf(fn, "work/%s.tv", testName);
fptr = fopen(fn, "w");
prepTests(e, f, testName, desc, cases, fptr, &numCases);
cases[numCases].v = 0x0000; // add +0 case
cases[numCases+1].v = 0x8000; // add -0 case
numCases += 2;
for (i=0; i < numCases; i++) {
x.v = cases[i].v;
for (j=0; j<numCases; j++) {
y.v = cases[j].v;
for (k=0; k<numCases; k++) {
z.v = cases[k].v;
for (sx=0; sx<=sgn; sx++) {
x.v ^= (sx<<15);
for (sy=0; sy<=sgn; sy++) {
y.v ^= (sy<<15);
for (sz=0; sz<=sgn; sz++) {
z.v ^= (sz<<15);
genCase(fptr, x, y, z, 1, 1, 0, 0, roundingMode, zeroAllowed, infAllowed, nanAllowed);
}
}
}
}
}
}
fclose(fptr);
}
int main()
{
softfloatInit(); // configure softfloat modes
// Test cases: multiplication
genMulTests(easyExponents, easyFracts, 0, "fmul_0", "// Multiply with exponent of 0, significand of 1.0 and 1.1, RZ", 0, 0, 0, 0);
genMulTests(medExponents, medFracts, 0, "fmul_1", "// Multiply with various exponents and unsigned fractions, RZ", 0, 0, 0, 0);
genMulTests(medExponents, medFracts, 1, "fmul_2", "// Multiply with various exponents and signed fractions, RZ", 0, 0, 0, 0);
// Test cases: addition
genAddTests(easyExponents, easyFracts, 0, "fadd_0", "// Add with exponent of 0, significand of 1.0 and 1.1, RZ", 0, 0, 0, 0);
genAddTests(medExponents, medFracts, 0, "fadd_1", "// Add with various exponents and unsigned fractions, RZ", 0, 0, 0, 0);
genAddTests(medExponents, medFracts, 1, "fadd_2", "// Add with various exponents and signed fractions, RZ", 0, 0, 0, 0);
// Test cases: FMA
genFMATests(easyExponents, easyFracts, 0, "fma_0", "// FMA with exponent of 0, significand of 1.0 and 1.1, RZ", 0, 0, 0, 0);
genFMATests(medExponents, medFracts, 0, "fma_1", "// FMA with various exponents and unsigned fractions, RZ", 0, 0, 0, 0);
genFMATests(medExponents, medFracts, 1, "fma_2", "// FMA with various exponents and signed fractions, RZ", 0, 0, 0, 0);
// Test cases: Zero, Infinity, NaN
genSpecialTests(allExponents, medFracts, 1, "fma_special_rz", "// FMA with special cases, RZ", 0, 1, 1, 1);
// Full test cases with other rounding modes
softfloat_roundingMode = softfloat_round_near_even;
genSpecialTests(allExponents, medFracts, 1, "fma_special_rne", "// FMA with special cases, RNE", 1, 1, 1, 1);
softfloat_roundingMode = softfloat_round_min;
genSpecialTests(allExponents, medFracts, 1, "fma_special_rm", "// FMA with special cases, RM", 2, 1, 1, 1);
softfloat_roundingMode = softfloat_round_max;
genSpecialTests(allExponents, medFracts, 1, "fma_special_rp", "// FMA with special cases, RP", 3, 1, 1, 1);
return 0;
}

8
pipelined/src/fma/lint-fma
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@ -1,8 +0,0 @@
#!/bin/bash
# check for warnings in Verilog code
# The verilator lint tool is faster and better than Modelsim so it is best to run this first.
export PATH=$PATH:/usr/local/bin/
verilator=`which verilator`
basepath=$(dirname $0)/..
$verilator --lint-only --top-module fma16 fma16.v

2
pipelined/src/fma/sim-fma
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@ -1,2 +0,0 @@
vsim -do "do fma.do"

1
pipelined/src/fma/sim-fma-batch
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@ -1 +0,0 @@
vsim -c -do "do fma.do"

1
pipelined/src/fma/synth
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@ -1 +0,0 @@
make -C ../../../synthDC synth DESIGN=fma16

52
pipelined/src/fma/testbench.v
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@ -1,52 +0,0 @@
/* verilator lint_off STMTDLY */
module testbench_fma16;
reg clk, reset;
reg [15:0] x, y, z, rexpected;
wire [15:0] result;
reg [7:0] ctrl;
reg [3:0] flagsexpected;
reg mul, add, negp, negz;
reg [1:0] roundmode;
reg [31:0] vectornum, errors;
reg [75:0] testvectors[10000:0];
// instantiate device under test
fma16 dut(x, y, z, mul, add, negp, negz, roundmode, result);
// generate clock
always
begin
clk = 1; #5; clk = 0; #5;
end
// at start of test, load vectors and pulse reset
initial
begin
$readmemh("work/fmul_0.tv", testvectors);
vectornum = 0; errors = 0;
reset = 1; #22; reset = 0;
end
// apply test vectors on rising edge of clk
always @(posedge clk)
begin
#1; {x, y, z, ctrl, rexpected, flagsexpected} = testvectors[vectornum];
{roundmode, mul, add, negp, negz} = ctrl[5:0];
end
// check results on falling edge of clk
always @(negedge clk)
if (~reset) begin // skip during reset
if (result !== rexpected) begin // check result // *** should also add tests on flags eventually
$display("Error: inputs %h * %h + %h", x, y, z);
$display(" result = %h (%h expected)", result, rexpected);
errors = errors + 1;
end
vectornum = vectornum + 1;
if (testvectors[vectornum] === 'x) begin
$display("%d tests completed with %d errors",
vectornum, errors);
$stop;
end
end
endmodule

86257
pipelined/src/fma/torture.tv
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File diff suppressed because it is too large Load Diff

130
pipelined/src/fma/torturegen.pl
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@ -1,130 +0,0 @@
#!/usr/bin/perl -w
# torturegen.pl
# David_Harris@hmc.edu 19 April 2022
# Convert TestFloat cases into format for fma16 project torture test
# Strip out cases involving denorms
use strict;
my @basenames = ("add", "mul", "mulAdd");
my @roundingmodes = ("rz", "rd", "ru", "rne");
my @names = ();
foreach my $name (@basenames) {
foreach my $mode (@roundingmodes) {
push(@names, "f16_${name}_$mode.tv");
}
}
open(TORTURE, ">work/torture.tv") || die("Can't write torture.tv");
my $datestring = localtime();
print(TORTURE "// Torture tests generated $datestring by $0\n");
foreach my $tv (@names) {
open(TV, "work/$tv") || die("Can't read $tv");
my $type = &getType($tv); # is it mul, add, mulAdd
my $rm = &getRm($tv); # rounding mode
# if ($rm != 0) { next; } # only do rz
print (TORTURE "\n////////// Testcases from $tv of type $type rounding mode $rm\n");
print ("\n////////// Testcases from $tv of type $type rounding mode $rm\n");
my $linecount = 0;
my $babyTorture = 0;
while (<TV>) {
my $line = $_;
$linecount++;
my $density = 10;
if ($type eq "mulAdd") {$density = 500;}
if ($babyTorture) {
$density = 100;
if ($type eq "mulAdd") {$density = 50000;}
}
if ((($linecount + $rm) % $density) != 0) { next }; # too many tests to use
chomp($line); # strip off newline
my @parts = split(/_/, $line);
my ($x, $y, $z, $op, $w, $flags);
$x = $parts[0];
if ($type eq "add") { $y = "0000"; } else {$y = $parts[1]};
if ($type eq "mul") { $z = "3CFF"; } elsif ($type eq "add") {$z = $parts[1]} else { $z = $parts[2]};
$op = $rm << 4;
if ($type eq "mul" || $type eq "mulAdd") { $op = $op + 8; }
if ($type eq "add" || $type eq "mulAdd") { $op = $op + 4; }
my $opname = sprintf("%02x", $op);
if ($type eq "mulAdd") {$w = $parts[3];} else {$w = $parts[2]};
if ($type eq "mulAdd") {$flags = $parts[4];} else {$flags = $parts[3]};
$flags = substr($flags, -1); # take last character
if (&fpval($w) eq "NaN") { $w = "7e00"; }
my $vec = "${x}_${y}_${z}_${opname}_${w}_${flags}";
my $skip = "";
if (&isdenorm($x) || &isdenorm($y) || &isdenorm($z) || &isdenorm($w)) {
$skip = "Skipped denorm";
}
my $summary = &summary($x, $y, $z, $w, $type);
if ($skip ne "") {
print TORTURE "// $skip $tv line $linecount $line $summary\n"
}
else { print TORTURE "$vec // $tv line $linecount $line $summary\n";}
}
close(TV);
}
close(TORTURE);
sub fpval {
my $val = shift;
$val = hex($val); # convert hex string to number
my $frac = $val & 0x3FF;
my $exp = ($val >> 10) & 0x1F;
my $sign = $val >> 15;
my $res;
if ($exp == 31 && $frac != 0) { return "NaN"; }
elsif ($exp == 31) { $res = "INF"; }
elsif ($val == 0) { $res = 0; }
elsif ($exp == 0) { $res = "Denorm"; }
else { $res = sprintf("1.%011b x 2^%d", $frac, $exp-15); }
if ($sign == 1) { $res = "-$res"; }
return $res;
}
sub summary {
my $x = shift; my $y = shift; my $z = shift; my $w = shift; my $type = shift;
my $xv = &fpval($x);
my $yv = &fpval($y);
my $zv = &fpval($z);
my $wv = &fpval($w);
if ($type eq "add") { return "$xv + $zv = $wv"; }
elsif ($type eq "mul") { return "$xv * $yv = $wv"; }
else {return "$xv * $yv + $zv = $wv"; }
}
sub getType {
my $tv = shift;
if ($tv =~ /mulAdd/) { return("mulAdd"); }
elsif ($tv =~ /mul/) { return "mul"; }
else { return "add"; }
}
sub getRm {
my $tv = shift;
if ($tv =~ /rz/) { return 0; }
elsif ($tv =~ /rne/) { return 1; }
elsif ($tv =~ /rd/) {return 2; }
elsif ($tv =~ /ru/) { return 3; }
else { return "bad"; }
}
sub isdenorm {
my $fp = shift;
my $val = hex($fp);
my $expv = $val >> 10;
$expv = $expv & 0x1F;
my $denorm = 0;
if ($expv == 0 && $val != 0) { $denorm = 1;}
# my $e0 = ($expv == 0);
# my $vn0 = ($val != 0);
# my $denorm = 0; #($exp == 0 && $val != 0); # denorm exponent but not all zero
# print("Num $fp Exp $expv Denorm $denorm Done\n");
return $denorm;
}

62
pipelined/src/fma/wave.do
View File

@ -1,62 +0,0 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /testbench_fma16/clk
add wave -noupdate /testbench_fma16/reset
add wave -noupdate /testbench_fma16/x
add wave -noupdate /testbench_fma16/y
add wave -noupdate /testbench_fma16/z
add wave -noupdate /testbench_fma16/result
add wave -noupdate /testbench_fma16/rexpected
add wave -noupdate /testbench_fma16/dut/x
add wave -noupdate /testbench_fma16/dut/y
add wave -noupdate /testbench_fma16/dut/z
add wave -noupdate /testbench_fma16/dut/mul
add wave -noupdate /testbench_fma16/dut/add
add wave -noupdate /testbench_fma16/dut/negr
add wave -noupdate /testbench_fma16/dut/negz
add wave -noupdate /testbench_fma16/dut/roundmode
add wave -noupdate /testbench_fma16/dut/result
add wave -noupdate /testbench_fma16/dut/XManE
add wave -noupdate /testbench_fma16/dut/YManE
add wave -noupdate /testbench_fma16/dut/ZManE
add wave -noupdate /testbench_fma16/dut/XExpE
add wave -noupdate /testbench_fma16/dut/YExpE
add wave -noupdate /testbench_fma16/dut/ZExpE
add wave -noupdate /testbench_fma16/dut/PExpE
add wave -noupdate /testbench_fma16/dut/Ne
add wave -noupdate /testbench_fma16/dut/upOneExt
add wave -noupdate /testbench_fma16/dut/XSgnE
add wave -noupdate /testbench_fma16/dut/YSgnE
add wave -noupdate /testbench_fma16/dut/ZSgnE
add wave -noupdate /testbench_fma16/dut/PSgnE
add wave -noupdate /testbench_fma16/dut/ProdManE
add wave -noupdate /testbench_fma16/dut/NfracS
add wave -noupdate /testbench_fma16/dut/ProdManAl
add wave -noupdate /testbench_fma16/dut/ZManExt
add wave -noupdate /testbench_fma16/dut/ZManAl
add wave -noupdate /testbench_fma16/dut/Nfrac
add wave -noupdate /testbench_fma16/dut/res
add wave -noupdate -radix decimal /testbench_fma16/dut/AlignCnt
add wave -noupdate /testbench_fma16/dut/NSamt
add wave -noupdate /testbench_fma16/dut/ZExpGreater
add wave -noupdate /testbench_fma16/dut/ACLess
add wave -noupdate /testbench_fma16/dut/upOne
add wave -noupdate /testbench_fma16/dut/KillProd
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {3746 ns} 1} {{Cursor 2} {4169 ns} 0}
quietly wave cursor active 2
configure wave -namecolwidth 237
configure wave -valuecolwidth 64
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {4083 ns} {4235 ns}

4
pipelined/src/fpu/fclassify.sv
View File

@ -8,7 +8,7 @@ module fclassify (
input logic XDenormE, // is denormal
input logic XZeroE, // is zero
input logic XInfE, // is infinity
output logic [63:0] ClassResE // classify result
output logic [`XLEN-1:0] ClassResE // classify result
);
logic PInf, PZero, PNorm, PDenorm;
@ -37,6 +37,6 @@ module fclassify (
// bit 7 - +Inf
// bit 8 - signaling NaN
// bit 9 - quiet NaN
assign ClassResE = {{54{1'b0}}, XNaNE&~XSNaNE, XSNaNE, PInf, PNorm, PDenorm, PZero, NZero, NDenorm, NNorm, NInf};
assign ClassResE = {{`XLEN-10{1'b0}}, XNaNE&~XSNaNE, XSNaNE, PInf, PNorm, PDenorm, PZero, NZero, NDenorm, NNorm, NInf};
endmodule

2
pipelined/src/fpu/fcmp.sv
View File

@ -10,7 +10,7 @@
module fcmp (
input logic [`FPSIZES/3:0] FmtE, // precision 1 = double 0 = single
input logic [`FMTBITS-1:0] FmtE, // precision 1 = double 0 = single
input logic [2:0] FOpCtrlE, // see above table
input logic XSgnE, YSgnE, // input signs
input logic [`NE-1:0] XExpE, YExpE, // input exponents

19
pipelined/src/fpu/fctrl.sv
View File

@ -1,3 +1,4 @@
`include "wally-config.vh"
module fctrl (
input logic [6:0] Funct7D, // bits 31:25 of instruction - may contain percision
@ -13,7 +14,7 @@ module fctrl (
output logic [2:0] FOpCtrlD, // chooses which opperation to do - specifics shown at bottom of module and in each unit
output logic [1:0] FResSelD, // select one of the results done in the memory stage
output logic [1:0] FIntResSelD, // select the result that will be written to the integer register
output logic FmtD, // precision - single-0 double-1
output logic [`FMTBITS-1:0] FmtD, // precision - single-0 double-1
output logic [2:0] FrmD, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude
output logic FWriteIntD // is the result written to the integer register
);
@ -72,14 +73,12 @@ module fctrl (
2'b01: ControlsD = `FCTRLW'b1_0_11_100_11_00_0_0; // fcvt.s.wu wu->s
2'b10: ControlsD = `FCTRLW'b1_0_11_111_11_00_0_0; // fcvt.s.l l->s
2'b11: ControlsD = `FCTRLW'b1_0_11_110_11_00_0_0; // fcvt.s.lu lu->s
default: ControlsD = `FCTRLW'b0_0_00_000_00_00_0_1; // non-implemented instruction
endcase
7'b1100000: case(Rs2D[1:0])
2'b00: ControlsD = `FCTRLW'b0_1_11_001_11_11_0_0; // fcvt.w.s s->w
2'b01: ControlsD = `FCTRLW'b0_1_11_000_11_11_0_0; // fcvt.wu.s s->wu
2'b10: ControlsD = `FCTRLW'b0_1_11_011_11_11_0_0; // fcvt.l.s s->l
2'b11: ControlsD = `FCTRLW'b0_1_11_010_11_11_0_0; // fcvt.lu.s s->lu
default: ControlsD = `FCTRLW'b0_0_00_000_00_00_0_1; // non-implemented instruction
endcase
7'b1111000: ControlsD = `FCTRLW'b1_0_11_000_00_00_0_0; // fmv.w.x
7'b0100000: ControlsD = `FCTRLW'b1_0_11_000_11_00_0_0; // fcvt.s.d
@ -88,14 +87,12 @@ module fctrl (
2'b01: ControlsD = `FCTRLW'b1_0_11_100_11_00_0_0; // fcvt.d.wu wu->d
2'b10: ControlsD = `FCTRLW'b1_0_11_111_11_00_0_0; // fcvt.d.l l->d
2'b11: ControlsD = `FCTRLW'b1_0_11_110_11_00_0_0; // fcvt.d.lu lu->d
default: ControlsD = `FCTRLW'b0_0_00_000_00_00_0_1; // non-implemented instruction
endcase
7'b1100001: case(Rs2D[1:0])
2'b00: ControlsD = `FCTRLW'b0_1_11_001_11_11_0_0; // fcvt.w.d d->w
2'b01: ControlsD = `FCTRLW'b0_1_11_000_11_11_0_0; // fcvt.wu.d d->wu
2'b10: ControlsD = `FCTRLW'b0_1_11_011_11_11_0_0; // fcvt.l.d d->l
2'b11: ControlsD = `FCTRLW'b0_1_11_010_11_11_0_0; // fcvt.lu.d d->lu
default: ControlsD = `FCTRLW'b0_0_00_000_00_00_0_1; // non-implemented instruction
endcase
7'b1111001: ControlsD = `FCTRLW'b1_0_11_001_00_00_0_0; // fmv.d.x
7'b0100001: ControlsD = `FCTRLW'b1_0_11_001_11_00_0_0; // fcvt.d.s
@ -119,8 +116,18 @@ module fctrl (
// Precision
// 0-single
// 1-double
assign FmtD = FResultSelD == 2'b00 ? Funct3D[0] : ((Funct7D[6:3] == 4'b0100)&OpD[4]) | OpD[6:1] == 6'b010000 ? ~Funct7D[0] : Funct7D[0];
if (`FPSIZES == 1)
assign FmtD = 0;
else if (`FPSIZES == 2)begin
logic [1:0] FmtTmp;
assign FmtTmp = (FResultSelD == 2'b00) ? {~Funct3D[1], ~(Funct3D[1]^Funct3D[0])} : ((Funct7D[6:3] == 4'b0100)&OpD[4]) ? Rs2D[1:0] : Funct7D[1:0];
assign FmtD = (`FMT == FmtTmp);
end
else if (`FPSIZES == 3|`FPSIZES == 4)
assign FmtD = (FResultSelD == 2'b00) ? {~Funct3D[1], ~(Funct3D[1]^Funct3D[0])} : ((Funct7D[6:3] == 4'b0100)&OpD[4]) ? Rs2D[1:0] : Funct7D[1:0];
// assign FmtD = FResultSelD == 2'b00 ? Funct3D[0] : ((Funct7D[6:3] == 4'b0100)&OpD[4]) | OpD[6:1] == 6'b010000 ? ~Funct7D[0] : Funct7D[0];
// FResultSel:
// 000 - ReadRes - load
// 001 - FMARes - FMA and multiply

43
pipelined/src/fpu/fcvt.sv
View File

@ -2,6 +2,7 @@
`include "wally-config.vh"
// largest length in IEU/FPU
`define LGLEN ((`NF<`XLEN) ? `XLEN : `NF)
`define LOGLGLEN $unsigned($clog2(`LGLEN+1))
module fcvt (
input logic XSgnE, // input's sign
@ -16,7 +17,7 @@ module fcvt (
input logic XNaNE, // is the input a NaN
input logic XSNaNE, // is the input a signaling NaN
input logic [2:0] FrmE, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude
input logic [`FPSIZES/3:0] FmtE, // the input's precision (11=quad 01=double 00=single 10=half)
input logic [`FMTBITS-1:0] FmtE, // the input's precision (11=quad 01=double 00=single 10=half)
output logic [`FLEN-1:0] CvtResE, // the fp conversion result
output logic [`XLEN-1:0] CvtIntResE, // the int conversion result
output logic [4:0] CvtFlgE // the conversion's flags
@ -37,12 +38,12 @@ module fcvt (
// (FI) fp -> int coversion signals
logic [`FPSIZES/3:0] OutFmt; // format of the output
logic [`FMTBITS-1:0] OutFmt; // format of the output
logic [`XLEN-1:0] PosInt; // the positive integer input
logic [`XLEN-1:0] TrimInt; // integer trimmed to the correct size
logic [`LGLEN-1:0] LzcIn; // input to the Leading Zero Counter (priority encoder)
logic [`NE:0] CalcExp; // the calculated expoent
logic [$clog2(`LGLEN+1)-1:0] ShiftAmt; // how much to shift by
logic [`LOGLGLEN-1:0] ShiftAmt; // how much to shift by
logic [`LGLEN+`NF:0] ShiftIn; // number to be shifted
logic ResDenormUf;// does the result underflow or is denormalized
logic ResUf; // does the result underflow
@ -72,7 +73,7 @@ module fcvt (
logic Int64; // is the integer 64 bits?
logic IntToFp; // is the opperation an int->fp conversion?
logic ToInt; // is the opperation an fp->int conversion?
logic [$clog2(`LGLEN+1)-1:0] ZeroCnt; // output from the LZC
logic [`LOGLGLEN-1:0] ZeroCnt; // output from the LZC
// seperate OpCtrl for code readability
@ -143,9 +144,9 @@ module fcvt (
// - only shift fp -> fp if the intital value is denormalized
// - this is a problem because the input to the lzc was the fraction rather than the mantissa
// - rather have a few and-gates than an extra bit in the priority encoder??? *** is this true?
assign ShiftAmt = ToInt ? CalcExp[$clog2(`LGLEN+1)-1:0]&{$clog2(`LGLEN+1){~CalcExp[`NE]}} :
ResDenormUf&~IntToFp ? ($clog2(`LGLEN+1))'(`NF-1)+CalcExp[$clog2(`LGLEN+1)-1:0] :
(ZeroCnt+1)&{$clog2(`LGLEN+1){XDenormE|IntToFp}};
assign ShiftAmt = ToInt ? CalcExp[`LOGLGLEN-1:0]&{`LOGLGLEN{~CalcExp[`NE]}} :
ResDenormUf&~IntToFp ? (`LOGLGLEN)'(`NF-1)+CalcExp[`LOGLGLEN-1:0] :
(ZeroCnt+1)&{`LOGLGLEN{XDenormE|IntToFp}};
// shift
// fp -> int: | `XLEN zeros | Mantissa | 0's if nessisary | << CalcExp
@ -261,34 +262,34 @@ module fcvt (
// - shift left to normilize (-1-ZeroCnt)
// - newBias to make the biased exponent
//
assign CalcExp = {1'b0, OldExp} - (`NE+1)'(`BIAS) + {2'b0, NewBias} - {{`NE{1'b0}}, XDenormE|IntToFp} - {{`NE-$clog2(`LGLEN+1)+1{1'b0}}, (ZeroCnt&{$clog2(`LGLEN+1){XDenormE|IntToFp}})};
assign CalcExp = {1'b0, OldExp} - (`NE+1)'(`BIAS) + {2'b0, NewBias} - {{`NE{1'b0}}, XDenormE|IntToFp} - {{`NE-`LOGLGLEN+1{1'b0}}, (ZeroCnt&{`LOGLGLEN{XDenormE|IntToFp}})};
// find if the result is dnormal or underflows
// - if Calculated expoenent is 0 or negitive (and the input/result is not exactaly 0)
// - can't underflow an integer to Fp conversion
assign ResDenormUf = (~|CalcExp | CalcExp[`NE])&~XZeroE&~IntToFp;
// choose the negative of the fraction size
if (`FPSIZES == 1) begin
assign ResNegNF = -`NF;
assign ResNegNF = -($clog2(`NF)+1)'(`NF);
end else if (`FPSIZES == 2) begin
assign ResNegNF = OutFmt ? -`NF : -`NF1;
assign ResNegNF = OutFmt ? -($clog2(`NF)+1)'(`NF) : -($clog2(`NF)+1)'(`NF1);
end else if (`FPSIZES == 3) begin
always_comb
case (OutFmt)
`FMT: ResNegNF = -`NF;
`FMT1: ResNegNF = -`NF1;
`FMT2: ResNegNF = -`NF2;
`FMT: ResNegNF = -($clog2(`NF)+1)'(`NF);
`FMT1: ResNegNF = -($clog2(`NF)+1)'(`NF1);
`FMT2: ResNegNF = -($clog2(`NF)+1)'(`NF2);
default: ResNegNF = 1'bx;
endcase
end else if (`FPSIZES == 4) begin
always_comb
case (OutFmt)
2'h3: ResNegNF = -`Q_NF;
2'h1: ResNegNF = -`D_NF;
2'h0: ResNegNF = -`S_NF;
2'h2: ResNegNF = -`H_NF;
2'h3: ResNegNF = -($clog2(`NF)+1)'(`Q_NF);
2'h1: ResNegNF = -($clog2(`NF)+1)'(`D_NF);
2'h0: ResNegNF = -($clog2(`NF)+1)'(`S_NF);
2'h2: ResNegNF = -($clog2(`NF)+1)'(`H_NF);
endcase
end
// determine if the result underflows ??? -> fp
@ -453,10 +454,10 @@ module fcvt (
// find the maximum exponent (the exponent and larger overflows)
if (`FPSIZES == 1) begin
assign MaxExp = ToInt ? Int64 ? 65 : 33 : {`NE{1'b1}};
assign MaxExp = ToInt ? Int64 ? (`NE)'(65) : (`NE)'(33) : {`NE{1'b1}};
end else if (`FPSIZES == 2) begin
assign MaxExp = ToInt ? Int64 ? 65 : 33 :
assign MaxExp = ToInt ? Int64 ? (`NE)'($unsigned(65)) : (`NE)'($unsigned(33)) :
OutFmt ? {`NE{1'b1}} : {{`NE-`NE1{1'b0}}, {`NE1{1'b1}}};
end else if (`FPSIZES == 3) begin
@ -476,7 +477,7 @@ module fcvt (
MaxExpFp = 1'bx;
end
endcase
assign MaxExp = ToInt ? Int64 ? 65 : 33 : MaxExpFp;
assign MaxExp = ToInt ? Int64 ? (`NE)'(65) : (`NE)'(33) : MaxExpFp;
end else if (`FPSIZES == 4) begin
logic [`NE-1:0] MaxExpFp;
@ -495,7 +496,7 @@ module fcvt (
MaxExpFp = {{`Q_NE-`H_NE{1'b0}}, {`H_NE{1'b1}}};
end
endcase
assign MaxExp = ToInt ? Int64 ? 65 : 33 : MaxExpFp;
assign MaxExp = ToInt ? Int64 ? (`NE)'(65) : (`NE)'(33) : MaxExpFp;
end
// if the result exponent is larger then the maximum possible exponent

36
pipelined/src/fpu/fma.sv
View File

@ -34,7 +34,7 @@ module fma(
input logic reset,
input logic FlushM, // flush the memory stage
input logic StallM, // stall memory stage
input logic [`FPSIZES/3:0] FmtE, FmtM, // precision 1 = double 0 = single
input logic [`FMTBITS-1:0] FmtE, FmtM, // precision 1 = double 0 = single
input logic [2:0] FOpCtrlE, // 000 = fmadd (X*Y)+Z, 001 = fmsub (X*Y)-Z, 010 = fnmsub -(X*Y)+Z, 011 = fnmadd -(X*Y)-Z, 100 = fmul (X*Y)
input logic [2:0] FrmM, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude
input logic XSgnE, YSgnE, ZSgnE, // input signs - execute stage
@ -81,7 +81,7 @@ module fma(
// E/M pipeline registers
flopenrc #(3*`NF+6) EMRegFma2(clk, reset, FlushM, ~StallM, SumE, SumM);
flopenrc #(13) EMRegFma3(clk, reset, FlushM, ~StallM, ProdExpE, ProdExpM);
flopenrc #(`NE+2) EMRegFma3(clk, reset, FlushM, ~StallM, ProdExpE, ProdExpM);
flopenrc #($clog2(3*`NF+7)+8) EMRegFma4(clk, reset, FlushM, ~StallM,
{AddendStickyE, KillProdE, InvZE, NormCntE, NegSumE, ZSgnEffE, PSgnE, FOpCtrlE[2]&~FOpCtrlE[1]&~FOpCtrlE[0], ZDenormE},
{AddendStickyM, KillProdM, InvZM, NormCntM, NegSumM, ZSgnEffM, PSgnM, Mult, ZDenormM});
@ -102,7 +102,7 @@ module fma1(
input logic [`NF:0] XManE, YManE, ZManE, // fractions in U(0.NF) format
input logic XZeroE, YZeroE, ZZeroE, // is the input zero
input logic [2:0] FOpCtrlE, // 000 = fmadd (X*Y)+Z, 001 = fmsub (X*Y)-Z, 010 = fnmsub -(X*Y)+Z, 011 = fnmadd -(X*Y)-Z, 100 = fmul (X*Y)
input logic [`FPSIZES/3:0] FmtE, // precision 1 = double 0 = single
input logic [`FMTBITS-1:0] FmtE, // precision 1 = double 0 = single
output logic [`NE+1:0] ProdExpE, // X exponent + Y exponent - bias in B(NE+2.0) format; adds 2 bits to allow for size of number and negative sign
output logic AddendStickyE, // sticky bit that is calculated during alignment
output logic KillProdE, // set the product to zero before addition if the product is too small to matter
@ -161,7 +161,7 @@ endmodule
module expadd(
input logic [`FPSIZES/3:0] FmtE, // precision
input logic [`FMTBITS-1:0] FmtE, // precision
input logic [`NE-1:0] XExpE, YExpE, // input exponents
input logic XZeroE, YZeroE, // are the inputs zero
output logic [`NE+1:0] ProdExpE // product's exponent B^(1023)NE+2
@ -237,7 +237,7 @@ module align(
// - positive means the product is larger, so shift Z right
// *** can we use ProdExpE instead of XExp/YExp to save an adder? DH 5/12/22
// KP- yes we used ProdExpE originally but we did this for timing
assign AlignCnt = XZeroE|YZeroE ? -1 : {2'b0, XExpE} + {2'b0, YExpE} - {2'b0, (`NE)'(`BIAS)} + `NF+3 - {2'b0, ZExpE};
assign AlignCnt = XZeroE|YZeroE ? -(`NE+2)'($unsigned(1)) : {2'b0, XExpE} + {2'b0, YExpE} - {2'b0, (`NE)'(`BIAS)} + (`NE+2)'(`NF)+3 - {2'b0, ZExpE};
// Defualt Addition without shifting
// | 54'b0 | 106'b(product) | 2'b0 |
@ -320,7 +320,7 @@ module add(
// Do the addition
// - calculate a positive and negitive sum in parallel
assign PreSum = AlignedAddendInv + {55'b0, ProdManKilled, 2'b0} + {{3*`NF+6{1'b0}}, InvZE};
assign PreSum = AlignedAddendInv + {{`NF+3{1'b0}}, ProdManKilled, 2'b0} + {{3*`NF+6{1'b0}}, InvZE};
assign NegPreSum = XZeroE|YZeroE|KillProdE ? {1'b0, AlignedAddendE} : {1'b0, AlignedAddendE} + {{`NF+3{1'b1}}, ~ProdManKilled, 2'b0} + {(3*`NF+7)'(4)};
// Is the sum negitive
@ -378,7 +378,7 @@ module fma2(
input logic [`NE-1:0] ZExpM, // input exponents
input logic [`NF:0] XManM, YManM, ZManM, // input mantissas
input logic [2:0] FrmM, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude
input logic [`FPSIZES/3:0] FmtM, // precision 1 = double 0 = single
input logic [`FMTBITS-1:0] FmtM, // precision 1 = double 0 = single
input logic [`NE+1:0] ProdExpM, // X exponent + Y exponent - bias
input logic AddendStickyM, // sticky bit that is calculated during alignment
input logic KillProdM, // set the product to zero before addition if the product is too small to matter
@ -517,7 +517,7 @@ module normalize(
input logic [`NE-1:0] ZExpM, // exponent of Z
input logic [`NE+1:0] ProdExpM, // X exponent + Y exponent - bias
input logic [$clog2(3*`NF+7)-1:0] NormCntM, // normalization shift count
input logic [`FPSIZES/3:0] FmtM, // precision 1 = double 0 = single
input logic [`FMTBITS-1:0] FmtM, // precision 1 = double 0 = single
input logic KillProdM, // is the product set to zero
input logic ZDenormM,
input logic AddendStickyM, // the sticky bit caclulated from the aligned addend
@ -543,7 +543,7 @@ module normalize(
assign SumZero = ~(|SumM);
// calculate the sum's exponent
assign SumExpTmpTmp = KillProdM ? {2'b0, ZExpM[`NE-1:1], ZExpM[0]&~ZDenormM} : ProdExpM + -({4'b0, NormCntM} + 1 - (`NF+4));
assign SumExpTmpTmp = KillProdM ? {2'b0, ZExpM[`NE-1:1], ZExpM[0]&~ZDenormM} : ProdExpM + -({{`NE+2-$unsigned($clog2(3*`NF+7)){1'b0}}, NormCntM} + 1 - (`NE+2)'(`NF+4));
//convert the sum's exponent into the propper percision
if (`FPSIZES == 1) begin
@ -556,8 +556,8 @@ module normalize(
always_comb begin
case (FmtM)
`FMT: SumExpTmp = SumExpTmpTmp;
`FMT1: SumExpTmp = (SumExpTmpTmp-`BIAS+`BIAS1)&{`NE+2{|SumExpTmpTmp}};
`FMT2: SumExpTmp = (SumExpTmpTmp-`BIAS+`BIAS2)&{`NE+2{|SumExpTmpTmp}};
`FMT1: SumExpTmp = (SumExpTmpTmp-(`NE+2)'(`BIAS)+(`NE+2)'(`BIAS1))&{`NE+2{|SumExpTmpTmp}};
`FMT2: SumExpTmp = (SumExpTmpTmp-(`NE+2)'(`BIAS)+(`NE+2)'(`BIAS2))&{`NE+2{|SumExpTmpTmp}};
default: SumExpTmp = `NE+2'bx;
endcase
end
@ -566,9 +566,9 @@ module normalize(
always_comb begin
case (FmtM)
2'h3: SumExpTmp = SumExpTmpTmp;
2'h1: SumExpTmp = (SumExpTmpTmp-`BIAS+`D_BIAS)&{`NE+2{|SumExpTmpTmp}};
2'h0: SumExpTmp = (SumExpTmpTmp-`BIAS+`S_BIAS)&{`NE+2{|SumExpTmpTmp}};
2'h2: SumExpTmp = (SumExpTmpTmp-`BIAS+`H_BIAS)&{`NE+2{|SumExpTmpTmp}};
2'h1: SumExpTmp = (SumExpTmpTmp-(`NE+2)'(`BIAS)+(`NE+2)'(`D_BIAS))&{`NE+2{|SumExpTmpTmp}};
2'h0: SumExpTmp = (SumExpTmpTmp-(`NE+2)'(`BIAS)+(`NE+2)'(`S_BIAS))&{`NE+2{|SumExpTmpTmp}};
2'h2: SumExpTmp = (SumExpTmpTmp-(`NE+2)'(`BIAS)+(`NE+2)'(`H_BIAS))&{`NE+2{|SumExpTmpTmp}};
endcase
end
@ -674,14 +674,14 @@ module normalize(
// Determine sum's exponent
// if plus1 If plus2 if said denorm but norm plus 1 if said denorm but norm plus 2
assign SumExp = (SumExpTmp+{12'b0, LZAPlus1&~KillProdM}+{11'b0, LZAPlus2&~KillProdM, 1'b0}+{12'b0, ~ResultDenorm&PreResultDenorm&~KillProdM}+{12'b0, &SumExpTmp&SumShifted[3*`NF+6]&~KillProdM}) & {`NE+2{~(SumZero|ResultDenorm)}};
assign SumExp = (SumExpTmp+{{`NE+1{1'b0}}, LZAPlus1&~KillProdM}+{{`NE{1'b0}}, LZAPlus2&~KillProdM, 1'b0}+{{`NE+1{1'b0}}, ~ResultDenorm&PreResultDenorm&~KillProdM}+{{`NE+1{1'b0}}, &SumExpTmp&SumShifted[3*`NF+6]&~KillProdM}) & {`NE+2{~(SumZero|ResultDenorm)}};
// recalculate if the result is denormalized
assign ResultDenorm = PreResultDenorm&~SumShifted[3*`NF+6]&~SumShifted[3*`NF+7];
endmodule
module fmaround(
input logic [`FPSIZES/3:0] FmtM, // precision 1 = double 0 = single
input logic [`FMTBITS-1:0] FmtM, // precision 1 = double 0 = single
input logic [2:0] FrmM, // rounding mode
input logic UfSticky, // sticky bit for underlow calculation
input logic [`NF+1:0] NormSum, // normalized sum
@ -920,7 +920,7 @@ module fmaflags(
input logic [`NE+1:0] SumExp, // exponent of the normalized sum
input logic ZSgnEffM, PSgnM, // the product and modified Z signs
input logic Round, Guard, UfLSBNormSum, Sticky, UfPlus1, // bits used to determine rounding
input logic [`FPSIZES/3:0] FmtM, // precision 1 = double 0 = single
input logic [`FMTBITS-1:0] FmtM, // precision 1 = double 0 = single
output logic Invalid, Overflow, Underflow, // flags used to select the result
output logic [4:0] FMAFlgM // FMA flags
);
@ -996,7 +996,7 @@ module resultselect(
input logic [`NE-1:0] ZExpM, // input exponents
input logic [`NF:0] XManM, YManM, ZManM, // input mantissas
input logic [2:0] FrmM, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude
input logic [`FPSIZES/3:0] FmtM, // precision 1 = double 0 = single
input logic [`FMTBITS-1:0] FmtM, // precision 1 = double 0 = single
input logic AddendStickyM, // sticky bit that is calculated during alignment
input logic KillProdM, // set the product to zero before addition if the product is too small to matter
input logic XInfM, YInfM, ZInfM, // inputs are infinity

166
pipelined/src/fpu/fpu.sv
View File

@ -65,7 +65,7 @@ module fpu (
// control signals
logic FRegWriteD, FRegWriteE, FRegWriteW; // FP register write enable
logic [2:0] FrmD, FrmE, FrmM; // FP rounding mode
logic FmtD, FmtE, FmtM, FmtW; // FP precision 0-single 1-double
logic [`FMTBITS-1:0] FmtD, FmtE, FmtM, FmtW; // FP precision 0-single 1-double
logic FDivStartD, FDivStartE; // Start division or squareroot
logic FWriteIntD; // Write to integer register
logic [1:0] FForwardXE, FForwardYE, FForwardZE; // forwarding mux control signals
@ -77,19 +77,19 @@ module fpu (
logic [4:0] Adr1E, Adr2E, Adr3E; // adresses of each input
// regfile signals
logic [63:0] FRD1D, FRD2D, FRD3D; // Read Data from FP register - decode stage
logic [63:0] FRD1E, FRD2E, FRD3E; // Read Data from FP register - execute stage
logic [63:0] FSrcXE; // Input 1 to the various units (after forwarding)
logic [63:0] FPreSrcYE, FSrcYE; // Input 2 to the various units (after forwarding)
logic [63:0] FPreSrcZE, FSrcZE; // Input 3 to the various units (after forwarding)
logic [`FLEN-1:0] FRD1D, FRD2D, FRD3D; // Read Data from FP register - decode stage
logic [`FLEN-1:0] FRD1E, FRD2E, FRD3E; // Read Data from FP register - execute stage
logic [`FLEN-1:0] FSrcXE; // Input 1 to the various units (after forwarding)
logic [`FLEN-1:0] FPreSrcYE, FSrcYE; // Input 2 to the various units (after forwarding)
logic [`FLEN-1:0] FPreSrcZE, FSrcZE; // Input 3 to the various units (after forwarding)
// unpacking signals
logic XSgnE, YSgnE, ZSgnE; // input's sign - execute stage
logic XSgnM, YSgnM; // input's sign - memory stage
logic [10:0] XExpE, YExpE, ZExpE; // input's exponent - execute stage
logic [10:0] ZExpM; // input's exponent - memory stage
logic [52:0] XManE, YManE, ZManE; // input's fraction - execute stage
logic [52:0] XManM, YManM, ZManM; // input's fraction - memory stage
logic [`NE-1:0] XExpE, YExpE, ZExpE; // input's exponent - execute stage
logic [`NE-1:0] ZExpM; // input's exponent - memory stage
logic [`NF:0] XManE, YManE, ZManE; // input's fraction - execute stage
logic [`NF:0] XManM, YManM, ZManM; // input's fraction - memory stage
logic XNaNE, YNaNE, ZNaNE; // is the input a NaN - execute stage
logic XNaNM, YNaNM, ZNaNM; // is the input a NaN - memory stage
logic XNaNQ, YNaNQ; // is the input a NaN - divide
@ -109,26 +109,27 @@ module fpu (
// result and flag signals
logic [63:0] FDivResM, FDivResW; // divide/squareroot result
logic [4:0] FDivFlgM; // divide/squareroot flags
logic [63:0] FMAResM, FMAResW; // FMA/multiply result
logic [`FLEN-1:0] FMAResM, FMAResW; // FMA/multiply result
logic [4:0] FMAFlgM; // FMA/multiply result
logic [63:0] ReadResW; // read result (load instruction)
logic [63:0] CvtResE; // FP <-> int convert result
logic [`FLEN-1:0] ReadResW; // read result (load instruction)
logic [`FLEN-1:0] CvtResE; // FP <-> int convert result
logic [`XLEN-1:0] CvtIntResE; // FP <-> int convert result
logic [4:0] CvtFlgE; // FP <-> int convert flags //*** trim this
logic [63:0] ClassResE; // classify result
logic [63:0] CmpResE; // compare result
logic [`XLEN-1:0] ClassResE; // classify result
logic [`FLEN-1:0] CmpResE; // compare result
logic CmpNVE; // compare invalid flag (Not Valid)
logic [63:0] SgnResE; // sign injection result
logic [63:0] FResE, FResM, FResW; // selected result that is ready in the memory stage
logic [`FLEN-1:0] SgnResE; // sign injection result
logic [`FLEN-1:0] FResE, FResM, FResW; // selected result that is ready in the memory stage
logic [4:0] FFlgE, FFlgM; // selected flag that is ready in the memory stage
logic [`XLEN-1:0] FIntResE;
logic [63:0] FPUResultW; // final FP result being written to the FP register
logic [`FLEN-1:0] FPUResultW; // final FP result being written to the FP register
// other signals
logic FDivSqrtDoneE; // is divide done
logic [63:0] DivInput1E, DivInput2E; // inputs to divide/squareroot unit
logic load_preload; // enable for FF on fpdivsqrt
logic [63:0] AlignedSrcAE; // align SrcA to the floating point format
logic [63:0] BoxedZeroE; // Zero value for Z for multiplication, with NaN boxing if needed
logic [`FLEN-1:0] AlignedSrcAE; // align SrcA to the floating point format
logic [`FLEN-1:0] BoxedZeroE; // Zero value for Z for multiplication, with NaN boxing if needed
logic [`FLEN-1:0] BoxedOneE; // Zero value for Z for multiplication, with NaN boxing if needed
// DECODE STAGE
@ -144,12 +145,12 @@ module fpu (
.rd1(FRD1D), .rd2(FRD2D), .rd3(FRD3D));
// D/E pipeline registers
flopenrc #(64) DEReg1(clk, reset, FlushE, ~StallE, FRD1D, FRD1E);
flopenrc #(64) DEReg2(clk, reset, FlushE, ~StallE, FRD2D, FRD2E);
flopenrc #(64) DEReg3(clk, reset, FlushE, ~StallE, FRD3D, FRD3E);
flopenrc #(`FLEN) DEReg1(clk, reset, FlushE, ~StallE, FRD1D, FRD1E);
flopenrc #(`FLEN) DEReg2(clk, reset, FlushE, ~StallE, FRD2D, FRD2E);
flopenrc #(`FLEN) DEReg3(clk, reset, FlushE, ~StallE, FRD3D, FRD3E);
flopenrc #(15) DEAdrReg(clk, reset, FlushE, ~StallE, {InstrD[19:15], InstrD[24:20], InstrD[31:27]},
{Adr1E, Adr2E, Adr3E});
flopenrc #(16) DECtrlReg3(clk, reset, FlushE, ~StallE,
flopenrc #(16+int'(`FMTBITS-1)) DECtrlReg3(clk, reset, FlushE, ~StallE,
{FRegWriteD, FResultSelD, FResSelD, FIntResSelD, FrmD, FmtD, FOpCtrlD, FWriteIntD, FDivStartD},
{FRegWriteE, FResultSelE, FResSelE, FIntResSelE, FrmE, FmtE, FOpCtrlE, FWriteIntE, FDivStartE});
@ -160,17 +161,39 @@ module fpu (
.FStallD, .FForwardXE, .FForwardYE, .FForwardZE);
// forwarding muxs
mux3 #(64) fxemux (FRD1E, FPUResultW, FResM, FForwardXE, FSrcXE);
mux3 #(64) fyemux (FRD2E, FPUResultW, FResM, FForwardYE, FPreSrcYE);
mux3 #(64) fzemux (FRD3E, FPUResultW, FResM, FForwardZE, FPreSrcZE);
mux3 #(64) fyaddmux (FPreSrcYE, {{32{1'b1}}, 2'b0, {7{1'b1}}, 23'b0},
{2'b0, {10{1'b1}}, 52'b0},
{FmtE&FOpCtrlE[2]&FOpCtrlE[1]&(FResultSelE==2'b01), ~FmtE&FOpCtrlE[2]&FOpCtrlE[1]&(FResultSelE==2'b01)},
FSrcYE); // Force Z to be 0 for multiply instructions
mux3 #(`FLEN) fxemux (FRD1E, FPUResultW, FResM, FForwardXE, FSrcXE);
mux3 #(`FLEN) fyemux (FRD2E, FPUResultW, FResM, FForwardYE, FPreSrcYE);
mux3 #(`FLEN) fzemux (FRD3E, FPUResultW, FResM, FForwardZE, FPreSrcZE);
generate
if(`FPSIZES == 1) assign BoxedOneE = {2'b0, {`NE-1{1'b1}}, (`NF)'(0)};
else if(`FPSIZES == 2)
mux2 #(`FLEN) fonemux ({{`FLEN-`LEN1{1'b1}}, 2'b0, {`NE1-1{1'b1}}, (`NF1)'(0)}, {2'b0, {`NE-1{1'b1}}, (`NF)'(0)}, FmtE, BoxedOneE); // NaN boxing zeroes
else if(`FPSIZES == 3 | `FPSIZES == 4)
mux4 #(`FLEN) fonemux ({{`FLEN-`S_LEN{1'b1}}, 2'b0, {`S_NE-1{1'b1}}, (`S_NF)'(0)},
{{`FLEN-`D_LEN{1'b1}}, 2'b0, {`D_NE-1{1'b1}}, (`D_NF)'(0)},
{{`FLEN-`H_LEN{1'b1}}, 2'b0, {`H_NE-1{1'b1}}, (`H_NF)'(0)},
{2'b0, {`NE-1{1'b1}}, (`NF)'(0)}, FmtE, BoxedOneE); // NaN boxing zeroes
endgenerate
mux2 #(`FLEN) fyaddmux (FPreSrcYE, BoxedOneE, FOpCtrlE[2]&FOpCtrlE[1]&(FResultSelE==2'b01), FSrcYE); // Force Z to be 0 for multiply instructions
// Force Z to be 0 for multiply instructions
mux2 #(64) fmulzeromux (64'hFFFFFFFF00000000, 64'b0, FmtE, BoxedZeroE); // NaN boxing for 32-bit zero
mux3 #(64) fzmulmux (FPreSrcZE, BoxedZeroE, FPreSrcYE, {FOpCtrlE[2]&FOpCtrlE[1], FOpCtrlE[2]&~FOpCtrlE[1]}, FSrcZE);
generate
if(`FPSIZES == 1) assign BoxedZeroE = 0;
else if(`FPSIZES == 2)
mux2 #(`FLEN) fmulzeromux ({{`FLEN-`LEN1{1'b1}}, {`LEN1{1'b0}}}, (`FLEN)'(0), FmtE, BoxedZeroE); // NaN boxing zeroes
else if(`FPSIZES == 3 | `FPSIZES == 4)
mux4 #(`FLEN) fmulzeromux ({{`FLEN-`S_LEN{1'b1}}, {`S_LEN{1'b0}}},
{{`FLEN-`D_LEN{1'b1}}, {`D_LEN{1'b0}}},
{{`FLEN-`H_LEN{1'b1}}, {`H_LEN{1'b0}}},
(`FLEN)'(0), FmtE, BoxedZeroE); // NaN boxing zeroes
endgenerate
mux3 #(`FLEN) fzmulmux (FPreSrcZE, BoxedZeroE, FPreSrcYE, {FOpCtrlE[2]&FOpCtrlE[1], FOpCtrlE[2]&~FOpCtrlE[1]}, FSrcZE);
// unpack unit
// - splits FP inputs into their various parts
// - does some classifications (SNaN, NaN, Denorm, Norm, Zero, Infifnity)
@ -195,17 +218,27 @@ module fpu (
.FMAFlgM, .FMAResM);
// fpdivsqrt using Goldschmidt's iteration
flopenrc #(64) reg_input1 (.d({XSgnE, XExpE, XManE[51:0]}), .q(DivInput1E),
if(`FLEN == 64) begin
flopenrc #(64) reg_input1 (.d({FSrcXE[63:0]}), .q(DivInput1E),
.clear(FDivSqrtDoneE), .en(load_preload),
.reset(reset), .clk(clk));
flopenrc #(64) reg_input2 (.d({YSgnE, YExpE, YManE[51:0]}), .q(DivInput2E),
flopenrc #(64) reg_input2 (.d({FSrcYE[63:0]}), .q(DivInput2E),
.clear(FDivSqrtDoneE), .en(load_preload),
.reset(reset), .clk(clk));
flopenrc #(8) reg_input3 (.d({XNaNE, YNaNE, XInfE, YInfE, XZeroE, YZeroE, FmtE, FOpCtrlE[0]}),
end
else if (`FLEN == 32) begin
flopenrc #(64) reg_input1 (.d({32'b0, FSrcXE[31:0]}), .q(DivInput1E),
.clear(FDivSqrtDoneE), .en(load_preload),
.reset(reset), .clk(clk));
flopenrc #(64) reg_input2 (.d({32'b0, FSrcYE[31:0]}), .q(DivInput2E),
.clear(FDivSqrtDoneE), .en(load_preload),
.reset(reset), .clk(clk));
end
flopenrc #(8) reg_input3 (.d({XNaNE, YNaNE, XInfE, YInfE, XZeroE, YZeroE, FmtE[0], FOpCtrlE[0]}),
.q({XNaNQ, YNaNQ, XInfQ, YInfQ, XZeroQ, YZeroQ, FmtQ, FOpCtrlQ}),
.clear(FDivSqrtDoneE), .en(load_preload),
.reset(reset), .clk(clk));
fpdiv_pipe fdivsqrt (.op1(DivInput1E), .op2(DivInput2E), .rm(FrmE[1:0]), .op_type(FOpCtrlQ),
fpdiv_pipe fdivsqrt (.op1(DivInput1E[63:0]), .op2(DivInput2E[63:0]), .rm(FrmE[1:0]), .op_type(FOpCtrlQ),
.reset, .clk(clk), .start(FDivStartE), .P(~FmtQ), .OvEn(1'b1), .UnEn(1'b1),
.XNaNQ, .YNaNQ, .XInfQ, .YInfQ, .XZeroQ, .YZeroQ, .load_preload,
.FDivBusyE, .done(FDivSqrtDoneE), .AS_Result(FDivResM), .Flags(FDivFlgM));
@ -221,34 +254,47 @@ module fpu (
// data to be stored in memory - to IEU
// - FP uses NaN-blocking format
// - if there are any unsused bits the most significant bits are filled with 1s
assign FWriteDataE = FSrcYE[`XLEN-1:0];
// Align SrcA to MSB when single precicion
mux2 #(64) SrcAMux({{32{1'b1}}, ForwardedSrcAE[31:0]}, {{64-`XLEN{1'b1}}, ForwardedSrcAE}, FmtE, AlignedSrcAE);
if (`FLEN>`XLEN) assign FWriteDataE = FSrcYE[`XLEN-1:0];
else assign FWriteDataE = {{`XLEN-`FLEN{FSrcYE[`FLEN-1]}}, FSrcYE};
// NaN Block SrcA
generate
if(`FPSIZES == 1) assign AlignedSrcAE = {{`FLEN-`XLEN{1'b1}}, ForwardedSrcAE};
else if(`FPSIZES == 2)
mux2 #(`FLEN) SrcAMux ({{`FLEN-`LEN1{1'b1}}, ForwardedSrcAE[`LEN1-1:0]}, {{`FLEN-`XLEN{1'b1}}, ForwardedSrcAE}, FmtE, AlignedSrcAE);
else if(`FPSIZES == 3 | `FPSIZES == 4)
mux4 #(`FLEN) SrcAMux ({{`FLEN-`S_LEN{1'b1}}, ForwardedSrcAE[`S_LEN-1:0]},
{{`FLEN-`D_LEN{1'b1}}, ForwardedSrcAE[`D_LEN-1:0]},
{{`FLEN-`H_LEN{1'b1}}, ForwardedSrcAE[`H_LEN-1:0]},
{{`FLEN-`XLEN{1'b1}}, ForwardedSrcAE}, FmtE, AlignedSrcAE); // NaN boxing zeroes
endgenerate
// select a result that may be written to the FP register
mux4 #(64) FResMux(AlignedSrcAE, SgnResE, CmpResE, CvtResE, FResSelE, FResE);
mux4 #(`FLEN) FResMux(AlignedSrcAE, SgnResE, CmpResE, CvtResE, FResSelE, FResE);
mux4 #(5) FFlgMux(5'b0, 5'b0, {CmpNVE, 4'b0}, CvtFlgE, FResSelE, FFlgE);
// select the result that may be written to the integer register - to IEU
mux4 #(`XLEN) IntResMux(CmpResE[`XLEN-1:0], FSrcXE[`XLEN-1:0], ClassResE[`XLEN-1:0],
CvtIntResE, FIntResSelE, FIntResE);
if (`FLEN>`XLEN)
mux4 #(`XLEN) IntResMux(CmpResE[`XLEN-1:0], FSrcXE[`XLEN-1:0], ClassResE,
CvtIntResE, FIntResSelE, FIntResE);
else
mux4 #(`XLEN) IntResMux({{`XLEN-`FLEN{CmpResE[`FLEN-1:0]}}, CmpResE}, {{`XLEN-`FLEN{FSrcXE[`FLEN-1:0]}}, FSrcXE}, ClassResE,
CvtIntResE, FIntResSelE, FIntResE);
// *** DH 5/25/22: CvtRes will move to mem stage. Premux in execute to save area, then make sure stalls are ok
// *** make sure the fpu matches the chapter diagram
// E/M pipe registers
// flopenrc #(64) EMFpReg1(clk, reset, FlushM, ~StallM, FSrcXE, FSrcXM);
flopenrc #(54) EMFpReg2 (clk, reset, FlushM, ~StallM, {XSgnE,XManE}, {XSgnM,XManM});
flopenrc #(54) EMFpReg3 (clk, reset, FlushM, ~StallM, {YSgnE,YManE}, {YSgnM,YManM});
flopenrc #(64) EMFpReg4 (clk, reset, FlushM, ~StallM, {ZExpE,ZManE}, {ZExpM,ZManM});
flopenrc #(`NF+2) EMFpReg2 (clk, reset, FlushM, ~StallM, {XSgnE,XManE}, {XSgnM,XManM});
flopenrc #(`NF+2) EMFpReg3 (clk, reset, FlushM, ~StallM, {YSgnE,YManE}, {YSgnM,YManM});
flopenrc #(`FLEN) EMFpReg4 (clk, reset, FlushM, ~StallM, {ZExpE,ZManE}, {ZExpM,ZManM});
flopenrc #(12) EMFpReg5 (clk, reset, FlushM, ~StallM,
{XZeroE, YZeroE, ZZeroE, XInfE, YInfE, ZInfE, XNaNE, YNaNE, ZNaNE, XSNaNE, YSNaNE, ZSNaNE},
{XZeroM, YZeroM, ZZeroM, XInfM, YInfM, ZInfM, XNaNM, YNaNM, ZNaNM, XSNaNM, YSNaNM, ZSNaNM});
flopenrc #(64) EMRegCmpRes (clk, reset, FlushM, ~StallM, FResE, FResM);
flopenrc #(`FLEN) EMRegCmpRes (clk, reset, FlushM, ~StallM, FResE, FResM);
flopenrc #(5) EMRegCmpFlg (clk, reset, FlushM, ~StallM, FFlgE, FFlgM);
flopenrc #(`XLEN) EMRegSgnRes (clk, reset, FlushM, ~StallM, FIntResE, FIntResM);
flopenrc #(7) EMCtrlReg (clk, reset, FlushM, ~StallM,
flopenrc #(7+int'(`FMTBITS-1)) EMCtrlReg (clk, reset, FlushM, ~StallM,
{FRegWriteE, FResultSelE, FrmE, FmtE},
{FRegWriteM, FResultSelM, FrmM, FmtM});
@ -258,10 +304,10 @@ module fpu (
mux4 #(5) FPUFlgMux (5'b0, FMAFlgM, FDivFlgM, FFlgM, FResultSelM, SetFflagsM);
// M/W pipe registers
flopenrc #(64) MWRegFma(clk, reset, FlushW, ~StallW, FMAResM, FMAResW);
flopenrc #(`FLEN) MWRegFma(clk, reset, FlushW, ~StallW, FMAResM, FMAResW);
flopenrc #(64) MWRegDiv(clk, reset, FlushW, ~StallW, FDivResM, FDivResW);
flopenrc #(64) MWRegClass(clk, reset, FlushW, ~StallW, FResM, FResW);
flopenrc #(4) MWCtrlReg(clk, reset, FlushW, ~StallW,
flopenrc #(`FLEN) MWRegClass(clk, reset, FlushW, ~StallW, FResM, FResW);
flopenrc #(4+int'(`FMTBITS-1)) MWCtrlReg(clk, reset, FlushW, ~StallW,
{FRegWriteM, FResultSelM, FmtM},
{FRegWriteW, FResultSelW, FmtW});
@ -270,8 +316,18 @@ module fpu (
// put ReadData into NaN-blocking format
// - if there are any unsused bits the most significant bits are filled with 1s
// - for load instruction
mux2 #(64) ReadResMux ({{32{1'b1}}, ReadDataW[31:0]}, {{64-`XLEN{1'b1}}, ReadDataW}, FmtW, ReadResW);
generate
if(`FPSIZES == 1) assign ReadResW = {{`FLEN-`XLEN{1'b1}}, ReadDataW};
else if(`FPSIZES == 2)
mux2 #(`FLEN) SrcAMux ({{`FLEN-`LEN1{1'b1}}, ReadDataW[`LEN1-1:0]}, {{`FLEN-`XLEN{1'b1}}, ReadDataW}, FmtW, ReadResW);
else if(`FPSIZES == 3 | `FPSIZES == 4)
mux4 #(`FLEN) SrcAMux ({{`FLEN-`S_LEN{1'b1}}, ReadDataW[`S_LEN-1:0]},
{{`FLEN-`D_LEN{1'b1}}, ReadDataW[`D_LEN-1:0]},
{{`FLEN-`H_LEN{1'b1}}, ReadDataW[`H_LEN-1:0]},
{{`FLEN-`XLEN{1'b1}}, ReadDataW}, FmtW, ReadResW); // NaN boxing zeroes
endgenerate
// select the result to be written to the FP register
mux4 #(64) FPUResultMux (ReadResW, FMAResW, FDivResW, FResW, FResultSelW, FPUResultW);
if(`FLEN>=64)
mux4 #(`FLEN) FPUResultMux (ReadResW, FMAResW, {{`FLEN-64{1'b0}},FDivResW}, FResW, FResultSelW, FPUResultW);
endmodule // fpu

6
pipelined/src/fpu/fregfile.sv
View File

@ -33,10 +33,10 @@ module fregfile (
input logic clk, reset,
input logic we4,
input logic [4:0] a1, a2, a3, a4,
input logic [63:0] wd4,
output logic [63:0] rd1, rd2, rd3);
input logic [`FLEN-1:0] wd4,
output logic [`FLEN-1:0] rd1, rd2, rd3);
logic [63:0] rf[31:0];
logic [`FLEN-1:0] rf[31:0];
integer i;
// three ported register file

32
pipelined/src/fpu/fsgninj.sv
View File

@ -26,13 +26,14 @@
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
// OR OTHER DEALINGS IN THE SOFTWARE.
////////////////////////////////////////////////////////////////////////////////////////////////
`include "wally-config.vh"
module fsgninj (
input logic XSgnE, YSgnE, // X and Y sign bits
input logic [63:0] FSrcXE, // X
input logic FmtE, // precision 1 = double 0 = single
input logic [`FLEN-1:0] FSrcXE, // X
input logic [`FMTBITS-1:0] FmtE, // precision 1 = double 0 = single
input logic [1:0] SgnOpCodeE, // operation control
output logic [63:0] SgnResE // result
output logic [`FLEN-1:0] SgnResE // result
);
logic ResSgn;
@ -50,7 +51,30 @@ module fsgninj (
// format final result based on precision
// - uses NaN-blocking format
// - if there are any unsused bits the most significant bits are filled with 1s
assign SgnResE = FmtE ? {ResSgn, FSrcXE[62:0]} : {FSrcXE[63:32], ResSgn, FSrcXE[30:0]};
if (`FPSIZES == 1)
assign SgnResE = {ResSgn, FSrcXE[`FLEN-2:0]};
else if (`FPSIZES == 2)
assign SgnResE = FmtE ? {ResSgn, FSrcXE[`FLEN-2:0]} : {{`FLEN-`LEN1{1'b1}}, ResSgn, FSrcXE[`LEN1-2:0]};
else if (`FPSIZES == 3)
always_comb
case (FmtE)
`FMT: SgnResE = {ResSgn, FSrcXE[`FLEN-2:0]};
`FMT1: SgnResE = {{`FLEN-`LEN1{1'b1}}, ResSgn, FSrcXE[`LEN1-2:0]};
`FMT2: SgnResE = {{`FLEN-`LEN2{1'b1}}, ResSgn, FSrcXE[`LEN2-2:0]};
default: SgnResE = 0;
endcase
else if (`FPSIZES == 4)
always_comb
case (FmtE)
2'h3: SgnResE = {ResSgn, FSrcXE[`Q_LEN-2:0]};
2'h1: SgnResE = {{`Q_LEN-`D_LEN{1'b1}}, ResSgn, FSrcXE[`D_LEN-2:0]};
2'h0: SgnResE = {{`Q_LEN-`S_LEN{1'b1}}, ResSgn, FSrcXE[`S_LEN-2:0]};
2'h2: SgnResE = {{`Q_LEN-`H_LEN{1'b1}}, ResSgn, FSrcXE[`H_LEN-2:0]};
endcase
endmodule

2
pipelined/src/fpu/unpack.sv
View File

@ -2,7 +2,7 @@
module unpack (
input logic [`FLEN-1:0] X, Y, Z, // inputs from register file
input logic [`FPSIZES/3:0] FmtE, // format signal 00 - single 01 - double 11 - quad 10 - half
input logic [`FMTBITS-1:0] FmtE, // format signal 00 - single 01 - double 11 - quad 10 - half
output logic XSgnE, YSgnE, ZSgnE, // sign bits of XYZ
output logic [`NE-1:0] XExpE, YExpE, ZExpE, // exponents of XYZ (converted to largest supported precision)
output logic [`NF:0] XManE, YManE, ZManE, // mantissas of XYZ (converted to largest supported precision)

2
pipelined/src/fpu/unpackinput.sv
View File

@ -2,7 +2,7 @@
module unpackinput (
input logic [`FLEN-1:0] In, // inputs from register file
input logic [`FPSIZES/3:0] FmtE, // format signal 00 - single 01 - double 11 - quad 10 - half
input logic [`FMTBITS-1:0] FmtE, // format signal 00 - single 01 - double 11 - quad 10 - half
output logic Sgn, // sign bits of XYZ
output logic [`NE-1:0] Exp, // exponents of XYZ (converted to largest supported precision)
output logic [`NF:0] Man, // mantissas of XYZ (converted to largest supported precision)

2
pipelined/src/generic/lzc.sv
View File

@ -1,5 +1,5 @@
//leading zero counter i.e. priority encoder
module lzc #(parameter WIDTH=1) (
module lzc #(parameter WIDTH = 1) (
input logic [WIDTH-1:0] num,
output logic [$clog2(WIDTH+1)-1:0] ZeroCnt
);

15
pipelined/src/hazard/hazard.sv
View File

@ -32,13 +32,13 @@
module hazard(
// Detect hazards
(* mark_debug = "true" *) input logic BPPredWrongE, CSRWritePendingDEM, RetM, TrapM,
(* mark_debug = "true" *) input logic BPPredWrongE, CSRWriteFencePendingDEM, RetM, TrapM,
(* mark_debug = "true" *) input logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD,
(* mark_debug = "true" *) input logic LSUStallM, IFUStallF,
(* mark_debug = "true" *) input logic FPUStallD, FStallD,
(* mark_debug = "true" *) input logic DivBusyE,FDivBusyE,
(* mark_debug = "true" *) input logic EcallFaultM, BreakpointFaultM,
(* mark_debug = "true" *) input logic InvalidateICacheM, wfiM, IntPendingM,
(* mark_debug = "true" *) input logic wfiM, IntPendingM,
// Stall & flush outputs
(* mark_debug = "true" *) output logic StallF, StallD, StallE, StallM, StallW,
(* mark_debug = "true" *) output logic FlushF, FlushD, FlushE, FlushM, FlushW
@ -47,7 +47,6 @@ module hazard(
logic StallFCause, StallDCause, StallECause, StallMCause, StallWCause;
logic FirstUnstalledD, FirstUnstalledE, FirstUnstalledM, FirstUnstalledW;
// stalls and flushes
// loads: stall for one cycle if the subsequent instruction depends on the load
// branches and jumps: flush the next two instructions if the branch is taken in EXE
@ -62,7 +61,7 @@ module hazard(
// *** can stalls be pushed into earlier stages (e.g. no stall after Decode?)
assign StallFCause = CSRWritePendingDEM & ~(TrapM | RetM | BPPredWrongE);
assign StallFCause = CSRWriteFencePendingDEM & ~(TrapM | RetM | BPPredWrongE);
// stall in decode if instruction is a load/mul/csr dependent on previous
assign StallDCause = (LoadStallD | StoreStallD | MDUStallD | CSRRdStallD | FPUStallD | FStallD) & ~(TrapM | RetM | BPPredWrongE);
assign StallECause = (DivBusyE | FDivBusyE) & ~(TrapM); // *** can we move to decode stage (KP?)
@ -82,10 +81,10 @@ module hazard(
assign FirstUnstalledW = ~StallW & StallM;
// Each stage flushes if the previous stage is the last one stalled (for cause) or the system has reason to flush
assign FlushF = BPPredWrongE | InvalidateICacheM;
assign FlushD = FirstUnstalledD | TrapM | RetM | BPPredWrongE | InvalidateICacheM; // *** does RetM only need to flush if the privilege changes?
assign FlushE = FirstUnstalledE | TrapM | RetM | BPPredWrongE | InvalidateICacheM; // *** why is BPPredWrongE here, but not needed in simple processor
assign FlushM = FirstUnstalledM | TrapM | RetM | InvalidateICacheM;
assign FlushF = BPPredWrongE;
assign FlushD = FirstUnstalledD | TrapM | RetM | BPPredWrongE;
assign FlushE = FirstUnstalledE | TrapM | RetM | BPPredWrongE; // *** why is BPPredWrongE here, but not needed in simple processor
assign FlushM = FirstUnstalledM | TrapM | RetM;
// on Trap the memory stage should be flushed going into the W stage,
// except if the instruction causing the Trap is an ecall or ebreak.
assign FlushW = FirstUnstalledW | (TrapM & ~(BreakpointFaultM | EcallFaultM));

21
pipelined/src/ieu/controller.sv
View File

@ -67,7 +67,7 @@ module controller(
output logic RegWriteW, // for datapath and Hazard Unit
output logic [2:0] ResultSrcW,
// Stall during CSRs
output logic CSRWritePendingDEM,
output logic CSRWriteFencePendingDEM,
output logic StoreStallD
);
@ -107,6 +107,8 @@ module controller(
logic IEURegWriteE;
logic IllegalERegAdrD;
logic [1:0] AtomicE;
logic FencePendingD, FencePendingE, FencePendingM;
// Extract fields
assign OpD = InstrD[6:0];
@ -174,10 +176,10 @@ module controller(
assign {RegWriteD, ImmSrcD, ALUSrcAD, ALUSrcBD, MemRWD,
ResultSrcD, BranchD, ALUOpD, JumpD, ALUResultSrcD, W64D, CSRReadD,
PrivilegedD, FenceD, MDUD, AtomicD, unused} = IllegalIEUInstrFaultD ? `CTRLW'b0 : ControlsD;
// *** move Privileged, CSRwrite?? Or move controller out of IEU into datapath and handle all instructions
assign CSRZeroSrcD = InstrD[14] ? (InstrD[19:15] == 0) : (Rs1D == 0); // Is a CSR instruction using zero as the source?
assign CSRWriteD = CSRReadD & !(CSRZeroSrcD & InstrD[13]); // Don't write if setting or clearing zeros
assign FencePendingD = PrivilegedD & (InstrD[31:25] == 7'b0001001) | FenceD; // possible sfence.vma or fence.i
// ALU Decoding is lazy, only using func7[5] to distinguish add/sub and srl/sra
assign sltD = (Funct3D == 3'b010);
@ -204,9 +206,9 @@ module controller(
flopenrc #(1) controlregD(clk, reset, FlushD, ~StallD, 1'b1, InstrValidD);
// Execute stage pipeline control register and logic
flopenrc #(27) controlregE(clk, reset, FlushE, ~StallE,
{RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUControlD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, W64D, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, InstrValidD},
{IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUControlE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, InstrValidE});
flopenrc #(28) controlregE(clk, reset, FlushE, ~StallE,
{RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUControlD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, W64D, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FencePendingD, InstrValidD},
{IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUControlE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FencePendingE, InstrValidE});
// Branch Logic
assign {eqE, ltE, ltuE} = FlagsE;
@ -220,16 +222,17 @@ module controller(
assign RegWriteE = IEURegWriteE | FWriteIntE; // IRF register writes could come from IEU or FPU controllers
// Memory stage pipeline control register
flopenrc #(18) controlregM(clk, reset, FlushM, ~StallM,
{RegWriteE, ResultSrcE, MemRWE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, FWriteIntE, AtomicE, InvalidateICacheE, FlushDCacheE, InstrValidE},
{RegWriteM, ResultSrcM, MemRWM, CSRReadM, CSRWriteM, PrivilegedM, Funct3M, FWriteIntM, AtomicM, InvalidateICacheM, FlushDCacheM, InstrValidM});
flopenrc #(19) controlregM(clk, reset, FlushM, ~StallM,
{RegWriteE, ResultSrcE, MemRWE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, FWriteIntE, AtomicE, InvalidateICacheE, FlushDCacheE, FencePendingE, InstrValidE},
{RegWriteM, ResultSrcM, MemRWM, CSRReadM, CSRWriteM, PrivilegedM, Funct3M, FWriteIntM, AtomicM, InvalidateICacheM, FlushDCacheM, FencePendingM, InstrValidM});
// Writeback stage pipeline control register
flopenrc #(4) controlregW(clk, reset, FlushW, ~StallW,
{RegWriteM, ResultSrcM},
{RegWriteW, ResultSrcW});
assign CSRWritePendingDEM = CSRWriteD | CSRWriteE | CSRWriteM;
// Stall pipeline at Fetch if a CSR Write or Fence is pending in the subsequent stages
assign CSRWriteFencePendingDEM = CSRWriteD | CSRWriteE | CSRWriteM | FencePendingD | FencePendingE | FencePendingM;
assign StoreStallD = MemRWE[0] & ((|MemRWD) | (|AtomicD));
endmodule

4
pipelined/src/ieu/ieu.sv
View File

@ -71,7 +71,7 @@ module ieu (
output logic FPUStallD, LoadStallD, MDUStallD, CSRRdStallD,
output logic PCSrcE,
output logic CSRReadM, CSRWriteM, PrivilegedM,
output logic CSRWritePendingDEM,
output logic CSRWriteFencePendingDEM,
output logic StoreStallD
);
@ -99,7 +99,7 @@ module ieu (
.Funct3E, .MDUE, .W64E, .JumpE, .StallM, .FlushM, .MemRWM,
.CSRReadM, .CSRWriteM, .PrivilegedM, .SCE, .AtomicM, .Funct3M,
.RegWriteM, .InvalidateICacheM, .FlushDCacheM, .InstrValidM, .FWriteIntM,
.StallW, .FlushW, .RegWriteW, .ResultSrcW, .CSRWritePendingDEM, .StoreStallD);
.StallW, .FlushW, .RegWriteW, .ResultSrcW, .CSRWriteFencePendingDEM, .StoreStallD);
datapath dp(
.clk, .reset, .ImmSrcD, .InstrD, .StallE, .FlushE, .ForwardAE, .ForwardBE,

16
pipelined/src/ifu/ifu.sv
View File

@ -72,7 +72,7 @@ module ifu (
input logic [`XLEN-1:0] SATP_REGW,
input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
input logic [1:0] STATUS_MPP,
input logic ITLBWriteF, ITLBFlushF,
input logic ITLBWriteF, sfencevmaM,
output logic ITLBMissF, InstrDAPageFaultF,
input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0],
@ -137,6 +137,18 @@ module ifu (
////////////////////////////////////////////////////////////////////////////////////////////////
if(`ZICSR_SUPPORTED == 1) begin : immu
///////////////////////////////////////////
// sfence.vma causes TLB flushes
///////////////////////////////////////////
// sets ITLBFlush to pulse for one cycle of the sfence.vma instruction
// In this instr we want to flush the tlb and then do a pagetable walk to update the itlb and continue the program.
// But we're still in the stalled sfence instruction, so if itlbflushf == sfencevmaM, tlbflush would never drop and
// the tlbwrite would never take place after the pagetable walk. by adding in ~StallMQ, we are able to drop itlbflush
// after a cycle AND pulse it for another cycle on any further back-to-back sfences.
logic StallMQ, TLBFlush;
flopr #(1) StallMReg(.clk, .reset, .d(StallM), .q(StallMQ));
assign TLBFlush = sfencevmaM & ~StallMQ;
mmu #(.TLB_ENTRIES(`ITLB_ENTRIES), .IMMU(1))
immu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
.PrivilegeModeW, .DisableTranslation(1'b0),
@ -145,7 +157,7 @@ module ifu (
.PTE(PTE),
.PageTypeWriteVal(PageType),
.TLBWrite(ITLBWriteF),
.TLBFlush(ITLBFlushF),
.TLBFlush,
.PhysicalAddress(PCPF),
.TLBMiss(ITLBMissF),
.Cacheable(CacheableF), .Idempotent(), .AtomicAllowed(),

4
pipelined/src/lsu/lsu.sv
View File

@ -55,7 +55,7 @@ module lsu (
// cpu privilege
input logic [1:0] PrivilegeModeW,
input logic BigEndianM,
input logic DTLBFlushM,
input logic sfencevmaM,
// faults
output logic LoadPageFaultM, StoreAmoPageFaultM,
output logic LoadMisalignedFaultM, LoadAccessFaultM,
@ -157,7 +157,7 @@ module lsu (
.PTE,
.PageTypeWriteVal(PageType),
.TLBWrite(DTLBWriteM),
.TLBFlush(DTLBFlushM),
.TLBFlush(sfencevmaM),
.PhysicalAddress(LSUPAdrM),
.TLBMiss(DTLBMissM),
.Cacheable(CacheableM), .Idempotent(), .AtomicAllowed(),

117
pipelined/src/ppa/ppa.sv
View File

@ -478,10 +478,12 @@ module ppa_priorityencoder #(parameter WIDTH = 8) (
output logic [$clog2(WIDTH)-1:0] y);
int i;
always_comb
always_comb begin
y = 0;
for (i=0; i<WIDTH; i++) begin:pri
if (a[i]) y= i;
end
end
endmodule
module ppa_decoder_8 #(parameter WIDTH = 8) (
@ -531,15 +533,7 @@ module ppa_mux2_8 #(parameter WIDTH = 8) (
assign y = s ? d1 : d0;
endmodule
module ppa_mux3 #(parameter WIDTH = 8) (
input logic [WIDTH-1:0] d0, d1, d2,
input logic [1:0] s,
output logic [WIDTH-1:0] y);
assign y = s[1] ? d2 : (s[0] ? d1 : d0);
endmodule
module ppa_mux4 #(parameter WIDTH = 8) (
module ppa_mux4_8 #(parameter WIDTH = 8) (
input logic [WIDTH-1:0] d0, d1, d2, d3,
input logic [1:0] s,
output logic [WIDTH-1:0] y);
@ -547,15 +541,103 @@ module ppa_mux4 #(parameter WIDTH = 8) (
assign y = s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0);
endmodule
module ppa_mux6 #(parameter WIDTH = 8) (
input logic [WIDTH-1:0] d0, d1, d2, d3, d4, d5,
module ppa_mux8_8 #(parameter WIDTH = 8) (
input logic [WIDTH-1:0] d0, d1, d2, d3, d4, d5, d6, d7,
input logic [2:0] s,
output logic [WIDTH-1:0] y);
assign y = s[2] ? (s[0] ? d5 : d4) : (s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0));
assign y = s[2] ? (s[1] ? (s[0] ? d5 : d4) : (s[0] ? d6 : d7)) : (s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0));
endmodule
module ppa_mux8 #(parameter WIDTH = 8) (
module ppa_mux2_16 #(parameter WIDTH = 16) (
input logic [WIDTH-1:0] d0, d1,
input logic s,
output logic [WIDTH-1:0] y);
assign y = s ? d1 : d0;
endmodule
module ppa_mux4_16 #(parameter WIDTH = 16) (
input logic [WIDTH-1:0] d0, d1, d2, d3,
input logic [1:0] s,
output logic [WIDTH-1:0] y);
assign y = s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0);
endmodule
module ppa_mux8_16 #(parameter WIDTH = 16) (
input logic [WIDTH-1:0] d0, d1, d2, d3, d4, d5, d6, d7,
input logic [2:0] s,
output logic [WIDTH-1:0] y);
assign y = s[2] ? (s[1] ? (s[0] ? d5 : d4) : (s[0] ? d6 : d7)) : (s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0));
endmodule
module ppa_mux2_32 #(parameter WIDTH = 32) (
input logic [WIDTH-1:0] d0, d1,
input logic s,
output logic [WIDTH-1:0] y);
assign y = s ? d1 : d0;
endmodule
module ppa_mux4_32 #(parameter WIDTH = 32) (
input logic [WIDTH-1:0] d0, d1, d2, d3,
input logic [1:0] s,
output logic [WIDTH-1:0] y);
assign y = s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0);
endmodule
module ppa_mux8_32 #(parameter WIDTH = 32) (
input logic [WIDTH-1:0] d0, d1, d2, d3, d4, d5, d6, d7,
input logic [2:0] s,
output logic [WIDTH-1:0] y);
assign y = s[2] ? (s[1] ? (s[0] ? d5 : d4) : (s[0] ? d6 : d7)) : (s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0));
endmodule
module ppa_mux2_64 #(parameter WIDTH = 64) (
input logic [WIDTH-1:0] d0, d1,
input logic s,
output logic [WIDTH-1:0] y);
assign y = s ? d1 : d0;
endmodule
module ppa_mux4_64 #(parameter WIDTH = 64) (
input logic [WIDTH-1:0] d0, d1, d2, d3,
input logic [1:0] s,
output logic [WIDTH-1:0] y);
assign y = s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0);
endmodule
module ppa_mux8_64 #(parameter WIDTH = 64) (
input logic [WIDTH-1:0] d0, d1, d2, d3, d4, d5, d6, d7,
input logic [2:0] s,
output logic [WIDTH-1:0] y);
assign y = s[2] ? (s[1] ? (s[0] ? d5 : d4) : (s[0] ? d6 : d7)) : (s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0));
endmodule
module ppa_mux2_128 #(parameter WIDTH = 128) (
input logic [WIDTH-1:0] d0, d1,
input logic s,
output logic [WIDTH-1:0] y);
assign y = s ? d1 : d0;
endmodule
module ppa_mux4_128 #(parameter WIDTH = 128) (
input logic [WIDTH-1:0] d0, d1, d2, d3,
input logic [1:0] s,
output logic [WIDTH-1:0] y);
assign y = s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0);
endmodule
module ppa_mux8_128 #(parameter WIDTH = 128) (
input logic [WIDTH-1:0] d0, d1, d2, d3, d4, d5, d6, d7,
input logic [2:0] s,
output logic [WIDTH-1:0] y);
@ -867,4 +949,11 @@ module ppa_csa_128 #(parameter WIDTH = 128) (
assign sum = a ^ b ^ c;
assign carry = (a & (b | c)) | (b & c);
endmodule
module ppa_inv_1 #(parameter WIDTH = 1) (
input logic [WIDTH-1:0] a,
output logic [WIDTH-1:0] y);
assign y = ~a;
endmodule

8
pipelined/src/privileged/privdec.sv
View File

@ -39,7 +39,7 @@ module privdec (
input logic [1:0] PrivilegeModeW,
input logic STATUS_TSR, STATUS_TVM, STATUS_TW,
input logic [1:0] STATUS_FS,
output logic IllegalInstrFaultM, ITLBFlushF, DTLBFlushM,
output logic IllegalInstrFaultM,
output logic EcallFaultM, BreakpointFaultM,
output logic sretM, mretM, wfiM, sfencevmaM);
@ -84,9 +84,9 @@ module privdec (
// But we're still in the stalled sfence instruction, so if itlbflushf == sfencevmaM, tlbflush would never drop and
// the tlbwrite would never take place after the pagetable walk. by adding in ~StallMQ, we are able to drop itlbflush
// after a cycle AND pulse it for another cycle on any further back-to-back sfences.
flopr #(1) StallMReg(.clk, .reset, .d(StallM), .q(StallMQ));
assign ITLBFlushF = sfencevmaM & ~StallMQ;
assign DTLBFlushM = sfencevmaM;
// flopr #(1) StallMReg(.clk, .reset, .d(StallM), .q(StallMQ));
// assign ITLBFlushF = sfencevmaM & ~StallMQ;
// assign DTLBFlushM = sfencevmaM;
///////////////////////////////////////////
// Fault on illegal instructions

6
pipelined/src/privileged/privileged.sv
View File

@ -38,7 +38,7 @@ module privileged (
output logic [`XLEN-1:0] CSRReadValW,
output logic [`XLEN-1:0] PrivilegedNextPCM,
output logic RetM, TrapM,
output logic ITLBFlushF, DTLBFlushM,
output logic sfencevmaM,
input logic InstrValidM, CommittedM,
input logic FRegWriteM, LoadStallD,
input logic BPPredDirWrongM,
@ -85,7 +85,7 @@ module privileged (
logic [`XLEN-1:0] MEDELEG_REGW;
logic [11:0] MIDELEG_REGW;
logic sretM, mretM, sfencevmaM;
logic sretM, mretM;
logic IllegalCSRAccessM;
logic IllegalIEUInstrFaultM;
logic IllegalFPUInstrM;
@ -115,7 +115,7 @@ module privileged (
privdec pmd(.clk, .reset, .StallM, .InstrM(InstrM[31:20]),
.PrivilegedM, .IllegalIEUInstrFaultM, .IllegalCSRAccessM, .IllegalFPUInstrM,
.PrivilegeModeW, .STATUS_TSR, .STATUS_TVM, .STATUS_TW, .STATUS_FS, .IllegalInstrFaultM,
.ITLBFlushF, .DTLBFlushM, .EcallFaultM, .BreakpointFaultM,
.EcallFaultM, .BreakpointFaultM,
.sretM, .mretM, .wfiM, .sfencevmaM);
///////////////////////////////////////////

20
pipelined/src/wally/wallypipelinedcore.sv
View File

@ -82,7 +82,7 @@ module wallypipelinedcore (
logic StoreAmoMisalignedFaultM, StoreAmoAccessFaultM;
logic InvalidateICacheM, FlushDCacheM;
logic PCSrcE;
logic CSRWritePendingDEM;
logic CSRWriteFencePendingDEM;
logic DivBusyE;
logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD;
logic SquashSCW;
@ -101,7 +101,6 @@ module wallypipelinedcore (
// memory management unit signals
logic ITLBWriteF;
logic ITLBFlushF, DTLBFlushM;
logic ITLBMissF;
logic [`XLEN-1:0] SATP_REGW;
logic STATUS_MXR, STATUS_SUM, STATUS_MPRV;
@ -109,7 +108,7 @@ module wallypipelinedcore (
logic [1:0] PrivilegeModeW;
logic [`XLEN-1:0] PTE;
logic [1:0] PageType;
logic wfiM, IntPendingM;
logic sfencevmaM, wfiM, IntPendingM;
logic SelHPTW;
// PMA checker signals
@ -190,7 +189,7 @@ module wallypipelinedcore (
// mmu management
.PrivilegeModeW, .PTE, .PageType, .SATP_REGW,
.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV,
.STATUS_MPP, .ITLBWriteF, .ITLBFlushF,
.STATUS_MPP, .ITLBWriteF, .sfencevmaM,
.ITLBMissF,
// pmp/pma (inside mmu) signals. *** temporarily from AHB bus but eventually replace with internal versions pre H
@ -232,7 +231,7 @@ module wallypipelinedcore (
.FPUStallD, .LoadStallD, .MDUStallD, .CSRRdStallD,
.PCSrcE,
.CSRReadM, .CSRWriteM, .PrivilegedM,
.CSRWritePendingDEM, .StoreStallD
.CSRWriteFencePendingDEM, .StoreStallD
); // integer execution unit: integer register file, datapath and controller
@ -262,7 +261,7 @@ module wallypipelinedcore (
.STATUS_MPRV, // from csr
.STATUS_MPP, // from csr
.DTLBFlushM, // connects to privilege
.sfencevmaM, // connects to privilege
.LoadPageFaultM, // connects to privilege
.StoreAmoPageFaultM, // connects to privilege
.LoadMisalignedFaultM, // connects to privilege
@ -295,13 +294,13 @@ module wallypipelinedcore (
hazard hzu(
.BPPredWrongE, .CSRWritePendingDEM, .RetM, .TrapM,
.BPPredWrongE, .CSRWriteFencePendingDEM, .RetM, .TrapM,
.LoadStallD, .StoreStallD, .MDUStallD, .CSRRdStallD,
.LSUStallM, .IFUStallF,
.FPUStallD, .FStallD,
.DivBusyE, .FDivBusyE,
.EcallFaultM, .BreakpointFaultM,
.InvalidateICacheM, .wfiM, .IntPendingM,
.wfiM, .IntPendingM,
// Stall & flush outputs
.StallF, .StallD, .StallE, .StallM, .StallW,
.FlushF, .FlushD, .FlushE, .FlushM, .FlushW
@ -315,7 +314,7 @@ module wallypipelinedcore (
.CSRReadM, .CSRWriteM, .SrcAM, .PCM,
.InstrM, .CSRReadValW, .PrivilegedNextPCM,
.RetM, .TrapM,
.ITLBFlushF, .DTLBFlushM,
.sfencevmaM,
.InstrValidM, .CommittedM,
.FRegWriteM, .LoadStallD,
.BPPredDirWrongM, .BTBPredPCWrongM,
@ -344,8 +343,7 @@ module wallypipelinedcore (
assign RetM = 0;
assign TrapM = 0;
assign wfiM = 0;
assign ITLBFlushF = 0;
assign DTLBFlushM = 0;
assign sfencevmaM = 0;
assign BigEndianM = 0;
end
if (`M_SUPPORTED) begin:mdu

2
pipelined/srt/srt.do
View File

@ -17,7 +17,7 @@ if [file exists work] {
}
vlib work
vlog +incdir+../config/rv64gc +incdir+../config/shared srt.sv testbench.sv ../src/generic/flop/flop*.sv ../src/generic/mux.sv
vlog +incdir+../config/rv64gc +incdir+../config/shared srt.sv testbench.sv ../src/generic/flop/flop*.sv ../src/generic/mux.sv ../src/generic/lzc.sv
vopt +acc work.testbench -o workopt
vsim workopt

208
pipelined/srt/srt.sv
View File

@ -30,7 +30,11 @@
`include "wally-config.vh"
module srt #(parameter Nf=52) (
`define DIVLEN ((`NF<(`XLEN+1)) ? (`XLEN + 1) : `NF)
`define EXTRAFRACBITS ((`NF<(`XLEN+1)) ? (`XLEN - `NF + 1) : 0)
`define EXTRAINTBITS ((`NF<(`XLEN+1)) ? 0 : (`NF - `XLEN))
module srt (
input logic clk,
input logic Start,
input logic Stall, // *** multiple pipe stages
@ -39,7 +43,7 @@ module srt #(parameter Nf=52) (
// later add exponents, signs, special cases
input logic XSign, YSign,
input logic [`NE-1:0] XExp, YExp,
input logic [Nf-1:0] SrcXFrac, SrcYFrac,
input logic [`NF-1:0] SrcXFrac, SrcYFrac,
input logic [`XLEN-1:0] SrcA, SrcB,
input logic [1:0] Fmt, // Floats: 00 = 16 bit, 01 = 32 bit, 10 = 64 bit, 11 = 128 bit
input logic W64, // 32-bit ints on XLEN=64
@ -47,7 +51,7 @@ module srt #(parameter Nf=52) (
input logic Int, // Choose integer inputs
input logic Sqrt, // perform square root, not divide
output logic rsign,
output logic [Nf-1:0] Quot, Rem, QuotOTFC, // *** later handle integers
output logic [`DIVLEN-1:0] Quot, Rem, QuotOTFC, // *** later handle integers
output logic [`NE-1:0] rExp,
output logic [3:0] Flags
);
@ -55,38 +59,40 @@ module srt #(parameter Nf=52) (
logic qp, qz, qm; // quotient is +1, 0, or -1
logic [`NE-1:0] calcExp;
logic calcSign;
logic [Nf-1:0] X, Dpreproc;
logic [Nf+3:0] WS, WSA, WSN, WC, WCA, WCN, D, Db, Dsel;
logic [Nf+2:0] rp, rm;
logic [`DIVLEN-1:0] X, Dpreproc;
logic [`DIVLEN+3:0] WS, WSA, WSN, WC, WCA, WCN, D, Db, Dsel;
logic [`DIVLEN+2:0] rp, rm;
logic [$clog2(`XLEN+1)-1:0] intExp;
logic intSign;
srtpreproc #(Nf) preproc(SrcA, SrcB, SrcXFrac, SrcYFrac, Fmt, W64, Signed, Int, Sqrt, X, Dpreproc);
srtpreproc preproc(SrcA, SrcB, SrcXFrac, SrcYFrac, Fmt, W64, Signed, Int, Sqrt, X, Dpreproc, intExp, intSign);
// Top Muxes and Registers
// When start is asserted, the inputs are loaded into the divider.
// Otherwise, the divisor is retained and the partial remainder
// is fed back for the next iteration.
mux2 #(Nf+4) wsmux({WSA[54:0], 1'b0}, {4'b0001, X}, Start, WSN);
flop #(Nf+4) wsflop(clk, WSN, WS);
mux2 #(Nf+4) wcmux({WCA[54:0], 1'b0}, 56'b0, Start, WCN);
flop #(Nf+4) wcflop(clk, WCN, WC);
flopen #(Nf+4) dflop(clk, Start, {4'b0001, Dpreproc}, D);
mux2 #(`DIVLEN+4) wsmux({WSA[`DIVLEN+2:0], 1'b0}, {4'b0001, X}, Start, WSN);
flop #(`DIVLEN+4) wsflop(clk, WSN, WS);
mux2 #(`DIVLEN+4) wcmux({WCA[`DIVLEN+2:0], 1'b0}, {(`DIVLEN+4){1'b0}}, Start, WCN);
flop #(`DIVLEN+4) wcflop(clk, WCN, WC);
flopen #(`DIVLEN+4) dflop(clk, Start, {4'b0001, Dpreproc}, D);
// Quotient Selection logic
// Given partial remainder, select quotient of +1, 0, or -1 (qp, qz, pm)
// Accumulate quotient digits in a shift register
qsel #(Nf) qsel(WS[55:52], WC[55:52], qp, qz, qm);
qacc #(Nf+3) qacc(clk, Start, qp, qz, qm, rp, rm);
qsel2 qsel2(WS[`DIVLEN+3:`DIVLEN], WC[`DIVLEN+3:`DIVLEN], qp, qz, qm);
// Accumulate quotient digits in a shift register (now done in OTFC)
qacc #(`DIVLEN+3) qacc(clk, Start, qp, qz, qm, rp, rm);
flopen #(`NE) expflop(clk, Start, calcExp, rExp);
flopen #(1) signflop(clk, Start, calcSign, rsign);
// Divisor Selection logic
inv dinv(D, Db);
mux3onehot divisorsel(Db, 56'b0, D, qp, qz, qm, Dsel);
mux3onehot #(`DIVLEN) divisorsel(Db, {(`DIVLEN+4){1'b0}}, D, qp, qz, qm, Dsel);
// Partial Product Generation
csa csa(WS, WC, Dsel, qp, WSA, WCA);
csa #(`DIVLEN+4) csa(WS, WC, Dsel, qp, WSA, WCA);
otfc2 otfc2(clk, Start, qp, qz, qm, QuotOTFC);
otfc2 #(`DIVLEN) otfc2(clk, Start, qp, qz, qm, QuotOTFC);
expcalc expcalc(.XExp, .YExp, .calcExp);
@ -95,70 +101,60 @@ module srt #(parameter Nf=52) (
srtpostproc postproc(rp, rm, Quot);
endmodule
module srtpostproc #(parameter N=52) (
input [N+2:0] rp, rm,
output [N-1:0] Quot
);
////////////////
// Submodules //
////////////////
//assign Quot = rp - rm;
finaladd finaladd(rp, rm, Quot);
endmodule
module srtpreproc #(parameter Nf=52) (
///////////////////
// Preprocessing //
///////////////////
module srtpreproc (
input logic [`XLEN-1:0] SrcA, SrcB,
input logic [Nf-1:0] SrcXFrac, SrcYFrac,
input logic [`NF-1:0] SrcXFrac, SrcYFrac,
input logic [1:0] Fmt, // Floats: 00 = 16 bit, 01 = 32 bit, 10 = 64 bit, 11 = 128 bit
input logic W64, // 32-bit ints on XLEN=64
input logic Signed, // Interpret integers as signed 2's complement
input logic Int, // Choose integer inputss
input logic Int, // Choose integer inputs
input logic Sqrt, // perform square root, not divide
output logic [Nf-1:0] X, D
output logic [`DIVLEN-1:0] X, D,
output logic [$clog2(`XLEN+1)-1:0] intExp, // Quotient integer exponent
output logic intSign // Quotient integer sign
);
// Initial: just pass X and Y through for simple fp division
assign X = SrcXFrac;
assign D = SrcYFrac;
logic [$clog2(`XLEN+1)-1:0] zeroCntA, zeroCntB;
logic [`XLEN-1:0] PosA, PosB;
logic [`DIVLEN-1:0] ExtraA, ExtraB, PreprocA, PreprocB, PreprocX, PreprocY;
assign PosA = (Signed & SrcA[`XLEN - 1]) ? -SrcA : SrcA;
assign PosB = (Signed & SrcB[`XLEN - 1]) ? -SrcB : SrcB;
lzc #(`XLEN) lzcA (PosA, zeroCntA);
lzc #(`XLEN) lzcB (PosB, zeroCntB);
assign ExtraA = {1'b0, PosA, {`EXTRAINTBITS{1'b0}}};
assign ExtraB = {1'b0, PosB, {`EXTRAINTBITS{1'b0}}};
assign PreprocA = ExtraA << zeroCntA;
assign PreprocB = ExtraB << (zeroCntB + 1);
assign PreprocX = {SrcXFrac, {`EXTRAFRACBITS{1'b0}}};
assign PreprocY = {SrcYFrac, {`EXTRAFRACBITS{1'b0}}};
assign X = Int ? PreprocA : PreprocX;
assign D = Int ? PreprocB : PreprocY;
assign intExp = zeroCntB - zeroCntA + 1;
assign intSign = Signed & (SrcA[`XLEN - 1] ^ SrcB[`XLEN - 1]);
endmodule
/*
//////////
// mux2 //
//////////
module mux2(input logic [55:0] in0, in1,
input logic sel,
output logic [55:0] out);
assign #1 out = sel ? in1 : in0;
endmodule
//////////
// flop //
//////////
module flop(clk, in, out);
input clk;
input [55:0] in;
output [55:0] out;
logic [55:0] state;
always @(posedge clk)
state <= #1 in;
assign #1 out = state;
endmodule
*/
//////////
// qsel //
//////////
module qsel #(parameter Nf=52) ( // *** eventually just change to 4 bits
input logic [Nf+3:Nf] ps, pc,
/////////////////////////////////
// Quotient Selection, Radix 2 //
/////////////////////////////////
module qsel2 ( // *** eventually just change to 4 bits
input logic [`DIVLEN+3:`DIVLEN] ps, pc,
output logic qp, qz, qm
);
logic [Nf+3:Nf] p, g;
logic [`DIVLEN+3:`DIVLEN] p, g;
logic magnitude, sign, cout;
// The quotient selection logic is presented for simplicity, not
@ -169,9 +165,9 @@ module qsel #(parameter Nf=52) ( // *** eventually just change to 4 bits
assign p = ps ^ pc;
assign g = ps & pc;
assign #1 magnitude = ~(&p[54:52]);
assign #1 cout = g[54] | (p[54] & (g[53] | p[53] & g[52]));
assign #1 sign = p[55] ^ cout;
assign #1 magnitude = ~(&p[`DIVLEN+2:`DIVLEN]);
assign #1 cout = g[`DIVLEN+2] | (p[`DIVLEN+2] & (g[`DIVLEN+1] | p[`DIVLEN+1] & g[`DIVLEN]));
assign #1 sign = p[`DIVLEN+3] ^ cout;
/* assign #1 magnitude = ~((ps[54]^pc[54]) & (ps[53]^pc[53]) &
(ps[52]^pc[52]));
assign #1 sign = (ps[55]^pc[55])^
@ -188,15 +184,16 @@ endmodule
//////////
// qacc //
//////////
module qacc #(parameter N=55) (
// To be replaced by OTFC
module qacc #(parameter N=68) (
input logic clk,
input logic req,
input logic qp, qz, qm,
output logic [N-1:0] rp, rm
);
flopr #(N) rmreg(clk, req, {rm[53:0], qm}, rm);
flopr #(N) rpreg(clk, req, {rp[53:0], qp}, rp);
flopr #(N) rmreg(clk, req, {rm[N-2:0], qm}, rm);
flopr #(N) rpreg(clk, req, {rp[N-2:0], qp}, rp);
/* always @(posedge clk)
begin
if (req)
@ -212,11 +209,10 @@ module qacc #(parameter N=55) (
end */
endmodule
//////////
// otfc //
//////////
module otfc2 #(parameter N=52) (
///////////////////////////////////
// On-The-Fly Converter, Radix 2 //
///////////////////////////////////
module otfc2 #(parameter N=65) (
input logic clk,
input logic Start,
input logic qp, qz, qm,
@ -255,16 +251,15 @@ module otfc2 #(parameter N=52) (
QMNext = {QMR, 1'b0};
end
end
assign r = Q[54] ? Q[53:2] : Q[52:1];
assign r = Q[N+2] ? Q[N+1:2] : Q[N:1];
endmodule
/////////
// inv //
/////////
module inv(input logic [55:0] in,
output logic [55:0] out);
module inv(input logic [`DIVLEN+3:0] in,
output logic [`DIVLEN+3:0] out);
assign #1 out = ~in;
endmodule
@ -272,14 +267,11 @@ endmodule
//////////
// mux3 //
//////////
module mux3onehot(in0, in1, in2, sel0, sel1, sel2, out);
input [55:0] in0;
input [55:0] in1;
input [55:0] in2;
input sel0;
input sel1;
input sel2;
output [55:0] out;
module mux3onehot #(parameter N=65) (
input logic [N+3:0] in0, in1, in2,
input logic sel0, sel1, sel2,
output logic [N+3:0] out
);
// lazy inspection of the selects
// really we should make sure selects are mutually exclusive
@ -290,7 +282,7 @@ endmodule
/////////
// csa //
/////////
module csa #(parameter N=56) (
module csa #(parameter N=69) (
input logic [N-1:0] in1, in2, in3,
input logic cin,
output logic [N-1:0] out1, out2
@ -305,28 +297,26 @@ module csa #(parameter N=56) (
// insert cin.
assign #1 out1 = in1 ^ in2 ^ in3;
assign #1 out2 = {in1[54:0] & (in2[54:0] | in3[54:0]) |
(in2[54:0] & in3[54:0]), cin};
assign #1 out2 = {in1[N-2:0] & (in2[N-2:0] | in3[N-2:0]) |
(in2[N-2:0] & in3[N-2:0]), cin};
endmodule
//////////////
// expcalc //
//////////////
module expcalc(
input logic [`NE-1:0] XExp, YExp,
output logic [`NE-1:0] calcExp
);
assign calcExp = XExp - YExp + 11'b01111111111;
assign calcExp = XExp - YExp + (`NE)'(`BIAS);
endmodule
//////////////
// signcalc //
//////////////
module signcalc(
input logic XSign, YSign,
output logic calcSign
@ -336,15 +326,27 @@ module signcalc(
endmodule
////////////////////
// Postprocessing //
////////////////////
module srtpostproc (
input [`DIVLEN+2:0] rp, rm,
output [`DIVLEN-1:0] Quot
);
//assign Quot = rp - rm;
finaladd #(`DIVLEN+3) finaladd(rp, rm, Quot);
endmodule
//////////////
// finaladd //
//////////////
module finaladd(
input logic [54:0] rp, rm,
output logic [51:0] r
module finaladd #(parameter N=68) (
input logic [N-1:0] rp, rm,
output logic [N-4:0] r
);
logic [54:0] diff;
logic [N-1:0] diff;
// this magic block performs the final addition for you
// to convert the positive and negative quotient digits
@ -359,6 +361,6 @@ module finaladd(
// The checker ignores such an error.
assign #1 diff = rp - rm;
assign #1 r = diff[54] ? diff[53:2] : diff[52:1];
assign #1 r = diff[N-1] ? diff[N-2:2] : diff[N-3:1];
endmodule

27
pipelined/srt/testbench.sv
View File

@ -1,3 +1,5 @@
`define DIVLEN 65
/////////////
// counter //
/////////////
@ -37,15 +39,16 @@ endmodule
// testbench //
//////////
module testbench;
logic clk;
logic req;
logic done;
logic [63:0] a, b;
logic [51:0] afrac, bfrac;
logic [10:0] aExp, bExp;
logic asign, bsign;
logic [51:0] r, rOTFC;
logic [54:0] rp, rm; // positive quotient digits
logic clk;
logic req;
logic done;
logic [63:0] a, b;
logic [51:0] afrac, bfrac;
logic [10:0] aExp, bExp;
logic asign, bsign;
logic [51:0] r, rOTFC;
logic [`DIVLEN-1:0] Quot, QuotOTFC;
logic [54:0] rp, rm; // positive quotient digits
// Test parameters
parameter MEM_SIZE = 40000;
@ -65,14 +68,14 @@ module testbench;
integer testnum, errors;
// Divider
srt #(52) srt(.clk, .Start(req),
srt srt(.clk, .Start(req),
.Stall(1'b0), .Flush(1'b0),
.XExp(aExp), .YExp(bExp), .rExp,
.XSign(asign), .YSign(bsign), .rsign,
.SrcXFrac(afrac), .SrcYFrac(bfrac),
.SrcA('0), .SrcB('0), .Fmt(2'b00),
.W64(1'b0), .Signed(1'b0), .Int(1'b0), .Sqrt(1'b0),
.Quot(r), .QuotOTFC(rOTFC), .Rem(), .Flags());
.Quot, .QuotOTFC, .Rem(), .Flags());
// Counter
counter counter(clk, req, done);
@ -98,6 +101,8 @@ module testbench;
b = Vec[`memb];
{bsign, bExp, bfrac} = b;
nextr = Vec[`memr];
r = Quot[`DIVLEN:`DIVLEN - 52];
rOTFC = QuotOTFC[`DIVLEN:`DIVLEN - 52];
req <= #5 1;
end

357
pipelined/testbench/testbench-fp.sv
View File

@ -25,9 +25,11 @@ module testbenchfp;
logic clk=0;
logic [31:0] TestNum=0; // index for the test
logic [31:0] FmaTestNum=0; // index for the test
logic [31:0] OpCtrlNum=0; // index for OpCtrl
logic [31:0] errors=0; // how many errors
logic [31:0] VectorNum=0; // index for test vector
logic [31:0] FmaVectorNum=0; // index for test vector
logic [31:0] FrmNum=0; // index for rounding mode
logic [`FLEN*4+7:0] TestVectors[46464:0]; // list of test vectors
logic [`FLEN*4+7:0] FmaRneVectors[6133248:0]; // list of fma rne test vectors
@ -54,7 +56,7 @@ module testbenchfp;
logic [4:0] FmaRneAnsFlg, FmaRzAnsFlg, FmaRuAnsFlg, FmaRdAnsFlg, FmaRnmAnsFlg; // flags read form testfloat
logic [4:0] ResFlg; // Result flags
logic [4:0] FmaRneResFlg, FmaRzResFlg, FmaRuResFlg, FmaRdResFlg, FmaRnmResFlg; // flags read form testfloat
logic [`FPSIZES/3:0] ModFmt, FmaModFmt; // format - 10 = half, 00 = single, 01 = double, 11 = quad
logic [`FMTBITS-1:0] ModFmt, FmaModFmt; // format - 10 = half, 00 = single, 01 = double, 11 = quad
logic [`FLEN-1:0] FmaRes, DivRes, CmpRes, CvtRes; // Results from each unit
logic [`XLEN-1:0] CvtIntRes; // Results from each unit
logic [4:0] FmaFlg, CvtFlg, DivFlg, CmpFlg; // Outputed flags
@ -259,26 +261,26 @@ module testbenchfp;
Fmt = {Fmt, 2'b11};
end
end
if (TEST === "div" | TEST === "all") begin // if division is being tested
// add the divide tests/op-ctrls/unit/fmt
Tests = {Tests, f128div};
OpCtrl = {OpCtrl, `DIV_OPCTRL};
WriteInt = {WriteInt, 1'b0};
for(int i = 0; i<5; i++) begin
Unit = {Unit, `DIVUNIT};
Fmt = {Fmt, 2'b11};
end
end
if (TEST === "sqrt" | TEST === "all") begin // if square-root is being tested
// add the square-root tests/op-ctrls/unit/fmt
Tests = {Tests, f128sqrt};
OpCtrl = {OpCtrl, `SQRT_OPCTRL};
WriteInt = {WriteInt, 1'b0};
for(int i = 0; i<5; i++) begin
Unit = {Unit, `DIVUNIT};
Fmt = {Fmt, 2'b11};
end
end
// if (TEST === "div" | TEST === "all") begin // if division is being tested
// // add the divide tests/op-ctrls/unit/fmt
// Tests = {Tests, f128div};
// OpCtrl = {OpCtrl, `DIV_OPCTRL};
// WriteInt = {WriteInt, 1'b0};
// for(int i = 0; i<5; i++) begin
// Unit = {Unit, `DIVUNIT};
// Fmt = {Fmt, 2'b11};
// end
// end
// if (TEST === "sqrt" | TEST === "all") begin // if square-root is being tested
// // add the square-root tests/op-ctrls/unit/fmt
// Tests = {Tests, f128sqrt};
// OpCtrl = {OpCtrl, `SQRT_OPCTRL};
// WriteInt = {WriteInt, 1'b0};
// for(int i = 0; i<5; i++) begin
// Unit = {Unit, `DIVUNIT};
// Fmt = {Fmt, 2'b11};
// end
// end
if (TEST === "fma" | TEST === "all") begin // if fused-mutliply-add is being tested
// add each rounding mode to it's own list of tests
// - fma tests are very long, so run all rounding modes in parallel
@ -388,26 +390,26 @@ module testbenchfp;
Fmt = {Fmt, 2'b01};
end
end
if (TEST === "div" | TEST === "all") begin // if division is being tested
// add the correct tests/op-ctrls/unit/fmt to their lists
Tests = {Tests, f64div};
OpCtrl = {OpCtrl, `DIV_OPCTRL};
WriteInt = {WriteInt, 1'b0};
for(int i = 0; i<5; i++) begin
Unit = {Unit, `DIVUNIT};
Fmt = {Fmt, 2'b01};
end
end
if (TEST === "sqrt" | TEST === "all") begin // if square-root is being tessted
// add the correct tests/op-ctrls/unit/fmt to their lists
Tests = {Tests, f64sqrt};
OpCtrl = {OpCtrl, `SQRT_OPCTRL};
WriteInt = {WriteInt, 1'b0};
for(int i = 0; i<5; i++) begin
Unit = {Unit, `DIVUNIT};
Fmt = {Fmt, 2'b01};
end
end
// if (TEST === "div" | TEST === "all") begin // if division is being tested
// // add the correct tests/op-ctrls/unit/fmt to their lists
// Tests = {Tests, f64div};
// OpCtrl = {OpCtrl, `DIV_OPCTRL};
// WriteInt = {WriteInt, 1'b0};
// for(int i = 0; i<5; i++) begin
// Unit = {Unit, `DIVUNIT};
// Fmt = {Fmt, 2'b01};
// end
// end
// if (TEST === "sqrt" | TEST === "all") begin // if square-root is being tessted
// // add the correct tests/op-ctrls/unit/fmt to their lists
// Tests = {Tests, f64sqrt};
// OpCtrl = {OpCtrl, `SQRT_OPCTRL};
// WriteInt = {WriteInt, 1'b0};
// for(int i = 0; i<5; i++) begin
// Unit = {Unit, `DIVUNIT};
// Fmt = {Fmt, 2'b01};
// end
// end
if (TEST === "fma" | TEST === "all") begin // if the fused multiply add is being tested
// add each rounding mode to it's own list of tests
// - fma tests are very long, so run all rounding modes in parallel
@ -500,26 +502,26 @@ module testbenchfp;
Fmt = {Fmt, 2'b00};
end
end
if (TEST === "div" | TEST === "all") begin // if division is being tested
// add the correct tests/op-ctrls/unit/fmt to their lists
Tests = {Tests, f32div};
OpCtrl = {OpCtrl, `DIV_OPCTRL};
WriteInt = {WriteInt, 1'b0};
for(int i = 0; i<5; i++) begin
Unit = {Unit, `DIVUNIT};
Fmt = {Fmt, 2'b00};
end
end
if (TEST === "sqrt" | TEST === "all") begin // if sqrt is being tested
// add the correct tests/op-ctrls/unit/fmt to their lists
Tests = {Tests, f32sqrt};
OpCtrl = {OpCtrl, `SQRT_OPCTRL};
WriteInt = {WriteInt, 1'b0};
for(int i = 0; i<5; i++) begin
Unit = {Unit, `DIVUNIT};
Fmt = {Fmt, 2'b00};
end
end
// if (TEST === "div" | TEST === "all") begin // if division is being tested
// // add the correct tests/op-ctrls/unit/fmt to their lists
// Tests = {Tests, f32div};
// OpCtrl = {OpCtrl, `DIV_OPCTRL};
// WriteInt = {WriteInt, 1'b0};
// for(int i = 0; i<5; i++) begin
// Unit = {Unit, `DIVUNIT};
// Fmt = {Fmt, 2'b00};
// end
// end
// if (TEST === "sqrt" | TEST === "all") begin // if sqrt is being tested
// // add the correct tests/op-ctrls/unit/fmt to their lists
// Tests = {Tests, f32sqrt};
// OpCtrl = {OpCtrl, `SQRT_OPCTRL};
// WriteInt = {WriteInt, 1'b0};
// for(int i = 0; i<5; i++) begin
// Unit = {Unit, `DIVUNIT};
// Fmt = {Fmt, 2'b00};
// end
// end
if (TEST === "fma" | TEST === "all") begin // if fma is being tested
// add each rounding mode to it's own list of tests
// - fma tests are very long, so run all rounding modes in parallel
@ -594,26 +596,26 @@ module testbenchfp;
Fmt = {Fmt, 2'b10};
end
end
if (TEST === "div" | TEST === "all") begin // if division is being tested
// add the correct tests/op-ctrls/unit/fmt to their lists
Tests = {Tests, f16div};
OpCtrl = {OpCtrl, `DIV_OPCTRL};
WriteInt = {WriteInt, 1'b0};
for(int i = 0; i<5; i++) begin
Unit = {Unit, `DIVUNIT};
Fmt = {Fmt, 2'b10};
end
end
if (TEST === "sqrt" | TEST === "all") begin // if sqrt is being tested
// add the correct tests/op-ctrls/unit/fmt to their lists
Tests = {Tests, f16sqrt};
OpCtrl = {OpCtrl, `SQRT_OPCTRL};
WriteInt = {WriteInt, 1'b0};
for(int i = 0; i<5; i++) begin
Unit = {Unit, `DIVUNIT};
Fmt = {Fmt, 2'b10};
end
end
// if (TEST === "div" | TEST === "all") begin // if division is being tested
// // add the correct tests/op-ctrls/unit/fmt to their lists
// Tests = {Tests, f16div};
// OpCtrl = {OpCtrl, `DIV_OPCTRL};
// WriteInt = {WriteInt, 1'b0};
// for(int i = 0; i<5; i++) begin
// Unit = {Unit, `DIVUNIT};
// Fmt = {Fmt, 2'b10};
// end
// end
// if (TEST === "sqrt" | TEST === "all") begin // if sqrt is being tested
// // add the correct tests/op-ctrls/unit/fmt to their lists
// Tests = {Tests, f16sqrt};
// OpCtrl = {OpCtrl, `SQRT_OPCTRL};
// WriteInt = {WriteInt, 1'b0};
// for(int i = 0; i<5; i++) begin
// Unit = {Unit, `DIVUNIT};
// Fmt = {Fmt, 2'b10};
// end
// end
if (TEST === "fma" | TEST === "all") begin // if fma is being tested
// add each rounding mode to it's own list of tests
// - fma tests are very long, so run all rounding modes in parallel
@ -646,18 +648,20 @@ module testbenchfp;
// Read the first test
initial begin
$display("\n\nRunning %s vectors", Tests[TestNum]);
$display("Running FMA precision %d", FmaTestNum);
$readmemh({`PATH, Tests[TestNum]}, TestVectors);
$readmemh({`PATH, FmaRneTests[TestNum]}, FmaRneVectors);
$readmemh({`PATH, FmaRuTests[TestNum]}, FmaRuVectors);
$readmemh({`PATH, FmaRdTests[TestNum]}, FmaRdVectors);
$readmemh({`PATH, FmaRzTests[TestNum]}, FmaRzVectors);
$readmemh({`PATH, FmaRnmTests[TestNum]}, FmaRnmVectors);
$readmemh({`PATH, FmaRneTests[FmaTestNum]}, FmaRneVectors);
$readmemh({`PATH, FmaRuTests[FmaTestNum]}, FmaRuVectors);
$readmemh({`PATH, FmaRdTests[FmaTestNum]}, FmaRdVectors);
$readmemh({`PATH, FmaRzTests[FmaTestNum]}, FmaRzVectors);
$readmemh({`PATH, FmaRnmTests[FmaTestNum]}, FmaRnmVectors);
// set the test index to 0
TestNum = 0;
FmaTestNum = 0;
end
// set a the signals for all tests
always_comb FmaFmtVal = FmaFmt[TestNum];
always_comb FmaFmtVal = FmaFmt[FmaTestNum];
always_comb UnitVal = Unit[TestNum];
always_comb FmtVal = Fmt[TestNum];
always_comb OpCtrlVal = OpCtrl[OpCtrlNum];
@ -669,14 +673,14 @@ module testbenchfp;
// - 1 for the larger precision
// - 0 for the smaller precision
always_comb begin
if(`FPSIZES/3 === 1) ModFmt = FmtVal;
else ModFmt = FmtVal === `FMT;
if(`FPSIZES/3 === 1) FmaModFmt = FmaFmtVal;
else FmaModFmt = FmaFmtVal === `FMT;
if(`FMTBITS == 1) ModFmt = FmtVal == `FMT;
else ModFmt = FmtVal;
if(`FMTBITS == 1) FmaModFmt = FmaFmtVal == `FMT;
else FmaModFmt = FmaFmtVal;
end
// extract the inputs (X, Y, Z, SrcA) and the output (Ans, AnsFlg) from the current test vector
readfmavectors readfmarnevectors (.clk, .TestVector(FmaRneVectors[VectorNum]), .Ans(FmaRneAns), .AnsFlg(FmaRneAnsFlg),
readfmavectors readfmarnevectors (.clk, .TestVector(FmaRneVectors[FmaVectorNum]), .Ans(FmaRneAns), .AnsFlg(FmaRneAnsFlg),
.XSgnE(FmaRneXSgn), .YSgnE(FmaRneYSgn), .ZSgnE(FmaRneZSgn),
.XExpE(FmaRneXExp), .YExpE(FmaRneYExp), .ZExpE(FmaRneZExp),
.XManE(FmaRneXMan), .YManE(FmaRneYMan), .ZManE(FmaRneZMan),
@ -686,7 +690,7 @@ module testbenchfp;
.XZeroE(FmaRneXZero), .YZeroE(FmaRneYZero), .ZZeroE(FmaRneZZero),
.XInfE(FmaRneXInf), .YInfE(FmaRneYInf), .ZInfE(FmaRneZInf), .FmaModFmt, .FmaFmt(FmaFmtVal),
.X(FmaRneX), .Y(FmaRneY), .Z(FmaRneZ));
readfmavectors readfmarzvectors (.clk, .TestVector(FmaRzVectors[VectorNum]), .Ans(FmaRzAns), .AnsFlg(FmaRzAnsFlg),
readfmavectors readfmarzvectors (.clk, .TestVector(FmaRzVectors[FmaVectorNum]), .Ans(FmaRzAns), .AnsFlg(FmaRzAnsFlg),
.XSgnE(FmaRzXSgn), .YSgnE(FmaRzYSgn), .ZSgnE(FmaRzZSgn), .FmaModFmt,
.XExpE(FmaRzXExp), .YExpE(FmaRzYExp), .ZExpE(FmaRzZExp),
.XManE(FmaRzXMan), .YManE(FmaRzYMan), .ZManE(FmaRzZMan),
@ -696,7 +700,7 @@ module testbenchfp;
.XZeroE(FmaRzXZero), .YZeroE(FmaRzYZero), .ZZeroE(FmaRzZZero),
.XInfE(FmaRzXInf), .YInfE(FmaRzYInf), .ZInfE(FmaRzZInf), .FmaFmt(FmaFmtVal),
.X(FmaRzX), .Y(FmaRzY), .Z(FmaRzZ));
readfmavectors readfmaruvectors (.clk, .TestVector(FmaRuVectors[VectorNum]), .Ans(FmaRuAns), .AnsFlg(FmaRuAnsFlg),
readfmavectors readfmaruvectors (.clk, .TestVector(FmaRuVectors[FmaVectorNum]), .Ans(FmaRuAns), .AnsFlg(FmaRuAnsFlg),
.XSgnE(FmaRuXSgn), .YSgnE(FmaRuYSgn), .ZSgnE(FmaRuZSgn), .FmaModFmt,
.XExpE(FmaRuXExp), .YExpE(FmaRuYExp), .ZExpE(FmaRuZExp),
.XManE(FmaRuXMan), .YManE(FmaRuYMan), .ZManE(FmaRuZMan),
@ -706,7 +710,7 @@ module testbenchfp;
.XZeroE(FmaRuXZero), .YZeroE(FmaRuYZero), .ZZeroE(FmaRuZZero),
.XInfE(FmaRuXInf), .YInfE(FmaRuYInf), .ZInfE(FmaRuZInf), .FmaFmt(FmaFmtVal),
.X(FmaRuX), .Y(FmaRuY), .Z(FmaRuZ));
readfmavectors readfmardvectors (.clk, .TestVector(FmaRdVectors[VectorNum]), .Ans(FmaRdAns), .AnsFlg(FmaRdAnsFlg),
readfmavectors readfmardvectors (.clk, .TestVector(FmaRdVectors[FmaVectorNum]), .Ans(FmaRdAns), .AnsFlg(FmaRdAnsFlg),
.XSgnE(FmaRdXSgn), .YSgnE(FmaRdYSgn), .ZSgnE(FmaRdZSgn), .FmaModFmt,
.XExpE(FmaRdXExp), .YExpE(FmaRdYExp), .ZExpE(FmaRdZExp),
.XManE(FmaRdXMan), .YManE(FmaRdYMan), .ZManE(FmaRdZMan),
@ -716,7 +720,7 @@ module testbenchfp;
.XZeroE(FmaRdXZero), .YZeroE(FmaRdYZero), .ZZeroE(FmaRdZZero),
.XInfE(FmaRdXInf), .YInfE(FmaRdYInf), .ZInfE(FmaRdZInf), .FmaFmt(FmaFmtVal),
.X(FmaRdX), .Y(FmaRdY), .Z(FmaRdZ));
readfmavectors readfmarnmvectors (.clk, .TestVector(FmaRnmVectors[VectorNum]), .Ans(FmaRnmAns), .AnsFlg(FmaRnmAnsFlg),
readfmavectors readfmarnmvectors (.clk, .TestVector(FmaRnmVectors[FmaVectorNum]), .Ans(FmaRnmAns), .AnsFlg(FmaRnmAnsFlg),
.XSgnE(FmaRnmXSgn), .YSgnE(FmaRnmYSgn), .ZSgnE(FmaRnmZSgn), .FmaModFmt,
.XExpE(FmaRnmXExp), .YExpE(FmaRnmYExp), .ZExpE(FmaRnmZExp),
.XManE(FmaRnmXMan), .YManE(FmaRnmYMan), .ZManE(FmaRnmZMan),
@ -1024,130 +1028,158 @@ end
// - the sign of the NaN does not matter for the opperations being tested
// - when 2 or more NaNs are inputed the NaN that is propigated doesn't matter
case (FmaFmtVal)
4'b11: FmaRneNaNGood =((FmaRneAnsFlg[4]&(FmaRneRes[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) |
4'b11: FmaRneNaNGood =(((`IEEE754==0)&FmaRneAnsNaN&(FmaRneRes === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) |
(FmaRneAnsFlg[4]&(FmaRneRes[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) |
(FmaRneXNaN&(FmaRneRes[`Q_LEN-2:0] === {FmaRneX[`Q_LEN-2:`Q_NF],1'b1,FmaRneX[`Q_NF-2:0]})) |
(FmaRneYNaN&(FmaRneRes[`Q_LEN-2:0] === {FmaRneY[`Q_LEN-2:`Q_NF],1'b1,FmaRneY[`Q_NF-2:0]})) |
(FmaRneZNaN&(FmaRneRes[`Q_LEN-2:0] === {FmaRneZ[`Q_LEN-2:`Q_NF],1'b1,FmaRneZ[`Q_NF-2:0]})));
4'b01: FmaRneNaNGood =((FmaRneAnsFlg[4]&(FmaRneRes[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) |
4'b01: FmaRneNaNGood =(((`IEEE754==0)&FmaRneAnsNaN&(FmaRneRes[`D_LEN-1:0] === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) |
(FmaRneAnsFlg[4]&(FmaRneRes[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) |
(FmaRneXNaN&(FmaRneRes[`D_LEN-2:0] === {FmaRneX[`D_LEN-2:`D_NF],1'b1,FmaRneX[`D_NF-2:0]})) |
(FmaRneYNaN&(FmaRneRes[`D_LEN-2:0] === {FmaRneY[`D_LEN-2:`D_NF],1'b1,FmaRneY[`D_NF-2:0]})) |
(FmaRneZNaN&(FmaRneRes[`D_LEN-2:0] === {FmaRneZ[`D_LEN-2:`D_NF],1'b1,FmaRneZ[`D_NF-2:0]})));
4'b00: FmaRneNaNGood =((FmaRneAnsFlg[4]&(FmaRneRes[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) |
4'b00: FmaRneNaNGood =(((`IEEE754==0)&FmaRneAnsNaN&(FmaRneRes[`S_LEN-1:0] === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) |
(FmaRneAnsFlg[4]&(FmaRneRes[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) |
(FmaRneXNaN&(FmaRneRes[`S_LEN-2:0] === {FmaRneX[`S_LEN-2:`S_NF],1'b1,FmaRneX[`S_NF-2:0]})) |
(FmaRneYNaN&(FmaRneRes[`S_LEN-2:0] === {FmaRneY[`S_LEN-2:`S_NF],1'b1,FmaRneY[`S_NF-2:0]})) |
(FmaRneZNaN&(FmaRneRes[`S_LEN-2:0] === {FmaRneZ[`S_LEN-2:`S_NF],1'b1,FmaRneZ[`S_NF-2:0]})));
4'b10: FmaRneNaNGood =((FmaRneAnsFlg[4]&(FmaRneRes[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) |
4'b10: FmaRneNaNGood =(((`IEEE754==0)&FmaRneAnsNaN&(FmaRneRes[`H_LEN-1:0] === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) |
(FmaRneAnsFlg[4]&(FmaRneRes[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) |
(FmaRneXNaN&(FmaRneRes[`H_LEN-2:0] === {FmaRneX[`H_LEN-2:`H_NF],1'b1,FmaRneX[`H_NF-2:0]})) |
(FmaRneYNaN&(FmaRneRes[`H_LEN-2:0] === {FmaRneY[`H_LEN-2:`H_NF],1'b1,FmaRneY[`H_NF-2:0]})) |
(FmaRneZNaN&(FmaRneRes[`H_LEN-2:0] === {FmaRneZ[`H_LEN-2:`H_NF],1'b1,FmaRneZ[`H_NF-2:0]})));
endcase
case (FmaFmtVal)
4'b11: FmaRzNaNGood = ((FmaRzAnsFlg[4]&(FmaRzRes[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) |
4'b11: FmaRzNaNGood = (((`IEEE754==0)&FmaRzAnsNaN&(FmaRzRes === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) |
(FmaRzAnsFlg[4]&(FmaRzRes[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) |
(FmaRzXNaN&(FmaRzRes[`Q_LEN-2:0] === {FmaRzX[`Q_LEN-2:`Q_NF],1'b1,FmaRzX[`Q_NF-2:0]})) |
(FmaRzYNaN&(FmaRzRes[`Q_LEN-2:0] === {FmaRzY[`Q_LEN-2:`Q_NF],1'b1,FmaRzY[`Q_NF-2:0]})) |
(FmaRzZNaN&(FmaRzRes[`Q_LEN-2:0] === {FmaRzZ[`Q_LEN-2:`Q_NF],1'b1,FmaRzZ[`Q_NF-2:0]})));
4'b01: FmaRzNaNGood = ((FmaRzAnsFlg[4]&(FmaRzRes[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) |
4'b01: FmaRzNaNGood = (((`IEEE754==0)&FmaRzAnsNaN&(FmaRzRes[`D_LEN-1:0] === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) |
(FmaRzAnsFlg[4]&(FmaRzRes[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) |
(FmaRzXNaN&(FmaRzRes[`D_LEN-2:0] === {FmaRzX[`D_LEN-2:`D_NF],1'b1,FmaRzX[`D_NF-2:0]})) |
(FmaRzYNaN&(FmaRzRes[`D_LEN-2:0] === {FmaRzY[`D_LEN-2:`D_NF],1'b1,FmaRzY[`D_NF-2:0]})) |
(FmaRzZNaN&(FmaRzRes[`D_LEN-2:0] === {FmaRzZ[`D_LEN-2:`D_NF],1'b1,FmaRzZ[`D_NF-2:0]})));
4'b00: FmaRzNaNGood = ((FmaRzAnsFlg[4]&(FmaRzRes[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) |
4'b00: FmaRzNaNGood = (((`IEEE754==0)&FmaRzAnsNaN&(FmaRzRes[`S_LEN-1:0] === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) |
(FmaRzAnsFlg[4]&(FmaRzRes[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) |
(FmaRzXNaN&(FmaRzRes[`S_LEN-2:0] === {FmaRzX[`S_LEN-2:`S_NF],1'b1,FmaRzX[`S_NF-2:0]})) |
(FmaRzYNaN&(FmaRzRes[`S_LEN-2:0] === {FmaRzY[`S_LEN-2:`S_NF],1'b1,FmaRzY[`S_NF-2:0]})) |
(FmaRzZNaN&(FmaRzRes[`S_LEN-2:0] === {FmaRzZ[`S_LEN-2:`S_NF],1'b1,FmaRzZ[`S_NF-2:0]})));
4'b10: FmaRzNaNGood = ((FmaRzAnsFlg[4]&(FmaRzRes[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) |
4'b10: FmaRzNaNGood = (((`IEEE754==0)&FmaRzAnsNaN&(FmaRzRes[`H_LEN-1:0] === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) |
(FmaRzAnsFlg[4]&(FmaRzRes[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) |
(FmaRzXNaN&(FmaRzRes[`H_LEN-2:0] === {FmaRzX[`H_LEN-2:`H_NF],1'b1,FmaRzX[`H_NF-2:0]})) |
(FmaRzYNaN&(FmaRzRes[`H_LEN-2:0] === {FmaRzY[`H_LEN-2:`H_NF],1'b1,FmaRzY[`H_NF-2:0]})) |
(FmaRzZNaN&(FmaRzRes[`H_LEN-2:0] === {FmaRzZ[`H_LEN-2:`H_NF],1'b1,FmaRzZ[`H_NF-2:0]})));
endcase
case (FmaFmtVal)
4'b11: FmaRuNaNGood = ((FmaRuAnsFlg[4]&(FmaRuRes[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) |
4'b11: FmaRuNaNGood = (((`IEEE754==0)&FmaRuAnsNaN&(FmaRuRes === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) |
(FmaRuAnsFlg[4]&(FmaRuRes[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) |
(FmaRuXNaN&(FmaRuRes[`Q_LEN-2:0] === {FmaRuX[`Q_LEN-2:`Q_NF],1'b1,FmaRuX[`Q_NF-2:0]})) |
(FmaRuYNaN&(FmaRuRes[`Q_LEN-2:0] === {FmaRuY[`Q_LEN-2:`Q_NF],1'b1,FmaRuY[`Q_NF-2:0]})) |
(FmaRuZNaN&(FmaRuRes[`Q_LEN-2:0] === {FmaRuZ[`Q_LEN-2:`Q_NF],1'b1,FmaRuZ[`Q_NF-2:0]})));
4'b01: FmaRuNaNGood = ((FmaRuAnsFlg[4]&(FmaRuRes[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) |
4'b01: FmaRuNaNGood = (((`IEEE754==0)&FmaRuAnsNaN&(FmaRuRes[`D_LEN-1:0] === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) |
(FmaRuAnsFlg[4]&(FmaRuRes[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) |
(FmaRuAnsFlg[4]&(FmaRuRes[`Q_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF{1'b0}}})) |
(FmaRuXNaN&(FmaRuRes[`D_LEN-2:0] === {FmaRuX[`D_LEN-2:`D_NF],1'b1,FmaRuX[`D_NF-2:0]})) |
(FmaRuYNaN&(FmaRuRes[`D_LEN-2:0] === {FmaRuY[`D_LEN-2:`D_NF],1'b1,FmaRuY[`D_NF-2:0]})) |
(FmaRuZNaN&(FmaRuRes[`D_LEN-2:0] === {FmaRuZ[`D_LEN-2:`D_NF],1'b1,FmaRuZ[`D_NF-2:0]})));
4'b00: FmaRuNaNGood = ((FmaRuAnsFlg[4]&(FmaRuRes[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) |
4'b00: FmaRuNaNGood = (((`IEEE754==0)&FmaRuAnsNaN&(FmaRuRes[`S_LEN-1:0] === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) |
(FmaRuAnsFlg[4]&(FmaRuRes[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) |
(FmaRuXNaN&(FmaRuRes[`S_LEN-2:0] === {FmaRuX[`S_LEN-2:`S_NF],1'b1,FmaRuX[`S_NF-2:0]})) |
(FmaRuYNaN&(FmaRuRes[`S_LEN-2:0] === {FmaRuY[`S_LEN-2:`S_NF],1'b1,FmaRuY[`S_NF-2:0]})) |
(FmaRuZNaN&(FmaRuRes[`S_LEN-2:0] === {FmaRuZ[`S_LEN-2:`S_NF],1'b1,FmaRuZ[`S_NF-2:0]})));
4'b10: FmaRuNaNGood = ((FmaRuAnsFlg[4]&(FmaRuRes[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) |
4'b10: FmaRuNaNGood = (((`IEEE754==0)&FmaRuAnsNaN&(FmaRuRes[`H_LEN-1:0] === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) |
(FmaRuAnsFlg[4]&(FmaRuRes[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) |
(FmaRuXNaN&(FmaRuRes[`H_LEN-2:0] === {FmaRuX[`H_LEN-2:`H_NF],1'b1,FmaRuX[`H_NF-2:0]})) |
(FmaRuYNaN&(FmaRuRes[`H_LEN-2:0] === {FmaRuY[`H_LEN-2:`H_NF],1'b1,FmaRuY[`H_NF-2:0]})) |
(FmaRuZNaN&(FmaRuRes[`H_LEN-2:0] === {FmaRuZ[`H_LEN-2:`H_NF],1'b1,FmaRuZ[`H_NF-2:0]})));
endcase
case (FmaFmtVal)
4'b11: FmaRdNaNGood = ((FmaRdAnsFlg[4]&(FmaRdRes[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) |
4'b11: FmaRdNaNGood = (((`IEEE754==0)&FmaRdAnsNaN&(FmaRdRes === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) |
(FmaRdAnsFlg[4]&(FmaRdRes[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) |
(FmaRdXNaN&(FmaRdRes[`Q_LEN-2:0] === {FmaRdX[`Q_LEN-2:`Q_NF],1'b1,FmaRdX[`Q_NF-2:0]})) |
(FmaRdYNaN&(FmaRdRes[`Q_LEN-2:0] === {FmaRdY[`Q_LEN-2:`Q_NF],1'b1,FmaRdY[`Q_NF-2:0]})) |
(FmaRdZNaN&(FmaRdRes[`Q_LEN-2:0] === {FmaRdZ[`Q_LEN-2:`Q_NF],1'b1,FmaRdZ[`Q_NF-2:0]})));
4'b01: FmaRdNaNGood = ((FmaRdAnsFlg[4]&(FmaRdRes[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) |
4'b01: FmaRdNaNGood = (((`IEEE754==0)&FmaRdAnsNaN&(FmaRdRes[`D_LEN-1:0] === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) |
(FmaRdAnsFlg[4]&(FmaRdRes[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) |
(FmaRdXNaN&(FmaRdRes[`D_LEN-2:0] === {FmaRdX[`D_LEN-2:`D_NF],1'b1,FmaRdX[`D_NF-2:0]})) |
(FmaRdYNaN&(FmaRdRes[`D_LEN-2:0] === {FmaRdY[`D_LEN-2:`D_NF],1'b1,FmaRdY[`D_NF-2:0]})) |
(FmaRdZNaN&(FmaRdRes[`D_LEN-2:0] === {FmaRdZ[`D_LEN-2:`D_NF],1'b1,FmaRdZ[`D_NF-2:0]})));
4'b00: FmaRdNaNGood = ((FmaRdAnsFlg[4]&(FmaRdRes[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) |
4'b00: FmaRdNaNGood = (((`IEEE754==0)&FmaRdAnsNaN&(FmaRdRes[`S_LEN-1:0] === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) |
(FmaRdAnsFlg[4]&(FmaRdRes[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) |
(FmaRdXNaN&(FmaRdRes[`S_LEN-2:0] === {FmaRdX[`S_LEN-2:`S_NF],1'b1,FmaRdX[`S_NF-2:0]})) |
(FmaRdYNaN&(FmaRdRes[`S_LEN-2:0] === {FmaRdY[`S_LEN-2:`S_NF],1'b1,FmaRdY[`S_NF-2:0]})) |
(FmaRdZNaN&(FmaRdRes[`S_LEN-2:0] === {FmaRdZ[`S_LEN-2:`S_NF],1'b1,FmaRdZ[`S_NF-2:0]})));
4'b10: FmaRdNaNGood = ((FmaRdAnsFlg[4]&(FmaRdRes[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) |
4'b10: FmaRdNaNGood = (((`IEEE754==0)&FmaRdAnsNaN&(FmaRdRes[`H_LEN-1:0] === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) |
(FmaRdAnsFlg[4]&(FmaRdRes[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) |
(FmaRdXNaN&(FmaRdRes[`H_LEN-2:0] === {FmaRdX[`H_LEN-2:`H_NF],1'b1,FmaRdX[`H_NF-2:0]})) |
(FmaRdYNaN&(FmaRdRes[`H_LEN-2:0] === {FmaRdY[`H_LEN-2:`H_NF],1'b1,FmaRdY[`H_NF-2:0]})) |
(FmaRdZNaN&(FmaRdRes[`H_LEN-2:0] === {FmaRdZ[`H_LEN-2:`H_NF],1'b1,FmaRdZ[`H_NF-2:0]})));
endcase
case (FmaFmtVal)
4'b11: FmaRnmNaNGood =((FmaRnmAnsFlg[4]&(FmaRnmRes[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) |
4'b11: FmaRnmNaNGood =(((`IEEE754==0)&FmaRnmAnsNaN&(FmaRnmRes === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) |
(FmaRnmAnsFlg[4]&(FmaRnmRes[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) |
(FmaRnmXNaN&(FmaRnmRes[`Q_LEN-2:0] === {FmaRnmX[`Q_LEN-2:`Q_NF],1'b1,FmaRnmX[`Q_NF-2:0]})) |
(FmaRnmYNaN&(FmaRnmRes[`Q_LEN-2:0] === {FmaRnmY[`Q_LEN-2:`Q_NF],1'b1,FmaRnmY[`Q_NF-2:0]})) |
(FmaRnmZNaN&(FmaRnmRes[`Q_LEN-2:0] === {FmaRnmZ[`Q_LEN-2:`Q_NF],1'b1,FmaRnmZ[`Q_NF-2:0]})));
4'b01: FmaRnmNaNGood =((FmaRnmAnsFlg[4]&(FmaRnmRes[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) |
4'b01: FmaRnmNaNGood =(((`IEEE754==0)&FmaRnmAnsNaN&(FmaRnmRes[`D_LEN-1:0] === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) |
(FmaRnmAnsFlg[4]&(FmaRnmRes[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) |
(FmaRnmXNaN&(FmaRnmRes[`D_LEN-2:0] === {FmaRnmX[`D_LEN-2:`D_NF],1'b1,FmaRnmX[`D_NF-2:0]})) |
(FmaRnmYNaN&(FmaRnmRes[`D_LEN-2:0] === {FmaRnmY[`D_LEN-2:`D_NF],1'b1,FmaRnmY[`D_NF-2:0]})) |
(FmaRnmZNaN&(FmaRnmRes[`D_LEN-2:0] === {FmaRnmZ[`D_LEN-2:`D_NF],1'b1,FmaRnmZ[`D_NF-2:0]})));
4'b00: FmaRnmNaNGood =((FmaRnmAnsFlg[4]&(FmaRnmRes[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) |
4'b00: FmaRnmNaNGood =(((`IEEE754==0)&FmaRnmAnsNaN&(FmaRnmRes[`S_LEN-1:0] === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) |
(FmaRnmAnsFlg[4]&(FmaRnmRes[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) |
(FmaRnmXNaN&(FmaRnmRes[`S_LEN-2:0] === {FmaRnmX[`S_LEN-2:`S_NF],1'b1,FmaRnmX[`S_NF-2:0]})) |
(FmaRnmYNaN&(FmaRnmRes[`S_LEN-2:0] === {FmaRnmY[`S_LEN-2:`S_NF],1'b1,FmaRnmY[`S_NF-2:0]})) |
(FmaRnmZNaN&(FmaRnmRes[`S_LEN-2:0] === {FmaRnmZ[`S_LEN-2:`S_NF],1'b1,FmaRnmZ[`S_NF-2:0]})));
4'b10: FmaRnmNaNGood =((FmaRnmAnsFlg[4]&(FmaRnmRes[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) |
4'b10: FmaRnmNaNGood =(((`IEEE754==0)&FmaRnmAnsNaN&(FmaRnmRes[`H_LEN-1:0] === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) |
(FmaRnmAnsFlg[4]&(FmaRnmRes[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) |
(FmaRnmXNaN&(FmaRnmRes[`H_LEN-2:0] === {FmaRnmX[`H_LEN-2:`H_NF],1'b1,FmaRnmX[`H_NF-2:0]})) |
(FmaRnmYNaN&(FmaRnmRes[`H_LEN-2:0] === {FmaRnmY[`H_LEN-2:`H_NF],1'b1,FmaRnmY[`H_NF-2:0]})) |
(FmaRnmZNaN&(FmaRnmRes[`H_LEN-2:0] === {FmaRnmZ[`H_LEN-2:`H_NF],1'b1,FmaRnmZ[`H_NF-2:0]})));
endcase
if (UnitVal !== `CVTFPUNIT & UnitVal !== `CVTINTUNIT)
case (FmtVal)
4'b11: NaNGood = ((AnsFlg[4]&(Res[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) |
4'b11: NaNGood = (((`IEEE754==0)&AnsNaN&(Res === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) |
(AnsFlg[4]&(Res[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) |
(XNaN&(Res[`Q_LEN-2:0] === {X[`Q_LEN-2:`Q_NF],1'b1,X[`Q_NF-2:0]})) |
(YNaN&(Res[`Q_LEN-2:0] === {Y[`Q_LEN-2:`Q_NF],1'b1,Y[`Q_NF-2:0]})) |
(ZNaN&(Res[`Q_LEN-2:0] === {Z[`Q_LEN-2:`Q_NF],1'b1,Z[`Q_NF-2:0]})));
4'b01: NaNGood = ((AnsFlg[4]&(Res[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) |
4'b01: NaNGood = (((`IEEE754==0)&AnsNaN&(Res[`D_LEN-1:0] === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) |
(AnsFlg[4]&(Res[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) |
(XNaN&(Res[`D_LEN-2:0] === {X[`D_LEN-2:`D_NF],1'b1,X[`D_NF-2:0]})) |
(YNaN&(Res[`D_LEN-2:0] === {Y[`D_LEN-2:`D_NF],1'b1,Y[`D_NF-2:0]})) |
(ZNaN&(Res[`D_LEN-2:0] === {Z[`D_LEN-2:`D_NF],1'b1,Z[`D_NF-2:0]})));
4'b00: NaNGood = ((AnsFlg[4]&(Res[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) |
4'b00: NaNGood = (((`IEEE754==0)&AnsNaN&(Res[`S_LEN-1:0] === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) |
(AnsFlg[4]&(Res[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) |
(XNaN&(Res[`S_LEN-2:0] === {X[`S_LEN-2:`S_NF],1'b1,X[`S_NF-2:0]})) |
(YNaN&(Res[`S_LEN-2:0] === {Y[`S_LEN-2:`S_NF],1'b1,Y[`S_NF-2:0]})) |
(ZNaN&(Res[`S_LEN-2:0] === {Z[`S_LEN-2:`S_NF],1'b1,Z[`S_NF-2:0]})));
4'b10: NaNGood = ((AnsFlg[4]&(Res[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) |
4'b10: NaNGood = (((`IEEE754==0)&AnsNaN&(Res[`H_LEN-1:0] === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) |
(AnsFlg[4]&(Res[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) |
(XNaN&(Res[`H_LEN-2:0] === {X[`H_LEN-2:`H_NF],1'b1,X[`H_NF-2:0]})) |
(YNaN&(Res[`H_LEN-2:0] === {Y[`H_LEN-2:`H_NF],1'b1,Y[`H_NF-2:0]})) |
(ZNaN&(Res[`H_LEN-2:0] === {Z[`H_LEN-2:`H_NF],1'b1,Z[`H_NF-2:0]})));
endcase
else if (UnitVal === `CVTFPUNIT) // if converting from floating point to floating point OpCtrl contains the final FP format
case (OpCtrlVal[1:0])
2'b11: NaNGood = ((AnsFlg[4]&(Res[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) |
2'b11: NaNGood = (((`IEEE754==0)&AnsNaN&(Res === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) |
(AnsFlg[4]&(Res[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) |
(AnsNaN&(Res[`Q_LEN-2:0] === Ans[`Q_LEN-2:0])) |
(XNaN&(Res[`Q_LEN-2:0] === {X[`Q_LEN-2:`Q_NF],1'b1,X[`Q_NF-2:0]})) |
(YNaN&(Res[`Q_LEN-2:0] === {Y[`Q_LEN-2:`Q_NF],1'b1,Y[`Q_NF-2:0]})));
2'b01: NaNGood = ((AnsFlg[4]&(Res[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) |
2'b01: NaNGood = (((`IEEE754==0)&AnsNaN&(Res[`D_LEN-1:0] === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) |
(AnsFlg[4]&(Res[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) |
(AnsNaN&(Res[`D_LEN-2:0] === Ans[`D_LEN-2:0])) |
(XNaN&(Res[`D_LEN-2:0] === {X[`D_LEN-2:`D_NF],1'b1,X[`D_NF-2:0]})) |
(YNaN&(Res[`D_LEN-2:0] === {Y[`D_LEN-2:`D_NF],1'b1,Y[`D_NF-2:0]})));
2'b00: NaNGood = ((AnsFlg[4]&(Res[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) |
2'b00: NaNGood = (((`IEEE754==0)&AnsNaN&(Res[`S_LEN-1:0] === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) |
(AnsFlg[4]&(Res[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) |
(AnsNaN&(Res[`S_LEN-2:0] === Ans[`S_LEN-2:0])) |
(XNaN&(Res[`S_LEN-2:0] === {X[`S_LEN-2:`S_NF],1'b1,X[`S_NF-2:0]})) |
(YNaN&(Res[`S_LEN-2:0] === {Y[`S_LEN-2:`S_NF],1'b1,Y[`S_NF-2:0]})));
2'b10: NaNGood = ((AnsFlg[4]&(Res[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) |
2'b10: NaNGood = (((`IEEE754==0)&AnsNaN&(Res[`H_LEN-1:0] === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) |
(AnsFlg[4]&(Res[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) |
(AnsNaN&(Res[`H_LEN-2:0] === Ans[`H_LEN-2:0])) |
(XNaN&(Res[`H_LEN-2:0] === {X[`H_LEN-2:`H_NF],1'b1,X[`H_NF-2:0]})) |
(YNaN&(Res[`H_LEN-2:0] === {Y[`H_LEN-2:`H_NF],1'b1,Y[`H_NF-2:0]})));
@ -1182,7 +1214,7 @@ end
else if ((UnitVal === `CVTINTUNIT) & ~(((WriteIntVal&~OpCtrlVal[0]&AnsFlg[4]&XSgn&(Res[`XLEN-1:0] === (`XLEN)'(0))) |
(WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~XSgn|XNaN)&OpCtrlVal[1]&(Res[`XLEN-1:0] === {1'b0, {`XLEN-1{1'b1}}})) |
(WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~XSgn|XNaN)&~OpCtrlVal[1]&(Res[`XLEN-1:0] === {{`XLEN-32{1'b0}}, 1'b0, {31{1'b1}}})) |
(Res === Ans | NaNGood | NaNGood === 1'bx)) & (ResFlg === AnsFlg | AnsFlg === 5'bx))) begin
(~(WriteIntVal&~OpCtrlVal[0]&AnsFlg[4]&XSgn&~XNaN)&(Res === Ans | NaNGood | NaNGood === 1'bx))) & (ResFlg === AnsFlg | AnsFlg === 5'bx))) begin
errors += 1;
$display("There is an error in %s", Tests[TestNum]);
$display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Ans: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg);
@ -1222,15 +1254,46 @@ end
end
VectorNum += 1; // increment the vector
FmaVectorNum += 1; // increment the vector
// check to see if there more vectors in this test
// *** fix this so that fma and other run sepratly - re-add fma num
if (TestVectors[VectorNum][0] === 1'bx &
FmaRneVectors[VectorNum][0] === 1'bx &
FmaRzVectors[VectorNum][0] === 1'bx &
FmaRuVectors[VectorNum][0] === 1'bx &
FmaRdVectors[VectorNum][0] === 1'bx &
FmaRnmVectors[VectorNum][0] === 1'bx) begin // if reached the end of file
if ((FmaRneVectors[FmaVectorNum][0] === 1'bx &
FmaRzVectors[FmaVectorNum][0] === 1'bx &
FmaRuVectors[FmaVectorNum][0] === 1'bx &
FmaRdVectors[FmaVectorNum][0] === 1'bx &
FmaRnmVectors[FmaVectorNum][0] === 1'bx & FmaRneTests[FmaTestNum] !== "" )) begin // if reached the end of file
// increment the test
FmaTestNum += 1;
// clear the vectors
for(int i=0; i<46465; i++) TestVectors[i] = {`FLEN*4+8{1'bx}};
// read next files
$readmemh({`PATH, FmaRneTests[FmaTestNum]}, FmaRneVectors);
$readmemh({`PATH, FmaRuTests[FmaTestNum]}, FmaRuVectors);
$readmemh({`PATH, FmaRdTests[FmaTestNum]}, FmaRdVectors);
$readmemh({`PATH, FmaRzTests[FmaTestNum]}, FmaRzVectors);
$readmemh({`PATH, FmaRnmTests[FmaTestNum]}, FmaRnmVectors);
// set the vector index back to 0
FmaVectorNum = 0;
// if no more Tests - finish
if(Tests[TestNum] === "" &
FmaRneTests[FmaTestNum] === "" &
FmaRzTests[FmaTestNum] === "" &
FmaRuTests[FmaTestNum] === "" &
FmaRdTests[FmaTestNum] === "" &
FmaRnmTests[FmaTestNum] === "") begin
$display("\nAll Tests completed with %d errors\n", errors);
$stop;
end
$display("Running FMA precision %d", FmaTestNum);
end
if (TestVectors[VectorNum][0] === 1'bx & Tests[TestNum] !== "") begin // if reached the end of file
// increment the test
TestNum += 1;
@ -1239,11 +1302,11 @@ end
for(int i=0; i<46465; i++) TestVectors[i] = {`FLEN*4+8{1'bx}};
// read next files
$readmemh({`PATH, Tests[TestNum]}, TestVectors);
$readmemh({`PATH, FmaRneTests[TestNum]}, FmaRneVectors);
$readmemh({`PATH, FmaRuTests[TestNum]}, FmaRuVectors);
$readmemh({`PATH, FmaRdTests[TestNum]}, FmaRdVectors);
$readmemh({`PATH, FmaRzTests[TestNum]}, FmaRzVectors);
$readmemh({`PATH, FmaRnmTests[TestNum]}, FmaRnmVectors);
$readmemh({`PATH, FmaRneTests[FmaTestNum]}, FmaRneVectors);
$readmemh({`PATH, FmaRuTests[FmaTestNum]}, FmaRuVectors);
$readmemh({`PATH, FmaRdTests[FmaTestNum]}, FmaRdVectors);
$readmemh({`PATH, FmaRzTests[FmaTestNum]}, FmaRzVectors);
$readmemh({`PATH, FmaRnmTests[FmaTestNum]}, FmaRnmVectors);
// set the vector index back to 0
VectorNum = 0;
@ -1255,11 +1318,11 @@ end
// if no more Tests - finish
if(Tests[TestNum] === "" &
FmaRneTests[TestNum] === "" &
FmaRzTests[TestNum] === "" &
FmaRuTests[TestNum] === "" &
FmaRdTests[TestNum] === "" &
FmaRnmTests[TestNum] === "") begin
FmaRneTests[FmaTestNum] === "" &
FmaRzTests[FmaTestNum] === "" &
FmaRuTests[FmaTestNum] === "" &
FmaRdTests[FmaTestNum] === "" &
FmaRnmTests[FmaTestNum] === "") begin
$display("\nAll Tests completed with %d errors\n", errors);
$stop;
end
@ -1283,7 +1346,7 @@ endmodule
module readfmavectors (
input logic clk,
input logic [`FPSIZES/3:0] FmaModFmt, // the modified format
input logic [`FMTBITS-1:0] FmaModFmt, // the modified format
input logic [1:0] FmaFmt, // the format of the FMA inputs
input logic [`FLEN*4+7:0] TestVector, // the test vector
output logic [`FLEN-1:0] Ans, // the correct answer
@ -1358,7 +1421,7 @@ endmodule
module readvectors (
input logic clk,
input logic [`FLEN*4+7:0] TestVector,
input logic [`FPSIZES/3:0] ModFmt,
input logic [`FMTBITS-1:0] ModFmt,
input logic [1:0] Fmt,
input logic [2:0] Unit,
input logic [31:0] VectorNum,
@ -1389,14 +1452,14 @@ module readvectors (
case (Fmt)
2'b11: begin // quad
X = TestVector[8+3*(`Q_LEN)-1:8+2*(`Q_LEN)];
if(OpCtrl === `MUL_OPCTRL) Y = TestVector[8+2*(`Q_LEN)-1:8+(`Q_LEN)]; else Y = {2'b0, {`Q_NE-1{1'b1}}, `Q_NF'h0};
if(OpCtrl === `MUL_OPCTRL) Y = TestVector[8+2*(`Q_LEN)-1:8+(`Q_LEN)]; else Y = {2'b0, {`Q_NE-1{1'b1}}, (`Q_NF)'(0)};
if(OpCtrl === `MUL_OPCTRL) Z = 0; else Z = TestVector[8+2*(`Q_LEN)-1:8+(`Q_LEN)];
Ans = TestVector[8+(`Q_LEN-1):8];
end
2'b01: begin // double
X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+3*(`D_LEN)-1:8+2*(`D_LEN)]};
if(OpCtrl === `MUL_OPCTRL) Y = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+(`D_LEN)]};
else Y = {{`FLEN-`D_LEN{1'b1}}, 2'b0, {`D_NE-1{1'b1}}, `D_NF'h0};
else Y = {{`FLEN-`D_LEN{1'b1}}, 2'b0, {`D_NE-1{1'b1}}, (`D_NF)'(0)};
if(OpCtrl === `MUL_OPCTRL) Z = {{`FLEN-`D_LEN{1'b1}}, {`D_LEN{1'b0}}};
else Z = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+(`D_LEN)]};
Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]};
@ -1404,7 +1467,7 @@ module readvectors (
2'b00: begin // single
X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+3*(`S_LEN)-1:8+2*(`S_LEN)]};
if(OpCtrl === `MUL_OPCTRL) Y = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+(`S_LEN)]};
else Y = {{`FLEN-`S_LEN{1'b1}}, 2'b0, {`S_NE-1{1'b1}}, `S_NF'h0};
else Y = {{`FLEN-`S_LEN{1'b1}}, 2'b0, {`S_NE-1{1'b1}}, (`S_NF)'(0)};
if(OpCtrl === `MUL_OPCTRL) Z = {{`FLEN-`S_LEN{1'b1}}, {`S_LEN{1'b0}}};
else Z = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+(`S_LEN)]};
Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]};
@ -1412,7 +1475,7 @@ module readvectors (
2'b10: begin // half
X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+3*(`H_LEN)-1:8+2*(`H_LEN)]};
if(OpCtrl === `MUL_OPCTRL) Y = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+2*(`H_LEN)-1:8+(`H_LEN)]};
else Y = {{`FLEN-`H_LEN{1'b1}}, 2'b0, {`H_NE-1{1'b1}}, `H_NF'h0};
else Y = {{`FLEN-`H_LEN{1'b1}}, 2'b0, {`H_NE-1{1'b1}}, (`H_NF)'(0)};
if(OpCtrl === `MUL_OPCTRL) Z = {{`FLEN-`H_LEN{1'b1}}, {`H_LEN{1'b0}}};
else Z = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+2*(`H_LEN)-1:8+(`H_LEN)]};
Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]};

50
pipelined/testbench/testbench-linux.sv
View File

@ -27,6 +27,15 @@
`include "wally-config.vh"
`define DEBUG_TRACE 0
// Debug Levels
// 0: don't check against QEMU
// 1: print disagreements with QEMU, but only halt on PCW disagreements
// 2: halt on any disagreement with QEMU except CSRs
// 3: halt on all disagreements with QEMU
// 4: print memory accesses whenever they happen
// 5: print everything
module testbench;
///////////////////////////////////////////////////////////////////////////////
/////////////////////////////////// CONFIG ////////////////////////////////////
@ -37,14 +46,7 @@ module testbench;
parameter CHECKPOINT = 0;
parameter RISCV_DIR = "/opt/riscv";
parameter NO_SPOOFING = 0;
parameter DEBUG_TRACE = 0;
// Debug Levels
// 0: don't check against QEMU
// 1: print disagreements with QEMU, but only halt on PCW disagreements
// 2: halt on any disagreement with QEMU except CSRs
// 3: halt on all disagreements with QEMU
// 4: print memory accesses whenever they happen
// 5: print everything
@ -350,6 +352,18 @@ module testbench;
end \
end
// Initializing all zeroes into the branch predictor memory.
genvar adrindex;
for(adrindex = 0; adrindex < 1024; adrindex++) begin
initial begin
force dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0;
force dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0;
#1;
release dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex];
release dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex];
end
end
genvar i;
`INIT_CHECKPOINT_SIMPLE_ARRAY(RF, [`XLEN-1:0],31,1);
`INIT_CHECKPOINT_SIMPLE_ARRAY(HPMCOUNTER, [`XLEN-1:0],`COUNTERS-1,0);
@ -403,8 +417,6 @@ module testbench;
$sformat(linuxImageDir,"%s/buildroot/output/images/",RISCV_DIR);
if (CHECKPOINT!=0)
$sformat(checkpointDir,"%s/linux-testvectors/checkpoint%0d/",RISCV_DIR,CHECKPOINT);
$readmemb(`TWO_BIT_PRELOAD, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem); // *** initialize these using zeroes rather than reading from files, see testbench.sv
$readmemb(`BTB_PRELOAD, dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem);
ProgramAddrMapFile = {linuxImageDir,"disassembly/vmlinux.objdump.addr"};
ProgramLabelMapFile = {linuxImageDir,"disassembly/vmlinux.objdump.lab"};
// initialize bootrom
@ -480,7 +492,7 @@ module testbench;
if (checkInstrM) begin \
// read 1 line of the trace file \
matchCount``STAGE = $fgets(line``STAGE, traceFile``STAGE); \
if(DEBUG_TRACE >= 5) $display("Time %t, line %x", $time, line``STAGE); \
if(`DEBUG_TRACE >= 5) $display("Time %t, line %x", $time, line``STAGE); \
// extract PC, Instr \
matchCount``STAGE = $sscanf(line``STAGE, "%x %x %s", ExpectedPC``STAGE, ExpectedInstr``STAGE, text``STAGE); \
if (`"STAGE`"=="M") begin \
@ -564,14 +576,14 @@ module testbench;
`define checkEQ(NAME, VAL, EXPECTED) \
if(VAL != EXPECTED) begin \
$display("%tns, %d instrs: %s %x differs from expected %x", $time, AttemptedInstructionCount, NAME, VAL, EXPECTED); \
if ((NAME == "PCW") | (DEBUG_TRACE >= 2)) fault = 1; \
if ((NAME == "PCW") | (`DEBUG_TRACE >= 2)) fault = 1; \
end
`define checkCSR(CSR) \
begin \
if (CSR != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin \
$display("%tns, %d instrs: CSR %s = %016x, does not equal expected value %016x", $time, AttemptedInstructionCount, ExpectedCSRArrayW[NumCSRPostWIndex], CSR, ExpectedCSRArrayValueW[NumCSRPostWIndex]); \
if(DEBUG_TRACE >= 3) fault = 1; \
if(`DEBUG_TRACE >= 3) fault = 1; \
end \
end
@ -656,13 +668,13 @@ module testbench;
// end sim
if ((AttemptedInstructionCount == INSTR_LIMIT) & (INSTR_LIMIT!=0)) begin $stop; $stop; end
fault = 0;
if (DEBUG_TRACE >= 1) begin
if (`DEBUG_TRACE >= 1) begin
`checkEQ("PCW",PCW,ExpectedPCW)
//`checkEQ("InstrW",InstrW,ExpectedInstrW) <-- not viable because of
// compressed to uncompressed conversion
`checkEQ("Instr Count",dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2],InstrCountW)
#2; // delay 2 ns.
if(DEBUG_TRACE >= 5) begin
if(`DEBUG_TRACE >= 5) begin
$display("%tns, %d instrs: Reg Write Address %02d ? expected value: %02d", $time, AttemptedInstructionCount, dut.core.ieu.dp.regf.a3, ExpectedRegAdrW);
$display("%tns, %d instrs: RF[%02d] %016x ? expected value: %016x", $time, AttemptedInstructionCount, ExpectedRegAdrW, dut.core.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW);
end
@ -672,13 +684,13 @@ module testbench;
`checkEQ(name, dut.core.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW)
end
if (MemOpW.substr(0,2) == "Mem") begin
if(DEBUG_TRACE >= 4) $display("\tIEUAdrW: %016x ? expected: %016x", IEUAdrW, ExpectedIEUAdrW);
if(`DEBUG_TRACE >= 4) $display("\tIEUAdrW: %016x ? expected: %016x", IEUAdrW, ExpectedIEUAdrW);
`checkEQ("IEUAdrW",IEUAdrW,ExpectedIEUAdrW)
if(MemOpW == "MemR" | MemOpW == "MemRW") begin
if(DEBUG_TRACE >= 4) $display("\tReadDataW: %016x ? expected: %016x", dut.core.ieu.dp.ReadDataW, ExpectedMemReadDataW);
if(`DEBUG_TRACE >= 4) $display("\tReadDataW: %016x ? expected: %016x", dut.core.ieu.dp.ReadDataW, ExpectedMemReadDataW);
`checkEQ("ReadDataW",dut.core.ieu.dp.ReadDataW,ExpectedMemReadDataW)
end else if(MemOpW == "MemW" | MemOpW == "MemRW") begin
if(DEBUG_TRACE >= 4) $display("\tWriteDataW: %016x ? expected: %016x", WriteDataW, ExpectedMemWriteDataW);
if(`DEBUG_TRACE >= 4) $display("\tWriteDataW: %016x ? expected: %016x", WriteDataW, ExpectedMemWriteDataW);
`checkEQ("WriteDataW",ExpectedMemWriteDataW,ExpectedMemWriteDataW)
end
end
@ -718,7 +730,7 @@ module testbench;
$display("processed %0d instructions with %0d warnings", AttemptedInstructionCount, warningCount);
$stop; $stop;
end
end // if (DEBUG_TRACE >= 1)
end // if (`DEBUG_TRACE >= 1)
end // if (checkInstrW)
end // always @ (negedge clk)

10
pipelined/testbench/testbench.sv
View File

@ -87,7 +87,6 @@ logic [3:0] dummy;
"arch64m": if (`M_SUPPORTED) tests = arch64m;
"arch64d": if (`D_SUPPORTED) tests = arch64d;
"imperas64i": tests = imperas64i;
//"imperas64mmu": if (`VIRTMEM_SUPPORTED) tests = imperas64mmu;
"imperas64f": if (`F_SUPPORTED) tests = imperas64f;
"imperas64d": if (`D_SUPPORTED) tests = imperas64d;
"imperas64m": if (`M_SUPPORTED) tests = imperas64m;
@ -95,8 +94,8 @@ logic [3:0] dummy;
"imperas64c": if (`C_SUPPORTED) tests = imperas64c;
else tests = imperas64iNOc;
"testsBP64": tests = testsBP64;
"wally64i": tests = wally64i; // *** redo
"wally64priv": tests = wally64priv;// *** redo
"wally64i": tests = wally64i;
"wally64priv": tests = wally64priv;
"wally64periph": tests = wally64periph;
"coremark": tests = coremark;
endcase
@ -110,15 +109,14 @@ logic [3:0] dummy;
"arch32m": if (`M_SUPPORTED) tests = arch32m;
"arch32f": if (`F_SUPPORTED) tests = arch32f;
"imperas32i": tests = imperas32i;
//"imperas32mmu": if (`VIRTMEM_SUPPORTED) tests = imperas32mmu;
"imperas32f": if (`F_SUPPORTED) tests = imperas32f;
"imperas32m": if (`M_SUPPORTED) tests = imperas32m;
"wally32a": if (`A_SUPPORTED) tests = wally32a;
"imperas32c": if (`C_SUPPORTED) tests = imperas32c;
else tests = imperas32iNOc;
"wally32i": tests = wally32i; // *** redo
"wally32i": tests = wally32i;
"wally32e": tests = wally32e;
"wally32priv": tests = wally32priv; // *** redo
"wally32priv": tests = wally32priv;
"embench": tests = embench;
endcase
end

17
synthDC/Synopsys_stack_trace_12580.txt
View File

@ -1,17 +0,0 @@
GNU gdb (GDB) Red Hat Enterprise Linux 8.2-16.el8
Copyright (C) 2018 Free Software Foundation, Inc.
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law.
Type "show copying" and "show warranty" for details.
This GDB was configured as "x86_64-redhat-linux-gnu".
Type "show configuration" for configuration details.
For bug reporting instructions, please see:
<http://www.gnu.org/software/gdb/bugs/>.
Find the GDB manual and other documentation resources online at:
<http://www.gnu.org/software/gdb/documentation/>.
For help, type "help".
Type "apropos word" to search for commands related to "word".
Attaching to process 12580
(gdb) (gdb) (gdb) (gdb)

17
synthDC/Synopsys_stack_trace_32764.txt
View File

@ -1,17 +0,0 @@
GNU gdb (GDB) Red Hat Enterprise Linux 8.2-16.el8
Copyright (C) 2018 Free Software Foundation, Inc.
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law.
Type "show copying" and "show warranty" for details.
This GDB was configured as "x86_64-redhat-linux-gnu".
Type "show configuration" for configuration details.
For bug reporting instructions, please see:
<http://www.gnu.org/software/gdb/bugs/>.
Find the GDB manual and other documentation resources online at:
<http://www.gnu.org/software/gdb/documentation/>.
For help, type "help".
Type "apropos word" to search for commands related to "word".
Attaching to process 32764
(gdb) (gdb) (gdb) (gdb)

17
synthDC/Synopsys_stack_trace_52064.txt
View File

@ -1,17 +0,0 @@
GNU gdb (GDB) Red Hat Enterprise Linux 8.2-16.el8
Copyright (C) 2018 Free Software Foundation, Inc.
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law.
Type "show copying" and "show warranty" for details.
This GDB was configured as "x86_64-redhat-linux-gnu".
Type "show configuration" for configuration details.
For bug reporting instructions, please see:
<http://www.gnu.org/software/gdb/bugs/>.
Find the GDB manual and other documentation resources online at:
<http://www.gnu.org/software/gdb/documentation/>.
For help, type "help".
Type "apropos word" to search for commands related to "word".
Attaching to process 52064
(gdb) (gdb) (gdb) (gdb)

17
synthDC/Synopsys_stack_trace_55441.txt
View File

@ -1,17 +0,0 @@
GNU gdb (GDB) Red Hat Enterprise Linux 8.2-16.el8
Copyright (C) 2018 Free Software Foundation, Inc.
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law.
Type "show copying" and "show warranty" for details.
This GDB was configured as "x86_64-redhat-linux-gnu".
Type "show configuration" for configuration details.
For bug reporting instructions, please see:
<http://www.gnu.org/software/gdb/bugs/>.
Find the GDB manual and other documentation resources online at:
<http://www.gnu.org/software/gdb/documentation/>.
For help, type "help".
Type "apropos word" to search for commands related to "word".
Attaching to process 55441
(gdb) (gdb) (gdb) (gdb)

17
synthDC/Synopsys_stack_trace_57184.txt
View File

@ -1,17 +0,0 @@
GNU gdb (GDB) Red Hat Enterprise Linux 8.2-16.el8
Copyright (C) 2018 Free Software Foundation, Inc.
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law.
Type "show copying" and "show warranty" for details.
This GDB was configured as "x86_64-redhat-linux-gnu".
Type "show configuration" for configuration details.
For bug reporting instructions, please see:
<http://www.gnu.org/software/gdb/bugs/>.
Find the GDB manual and other documentation resources online at:
<http://www.gnu.org/software/gdb/documentation/>.
For help, type "help".
Type "apropos word" to search for commands related to "word".
Attaching to process 57184
(gdb) (gdb) (gdb) (gdb)

17
synthDC/Synopsys_stack_trace_57185.txt
View File

@ -1,17 +0,0 @@
GNU gdb (GDB) Red Hat Enterprise Linux 8.2-16.el8
Copyright (C) 2018 Free Software Foundation, Inc.
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law.
Type "show copying" and "show warranty" for details.
This GDB was configured as "x86_64-redhat-linux-gnu".
Type "show configuration" for configuration details.
For bug reporting instructions, please see:
<http://www.gnu.org/software/gdb/bugs/>.
Find the GDB manual and other documentation resources online at:
<http://www.gnu.org/software/gdb/documentation/>.
For help, type "help".
Type "apropos word" to search for commands related to "word".
Attaching to process 57185
(gdb) (gdb) (gdb) (gdb)

101
synthDC/bestSynths.csv Normal file
View File

@ -0,0 +1,101 @@
Module,Tech,Width,Target Freq,Delay,Area,L Power (nW),D energy (fJ)
priorityencoder,sky90,8,7994,0.12495900000000001,60.760001,44.346,13.420596600000001
priorityencoder,sky90,16,5753,0.16977,136.220003,77.243,21.255203999999996
priorityencoder,sky90,32,4776,0.20887,379.260006,246.78,50.066139
priorityencoder,sky90,64,4096,0.244022,794.780014,364.853,72.718556
priorityencoder,sky90,128,3409,0.293333,1602.300031,610.009,126.13319000000001
add,sky90,8,3652,0.27337,245.000005,139.276,101.69364
add,sky90,16,2931,0.339912,623.280012,352.919,268.53048
add,sky90,32,2420,0.413219,1330.840024,582.809,520.65594
add,sky90,64,2139,0.467468,2781.240054,1050.0,939.143212
add,sky90,128,1885,0.5304949999999999,6186.740118,2230.0,2147.974254999999
csa,sky90,8,5984,0.166714,306.740006,227.761,164.046576
csa,sky90,16,5984,0.165225,588.000011,322.135,321.1974
csa,sky90,32,5740,0.166714,1160.320023,826.559,570.495308
csa,sky90,64,5984,0.165225,2469.600048,1440.0,1354.3493250000001
csa,sky90,128,5984,0.165225,4897.060095,2990.0,2649.0524250000003
shiftleft,sky90,8,4321,0.23109,250.880004,181.951,70.25136
shiftleft,sky90,16,3355,0.29804,666.400006,558.433,195.51424
shiftleft,sky90,32,2500,0.39945200000000003,1400.420023,738.137,368.29474400000004
shiftleft,sky90,64,2203,0.453859,3914.120062,2680.0,1144.632398
shiftleft,sky90,128,1907,0.5242939999999999,9192.400136,6080.0,2900.3944079999997
comparator,sky90,8,4829,0.206669,198.940004,136.459,48.567215
comparator,sky90,16,4014,0.24886599999999998,355.740006,188.666,62.714231999999996
comparator,sky90,32,3596,0.27763899999999997,697.760013,316.793,109.389766
comparator,sky90,64,3129,0.319542,1372.980026,508.393,204.826422
comparator,sky90,128,2682,0.37267500000000003,2836.120055,772.571,463.6077000000001
flop,sky90,8,7708,0.11434399999999999,133.279999,129.629,341.2939712
flop,sky90,16,7708,0.11434399999999999,266.5599975,259.258,682.4049919999999
flop,sky90,32,7708,0.11434399999999999,533.119995,518.516,1364.69564
flop,sky90,64,8396,0.114344,1066.23999,1040.0,2972.829656
flop,sky90,128,8396,0.114344,2132.4799805,2070.0,5945.087592
mux2,sky90,8,5280,0.188723,63.700001,23.506,19.4762136
mux2,sky90,16,4815,0.202073,119.560002,32.354,37.7674437
mux2,sky90,32,4950,0.199897,374.360008,259.372,135.530166
mux2,sky90,64,4060,0.245667,514.50001,165.954,163.614222
mux2,sky90,128,4004,0.249748,1302.420025,767.078,466.52926399999996
mux4,sky90,8,4655,0.214552,159.740002,86.462,42.0307368
mux4,sky90,16,4452,0.223139,392.0,398.313,103.090218
mux4,sky90,32,3802,0.262263,465.500009,150.568,139.26165300000002
mux4,sky90,64,3699,0.269517,877.100017,304.149,274.90734
mux4,sky90,128,3166,0.31572500000000003,1984.500039,725.267,569.5679000000001
mux8,sky90,8,3577,0.27891699999999997,287.140006,116.648,60.831797699999996
mux8,sky90,16,3419,0.29151,588.000006,280.193,150.71067
mux8,sky90,32,3155,0.314651,1237.740008,639.983,323.14657700000004
mux8,sky90,64,3020,0.330329,2207.940042,730.503,445.613821
mux8,sky90,128,2666,0.37501399999999996,3761.240072,1460.0,854.281892
mult,sky90,8,1310,0.7631560000000001,2194.220041,1440.0,1420.996472
mult,sky90,16,997,1.002926,7519.540137,4940.0,6375.600582
mult,sky90,32,763,1.310613,25200.700446,14900.0,24931.791099000002
mult,sky90,64,632,1.5822660000000002,86011.661365,42600.0,88845.818166
mult,sky90,128,524,1.9083759999999999,296198.144128,114000.0,273311.88559200004
priorityencoder,tsmc28,8,31306,0.031913,8.316,34.836,1.7137280999999998
priorityencoder,tsmc28,16,21202,0.047050999999999996,21.294,73.912,3.8158361
priorityencoder,tsmc28,32,16453,0.06074,62.118,205.801,9.438996
priorityencoder,tsmc28,64,13786,0.07244400000000001,137.088001,428.365,18.328332000000003
priorityencoder,tsmc28,128,11439,0.087412,315.252,980.365,40.908816
add,tsmc28,8,13787,0.072267,33.012,176.194,12.328750199999996
add,tsmc28,16,11520,0.08680199999999999,90.972001,475.452,33.679176
add,tsmc28,32,9810,0.101918,209.286002,1060.0,81.43248200000001
add,tsmc28,64,8203,0.121869,392.616003,1800.0,142.34299200000004
add,tsmc28,128,7210,0.138694,868.140006,4090.0,331.33996600000006
csa,tsmc28,8,23865,0.040776,49.392,473.393,20.918088
csa,tsmc28,16,23865,0.040776,98.783999,946.879,41.75462400000001
csa,tsmc28,32,23865,0.040776,197.567999,1890.0,83.305368
csa,tsmc28,64,23865,0.040776,395.135998,3790.0,166.52918400000001
csa,tsmc28,128,23865,0.040776,790.271996,7570.0,333.099144
shiftleft,tsmc28,8,15183,0.06578,48.384,333.876,15.517502
shiftleft,tsmc28,16,11800,0.084718,130.788,613.549,33.717764
shiftleft,tsmc28,32,9587,0.104304,384.803997,1940.0,101.800704
shiftleft,tsmc28,64,8269,0.120883,967.427998,4980.0,272.8329309999999
shiftleft,tsmc28,128,7023,0.14238299999999998,1836.953994,8670.0,566.541957
comparator,tsmc28,8,17054,0.058548,32.256,160.477,8.752925999999999
comparator,tsmc28,16,13709,0.07280299999999999,48.132,204.944,11.8523284
comparator,tsmc28,32,12136,0.082381,146.16,623.674,35.506211
comparator,tsmc28,64,10862,0.09205799999999999,291.312,1240.0,69.41173199999999
comparator,tsmc28,128,9371,0.106711,558.432,2400.0,127.946489
flop,tsmc28,8,19458,0.048892,15.12,157.268,51.8450768
flop,tsmc28,16,19226,0.048892,30.24,314.578,102.39940480000001
flop,tsmc28,32,20286,0.048892,60.4799995,629.157,216.053748
flop,tsmc28,64,20286,0.048892,120.959999,1260.0,432.107496
flop,tsmc28,128,20286,0.048892,241.919998,2520.0,864.1661
mux2,tsmc28,8,29634,0.033745,16.758,114.564,5.436319499999999
mux2,tsmc28,16,19150,0.052219,15.75,88.448,5.1592372
mux2,tsmc28,32,17903,0.055855999999999996,32.130001,171.146,9.897683199999998
mux2,tsmc28,64,18546,0.053857,90.846,517.414,27.359356000000002
mux2,tsmc28,128,16594,0.060106,184.968,1150.0,58.603350000000006
mux4,tsmc28,8,18130,0.055091999999999995,27.971999,133.963,8.0213952
mux4,tsmc28,16,16440,0.060656,39.438,185.149,12.373824000000003
mux4,tsmc28,32,15168,0.065805,69.174,324.969,23.229165
mux4,tsmc28,64,13915,0.071806,137.465999,648.086,45.59681
mux4,tsmc28,128,13089,0.07639599999999999,296.603997,1440.0,94.501852
mux8,tsmc28,8,12885,0.07751,44.856,215.13,11.905536000000001
mux8,tsmc28,16,12256,0.081543,121.841998,521.624,25.930674
mux8,tsmc28,32,11695,0.085374,168.21,815.694,46.35808200000001
mux8,tsmc28,64,11000,0.090793,304.037999,1490.0,81.895286
mux8,tsmc28,128,10464,0.095475,664.775992,2850.0,153.04642500000003
mult,tsmc28,8,5091,0.196425,516.222001,3840.0,342.95804999999996
mult,tsmc28,16,3819,0.261843,1634.472002,11800.0,1455.3233939999998
mult,tsmc28,32,2973,0.33635600000000004,5141.430011,36900.0,5416.340668
mult,tsmc28,64,2390,0.41840900000000003,16045.092071,109000.0,18545.978925000003
mult,tsmc28,128,1868,0.535328,44272.49428,262000.0,50011.412416
1 Module Tech Width Target Freq Delay Area L Power (nW) D energy (fJ)
2 priorityencoder sky90 8 7994 0.12495900000000001 60.760001 44.346 13.420596600000001
3 priorityencoder sky90 16 5753 0.16977 136.220003 77.243 21.255203999999996
4 priorityencoder sky90 32 4776 0.20887 379.260006 246.78 50.066139
5 priorityencoder sky90 64 4096 0.244022 794.780014 364.853 72.718556
6 priorityencoder sky90 128 3409 0.293333 1602.300031 610.009 126.13319000000001
7 add sky90 8 3652 0.27337 245.000005 139.276 101.69364
8 add sky90 16 2931 0.339912 623.280012 352.919 268.53048
9 add sky90 32 2420 0.413219 1330.840024 582.809 520.65594
10 add sky90 64 2139 0.467468 2781.240054 1050.0 939.143212
11 add sky90 128 1885 0.5304949999999999 6186.740118 2230.0 2147.974254999999
12 csa sky90 8 5984 0.166714 306.740006 227.761 164.046576
13 csa sky90 16 5984 0.165225 588.000011 322.135 321.1974
14 csa sky90 32 5740 0.166714 1160.320023 826.559 570.495308
15 csa sky90 64 5984 0.165225 2469.600048 1440.0 1354.3493250000001
16 csa sky90 128 5984 0.165225 4897.060095 2990.0 2649.0524250000003
17 shiftleft sky90 8 4321 0.23109 250.880004 181.951 70.25136
18 shiftleft sky90 16 3355 0.29804 666.400006 558.433 195.51424
19 shiftleft sky90 32 2500 0.39945200000000003 1400.420023 738.137 368.29474400000004
20 shiftleft sky90 64 2203 0.453859 3914.120062 2680.0 1144.632398
21 shiftleft sky90 128 1907 0.5242939999999999 9192.400136 6080.0 2900.3944079999997
22 comparator sky90 8 4829 0.206669 198.940004 136.459 48.567215
23 comparator sky90 16 4014 0.24886599999999998 355.740006 188.666 62.714231999999996
24 comparator sky90 32 3596 0.27763899999999997 697.760013 316.793 109.389766
25 comparator sky90 64 3129 0.319542 1372.980026 508.393 204.826422
26 comparator sky90 128 2682 0.37267500000000003 2836.120055 772.571 463.6077000000001
27 flop sky90 8 7708 0.11434399999999999 133.279999 129.629 341.2939712
28 flop sky90 16 7708 0.11434399999999999 266.5599975 259.258 682.4049919999999
29 flop sky90 32 7708 0.11434399999999999 533.119995 518.516 1364.69564
30 flop sky90 64 8396 0.114344 1066.23999 1040.0 2972.829656
31 flop sky90 128 8396 0.114344 2132.4799805 2070.0 5945.087592
32 mux2 sky90 8 5280 0.188723 63.700001 23.506 19.4762136
33 mux2 sky90 16 4815 0.202073 119.560002 32.354 37.7674437
34 mux2 sky90 32 4950 0.199897 374.360008 259.372 135.530166
35 mux2 sky90 64 4060 0.245667 514.50001 165.954 163.614222
36 mux2 sky90 128 4004 0.249748 1302.420025 767.078 466.52926399999996
37 mux4 sky90 8 4655 0.214552 159.740002 86.462 42.0307368
38 mux4 sky90 16 4452 0.223139 392.0 398.313 103.090218
39 mux4 sky90 32 3802 0.262263 465.500009 150.568 139.26165300000002
40 mux4 sky90 64 3699 0.269517 877.100017 304.149 274.90734
41 mux4 sky90 128 3166 0.31572500000000003 1984.500039 725.267 569.5679000000001
42 mux8 sky90 8 3577 0.27891699999999997 287.140006 116.648 60.831797699999996
43 mux8 sky90 16 3419 0.29151 588.000006 280.193 150.71067
44 mux8 sky90 32 3155 0.314651 1237.740008 639.983 323.14657700000004
45 mux8 sky90 64 3020 0.330329 2207.940042 730.503 445.613821
46 mux8 sky90 128 2666 0.37501399999999996 3761.240072 1460.0 854.281892
47 mult sky90 8 1310 0.7631560000000001 2194.220041 1440.0 1420.996472
48 mult sky90 16 997 1.002926 7519.540137 4940.0 6375.600582
49 mult sky90 32 763 1.310613 25200.700446 14900.0 24931.791099000002
50 mult sky90 64 632 1.5822660000000002 86011.661365 42600.0 88845.818166
51 mult sky90 128 524 1.9083759999999999 296198.144128 114000.0 273311.88559200004
52 priorityencoder tsmc28 8 31306 0.031913 8.316 34.836 1.7137280999999998
53 priorityencoder tsmc28 16 21202 0.047050999999999996 21.294 73.912 3.8158361
54 priorityencoder tsmc28 32 16453 0.06074 62.118 205.801 9.438996
55 priorityencoder tsmc28 64 13786 0.07244400000000001 137.088001 428.365 18.328332000000003
56 priorityencoder tsmc28 128 11439 0.087412 315.252 980.365 40.908816
57 add tsmc28 8 13787 0.072267 33.012 176.194 12.328750199999996
58 add tsmc28 16 11520 0.08680199999999999 90.972001 475.452 33.679176
59 add tsmc28 32 9810 0.101918 209.286002 1060.0 81.43248200000001
60 add tsmc28 64 8203 0.121869 392.616003 1800.0 142.34299200000004
61 add tsmc28 128 7210 0.138694 868.140006 4090.0 331.33996600000006
62 csa tsmc28 8 23865 0.040776 49.392 473.393 20.918088
63 csa tsmc28 16 23865 0.040776 98.783999 946.879 41.75462400000001
64 csa tsmc28 32 23865 0.040776 197.567999 1890.0 83.305368
65 csa tsmc28 64 23865 0.040776 395.135998 3790.0 166.52918400000001
66 csa tsmc28 128 23865 0.040776 790.271996 7570.0 333.099144
67 shiftleft tsmc28 8 15183 0.06578 48.384 333.876 15.517502
68 shiftleft tsmc28 16 11800 0.084718 130.788 613.549 33.717764
69 shiftleft tsmc28 32 9587 0.104304 384.803997 1940.0 101.800704
70 shiftleft tsmc28 64 8269 0.120883 967.427998 4980.0 272.8329309999999
71 shiftleft tsmc28 128 7023 0.14238299999999998 1836.953994 8670.0 566.541957
72 comparator tsmc28 8 17054 0.058548 32.256 160.477 8.752925999999999
73 comparator tsmc28 16 13709 0.07280299999999999 48.132 204.944 11.8523284
74 comparator tsmc28 32 12136 0.082381 146.16 623.674 35.506211
75 comparator tsmc28 64 10862 0.09205799999999999 291.312 1240.0 69.41173199999999
76 comparator tsmc28 128 9371 0.106711 558.432 2400.0 127.946489
77 flop tsmc28 8 19458 0.048892 15.12 157.268 51.8450768
78 flop tsmc28 16 19226 0.048892 30.24 314.578 102.39940480000001
79 flop tsmc28 32 20286 0.048892 60.4799995 629.157 216.053748
80 flop tsmc28 64 20286 0.048892 120.959999 1260.0 432.107496
81 flop tsmc28 128 20286 0.048892 241.919998 2520.0 864.1661
82 mux2 tsmc28 8 29634 0.033745 16.758 114.564 5.436319499999999
83 mux2 tsmc28 16 19150 0.052219 15.75 88.448 5.1592372
84 mux2 tsmc28 32 17903 0.055855999999999996 32.130001 171.146 9.897683199999998
85 mux2 tsmc28 64 18546 0.053857 90.846 517.414 27.359356000000002
86 mux2 tsmc28 128 16594 0.060106 184.968 1150.0 58.603350000000006
87 mux4 tsmc28 8 18130 0.055091999999999995 27.971999 133.963 8.0213952
88 mux4 tsmc28 16 16440 0.060656 39.438 185.149 12.373824000000003
89 mux4 tsmc28 32 15168 0.065805 69.174 324.969 23.229165
90 mux4 tsmc28 64 13915 0.071806 137.465999 648.086 45.59681
91 mux4 tsmc28 128 13089 0.07639599999999999 296.603997 1440.0 94.501852
92 mux8 tsmc28 8 12885 0.07751 44.856 215.13 11.905536000000001
93 mux8 tsmc28 16 12256 0.081543 121.841998 521.624 25.930674
94 mux8 tsmc28 32 11695 0.085374 168.21 815.694 46.35808200000001
95 mux8 tsmc28 64 11000 0.090793 304.037999 1490.0 81.895286
96 mux8 tsmc28 128 10464 0.095475 664.775992 2850.0 153.04642500000003
97 mult tsmc28 8 5091 0.196425 516.222001 3840.0 342.95804999999996
98 mult tsmc28 16 3819 0.261843 1634.472002 11800.0 1455.3233939999998
99 mult tsmc28 32 2973 0.33635600000000004 5141.430011 36900.0 5416.340668
100 mult tsmc28 64 2390 0.41840900000000003 16045.092071 109000.0 18545.978925000003
101 mult tsmc28 128 1868 0.535328 44272.49428 262000.0 50011.412416

67
synthDC/crte_000012580.txt
View File

@ -1,67 +0,0 @@
CRTE_SNAPSHOT_START
SECTION_CRTE_VERSION
3.0
SECTION_PID
12580
SECTION_POLLING_INTERVAL
5
SECTION_DATE_TIME
Mon May 16 23:44:09 UTC 2022 (1652744649)
SECTION_OS_VERSION
osname: Linux
hostname: tera
arch: x86_64
release_version: 5.4.157-1-pve
SECTION_IPC_INFO
------ Message Queues --------
key msqid owner perms used-bytes messages
------ Shared Memory Segments --------
key shmid owner perms bytes nattch status
0x00000000 15859713 nwhyte-agu 600 524288 2 dest
0x00000000 360451 nwhyte-agu 600 524288 2 dest
0x00000000 65540 kkim 600 134217728 2 dest
0x00000000 557061 nwhyte-agu 600 67108864 2 dest
0x00000000 6 harris 600 524288 2 dest
0x00000000 7 harris 600 524288 2 dest
0x00000000 5275656 harris 600 2097152 2 dest
0x00000000 11993097 kkim 600 524288 2 dest
0x00000000 15892490 kkim 600 524288 2 dest
0x00000000 11 harris 600 524288 2 SECTION_ULIMIT
core file size (blocks, -c) 0
data seg size (kbytes, -d) unlimited
scheduling priority (-e) 0
file size (blocks, -f) unlimited
pending signals (-i) 515072
max locked memory (kbytes, -l) 64
max memory size (kbytes, -m) unlimited
open files (-n) 524288
pipe size (512 bytes, -p) 8
POSIX message queues (bytes, -q) 819200
real-time priority (-r) 0
stack size (kbytes, -s) unlimited
cpu time (seconds, -t) unlimited
max user processes (-u) 515072
virtual memory (kbytes, -v) unlimited
file locks (-x) unlimited
SECTION_SYSCONF
_SC_THREAD_SAFE_FUNCTIONS= 200809
_SC_CLK_TCK= 100
_SC_OPEN_MAX= 524288
_SC_PAGE_SIZE= 4096
_SC_ARG_MAX= 4611686018427387903
_SC_CHILD_MAX= 515072
_SC_LINE_MAX= 2048
SECTION_FULL_COMMAND
/cad/synopsys/SYN/linux64/syn/bin/common_shell_exec -64 -shell dc_shell -r /cad/synopsys/SYN -f scripts/synth.tcl
SECTION_CPUINFO

67
synthDC/crte_000032764.txt
View File

@ -1,67 +0,0 @@
CRTE_SNAPSHOT_START
SECTION_CRTE_VERSION
3.0
SECTION_PID
32764
SECTION_POLLING_INTERVAL
5
SECTION_DATE_TIME
Tue May 17 00:05:18 UTC 2022 (1652745918)
SECTION_OS_VERSION
osname: Linux
hostname: tera
arch: x86_64
release_version: 5.4.157-1-pve
SECTION_IPC_INFO
------ Message Queues --------
key msqid owner perms used-bytes messages
------ Shared Memory Segments --------
key shmid owner perms bytes nattch status
0x00000000 360451 nwhyte-agu 600 524288 2 dest
0x00000000 65540 kkim 600 134217728 2 dest
0x00000000 557061 nwhyte-agu 600 67108864 2 dest
0x00000000 6 harris 600 524288 2 dest
0x00000000 7 harris 600 524288 2 dest
0x00000000 5275656 harris 600 2097152 2 dest
0x00000000 11993097 kkim 600 524288 2 dest
0x00000000 15892490 kkim 600 524288 2 dest
0x00000000 11 harris 600 524288 2 dest
0x00000000 15204364 harris 644 790528 3 SECTION_ULIMIT
core file size (blocks, -c) 0
data seg size (kbytes, -d) unlimited
scheduling priority (-e) 0
file size (blocks, -f) unlimited
pending signals (-i) 515072
max locked memory (kbytes, -l) 64
max memory size (kbytes, -m) unlimited
open files (-n) 524288
pipe size (512 bytes, -p) 8
POSIX message queues (bytes, -q) 819200
real-time priority (-r) 0
stack size (kbytes, -s) unlimited
cpu time (seconds, -t) unlimited
max user processes (-u) 515072
virtual memory (kbytes, -v) unlimited
file locks (-x) unlimited
SECTION_SYSCONF
_SC_THREAD_SAFE_FUNCTIONS= 200809
_SC_CLK_TCK= 100
_SC_OPEN_MAX= 524288
_SC_PAGE_SIZE= 4096
_SC_ARG_MAX= 4611686018427387903
_SC_CHILD_MAX= 515072
_SC_LINE_MAX= 2048
SECTION_FULL_COMMAND
/cad/synopsys/SYN/linux64/syn/bin/common_shell_exec -64 -shell dc_shell -r /cad/synopsys/SYN -f scripts/synth.tcl
SECTION_CPUINFO

67
synthDC/crte_000052064.txt
View File

@ -1,67 +0,0 @@
CRTE_SNAPSHOT_START
SECTION_CRTE_VERSION
3.0
SECTION_PID
52064
SECTION_POLLING_INTERVAL
5
SECTION_DATE_TIME
Thu May 12 21:44:48 UTC 2022 (1652391888)
SECTION_OS_VERSION
osname: Linux
hostname: tera
arch: x86_64
release_version: 5.4.157-1-pve
SECTION_IPC_INFO
------ Message Queues --------
key msqid owner perms used-bytes messages
------ Shared Memory Segments --------
key shmid owner perms bytes nattch status
0x00000000 360451 nwhyte-agu 600 524288 2 dest
0x00000000 65540 kkim 600 134217728 2 dest
0x00000000 557061 nwhyte-agu 600 67108864 2 dest
0x00000000 6 harris 600 524288 2 dest
0x00000000 7 harris 600 524288 2 dest
0x00000000 5275656 harris 600 2097152 2 dest
0x00000000 11993097 kkim 600 524288 2 dest
0x00000000 11 harris 600 524288 2 dest
0x00000000 15204364 harris 644 790528 2 dest
0x00000000 7372813 chuang 600 524288 2 SECTION_ULIMIT
core file size (blocks, -c) 0
data seg size (kbytes, -d) unlimited
scheduling priority (-e) 0
file size (blocks, -f) unlimited
pending signals (-i) 515072
max locked memory (kbytes, -l) 64
max memory size (kbytes, -m) unlimited
open files (-n) 524288
pipe size (512 bytes, -p) 8
POSIX message queues (bytes, -q) 819200
real-time priority (-r) 0
stack size (kbytes, -s) unlimited
cpu time (seconds, -t) unlimited
max user processes (-u) 515072
virtual memory (kbytes, -v) unlimited
file locks (-x) unlimited
SECTION_SYSCONF
_SC_THREAD_SAFE_FUNCTIONS= 200809
_SC_CLK_TCK= 100
_SC_OPEN_MAX= 524288
_SC_PAGE_SIZE= 4096
_SC_ARG_MAX= 4611686018427387903
_SC_CHILD_MAX= 515072
_SC_LINE_MAX= 2048
SECTION_FULL_COMMAND
/cad/synopsys/SYN/linux64/syn/bin/common_shell_exec -64 -shell dc_shell -r /cad/synopsys/SYN -f scripts/synth.tcl
SECTION_CPUINFO

67
synthDC/crte_000055441.txt
View File

@ -1,67 +0,0 @@
CRTE_SNAPSHOT_START
SECTION_CRTE_VERSION
3.0
SECTION_PID
55441
SECTION_POLLING_INTERVAL
5
SECTION_DATE_TIME
Thu May 12 21:47:47 UTC 2022 (1652392067)
SECTION_OS_VERSION
osname: Linux
hostname: tera
arch: x86_64
release_version: 5.4.157-1-pve
SECTION_IPC_INFO
------ Message Queues --------
key msqid owner perms used-bytes messages
------ Shared Memory Segments --------
key shmid owner perms bytes nattch status
0x00000000 360451 nwhyte-agu 600 524288 2 dest
0x00000000 65540 kkim 600 134217728 2 dest
0x00000000 557061 nwhyte-agu 600 67108864 2 dest
0x00000000 6 harris 600 524288 2 dest
0x00000000 7 harris 600 524288 2 dest
0x00000000 5275656 harris 600 2097152 2 dest
0x00000000 11993097 kkim 600 524288 2 dest
0x00000000 11 harris 600 524288 2 dest
0x00000000 15204364 harris 644 790528 2 dest
0x00000000 7372813 chuang 600 524288 2 SECTION_ULIMIT
core file size (blocks, -c) 0
data seg size (kbytes, -d) unlimited
scheduling priority (-e) 0
file size (blocks, -f) unlimited
pending signals (-i) 515072
max locked memory (kbytes, -l) 64
max memory size (kbytes, -m) unlimited
open files (-n) 524288
pipe size (512 bytes, -p) 8
POSIX message queues (bytes, -q) 819200
real-time priority (-r) 0
stack size (kbytes, -s) unlimited
cpu time (seconds, -t) unlimited
max user processes (-u) 515072
virtual memory (kbytes, -v) unlimited
file locks (-x) unlimited
SECTION_SYSCONF
_SC_THREAD_SAFE_FUNCTIONS= 200809
_SC_CLK_TCK= 100
_SC_OPEN_MAX= 524288
_SC_PAGE_SIZE= 4096
_SC_ARG_MAX= 4611686018427387903
_SC_CHILD_MAX= 515072
_SC_LINE_MAX= 2048
SECTION_FULL_COMMAND
/cad/synopsys/SYN/linux64/syn/bin/common_shell_exec -64 -shell dc_shell -r /cad/synopsys/SYN -f scripts/synth.tcl
SECTION_CPUINFO

67
synthDC/crte_000057184.txt
View File

@ -1,67 +0,0 @@
CRTE_SNAPSHOT_START
SECTION_CRTE_VERSION
3.0
SECTION_PID
57184
SECTION_POLLING_INTERVAL
5
SECTION_DATE_TIME
Mon May 16 22:54:26 UTC 2022 (1652741666)
SECTION_OS_VERSION
osname: Linux
hostname: tera
arch: x86_64
release_version: 5.4.157-1-pve
SECTION_IPC_INFO
------ Message Queues --------
key msqid owner perms used-bytes messages
------ Shared Memory Segments --------
key shmid owner perms bytes nattch status
0x00000000 15859713 nwhyte-agu 600 524288 2 dest
0x00000000 360451 nwhyte-agu 600 524288 2 dest
0x00000000 65540 kkim 600 134217728 2 dest
0x00000000 557061 nwhyte-agu 600 67108864 2 dest
0x00000000 6 harris 600 524288 2 dest
0x00000000 7 harris 600 524288 2 dest
0x00000000 5275656 harris 600 2097152 2 dest
0x00000000 11993097 kkim 600 524288 2 dest
0x00000000 15892490 kkim 600 524288 2 dest
0x00000000 11 harris 600 524288 2 SECTION_ULIMIT
core file size (blocks, -c) 0
data seg size (kbytes, -d) unlimited
scheduling priority (-e) 0
file size (blocks, -f) unlimited
pending signals (-i) 515072
max locked memory (kbytes, -l) 64
max memory size (kbytes, -m) unlimited
open files (-n) 524288
pipe size (512 bytes, -p) 8
POSIX message queues (bytes, -q) 819200
real-time priority (-r) 0
stack size (kbytes, -s) unlimited
cpu time (seconds, -t) unlimited
max user processes (-u) 515072
virtual memory (kbytes, -v) unlimited
file locks (-x) unlimited
SECTION_SYSCONF
_SC_THREAD_SAFE_FUNCTIONS= 200809
_SC_CLK_TCK= 100
_SC_OPEN_MAX= 524288
_SC_PAGE_SIZE= 4096
_SC_ARG_MAX= 4611686018427387903
_SC_CHILD_MAX= 515072
_SC_LINE_MAX= 2048
SECTION_FULL_COMMAND
/cad/synopsys/SYN/linux64/syn/bin/common_shell_exec -64 -shell dc_shell -r /cad/synopsys/SYN -f scripts/synth.tcl
SECTION_CPUINFO

67
synthDC/crte_000057185.txt
View File

@ -1,67 +0,0 @@
CRTE_SNAPSHOT_START
SECTION_CRTE_VERSION
3.0
SECTION_PID
57185
SECTION_POLLING_INTERVAL
5
SECTION_DATE_TIME
Mon May 16 22:54:26 UTC 2022 (1652741666)
SECTION_OS_VERSION
osname: Linux
hostname: tera
arch: x86_64
release_version: 5.4.157-1-pve
SECTION_IPC_INFO
------ Message Queues --------
key msqid owner perms used-bytes messages
------ Shared Memory Segments --------
key shmid owner perms bytes nattch status
0x00000000 15859713 nwhyte-agu 600 524288 2 dest
0x00000000 360451 nwhyte-agu 600 524288 2 dest
0x00000000 65540 kkim 600 134217728 2 dest
0x00000000 557061 nwhyte-agu 600 67108864 2 dest
0x00000000 6 harris 600 524288 2 dest
0x00000000 7 harris 600 524288 2 dest
0x00000000 5275656 harris 600 2097152 2 dest
0x00000000 11993097 kkim 600 524288 2 dest
0x00000000 15892490 kkim 600 524288 2 dest
0x00000000 11 harris 600 524288 2 SECTION_ULIMIT
core file size (blocks, -c) 0
data seg size (kbytes, -d) unlimited
scheduling priority (-e) 0
file size (blocks, -f) unlimited
pending signals (-i) 515072
max locked memory (kbytes, -l) 64
max memory size (kbytes, -m) unlimited
open files (-n) 524288
pipe size (512 bytes, -p) 8
POSIX message queues (bytes, -q) 819200
real-time priority (-r) 0
stack size (kbytes, -s) unlimited
cpu time (seconds, -t) unlimited
max user processes (-u) 515072
virtual memory (kbytes, -v) unlimited
file locks (-x) unlimited
SECTION_SYSCONF
_SC_THREAD_SAFE_FUNCTIONS= 200809
_SC_CLK_TCK= 100
_SC_OPEN_MAX= 524288
_SC_PAGE_SIZE= 4096
_SC_ARG_MAX= 4611686018427387903
_SC_CHILD_MAX= 515072
_SC_LINE_MAX= 2048
SECTION_FULL_COMMAND
/cad/synopsys/SYN/linux64/syn/bin/common_shell_exec -64 -shell dc_shell -r /cad/synopsys/SYN -f scripts/synth.tcl
SECTION_CPUINFO

998
synthDC/nm_500_MHz_2022-03-22-20-43_2947df5b/synth.out
View File

@ -1,998 +0,0 @@
Design Compiler Graphical
DC Ultra (TM)
DFTMAX (TM)
Power Compiler (TM)
DesignWare (R)
DC Expert (TM)
Design Vision (TM)
HDL Compiler (TM)
VHDL Compiler (TM)
DFT Compiler
Design Compiler(R)
Version S-2021.06-SP4 for linux64 - Nov 23, 2021
Copyright (c) 1988 - 2021 Synopsys, Inc.
This software and the associated documentation are proprietary to Synopsys,
Inc. This software may only be used in accordance with the terms and conditions
of a written license agreement with Synopsys, Inc. All other use, reproduction,
or distribution of this software is strictly prohibited. Licensed Products
communicate with Synopsys servers for the purpose of providing software
updates, detecting software piracy and verifying that customers are using
Licensed Products in conformity with the applicable License Key for such
Licensed Products. Synopsys will use information gathered in connection with
this process to deliver software updates and pursue software pirates and
infringers.
Inclusivity & Diversity - Visit SolvNetPlus to read the "Synopsys Statement on
Inclusivity and Diversity" (Refer to article 000036315 at
https://solvnetplus.synopsys.com)
Initializing...
#
# Synthesis Synopsys Flow
# james.stine@okstate.edu 27 Sep 2015
#
# Ignore unnecessary warnings:
# intraassignment delays for nonblocking assignments are ignored
suppress_message {VER-130}
# statements in initial blocks are ignored
suppress_message {VER-281}
suppress_message {VER-173}
# Enable Multicore
set_host_options -max_cores $::env(MAXCORES)
1
# get outputDir from environment (Makefile)
set outputDir $::env(OUTPUTDIR)
runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b
set cfgName $::env(CONFIG)
rv32e
# Config
set hdl_src "../pipelined/src"
../pipelined/src
set cfg "${hdl_src}/../config/${cfgName}/wally-config.vh"
../pipelined/src/../config/rv32e/wally-config.vh
set saifpower $::env(SAIFPOWER)
0
set maxopt $::env(MAXOPT)
0
eval file copy -force ${cfg} {hdl/}
eval file copy -force ${cfg} $outputDir
eval file copy -force [glob ${hdl_src}/../config/shared/*.vh] {hdl/}
eval file copy -force [glob ${hdl_src}/*/*.sv] {hdl/}
eval file copy -force [glob ${hdl_src}/*/flop/*.sv] {hdl/}
# Enables name mapping
if { $saifpower == 1 } {
saif_map -start
}
# Verilog files
set my_verilog_files [glob hdl/*]
hdl/gpio.sv hdl/cla64.sv hdl/cvtfp.sv hdl/flopenrc.sv hdl/csrm.sv hdl/adrdec.sv hdl/fpdiv.sv hdl/convert_inputs.sv hdl/forward.sv hdl/fpdiv_pipe.sv hdl/flopenl.sv hdl/unpacking.sv hdl/tlbcontrol.sv hdl/bpred.sv hdl/pmachecker.sv hdl/satCounter2.sv hdl/csr.sv hdl/fsm_fpdiv_pipe.sv hdl/prioritythermometer.sv hdl/mmu.sv hdl/csrn.sv hdl/ahblite.sv hdl/wally-config.vh hdl/wally-shared.vh hdl/cachereplacementpolicy.sv hdl/privileged.sv hdl/tlbmixer.sv hdl/privdec.sv hdl/or_rows.sv hdl/fctrl.sv hdl/sram1p1rw.sv hdl/unpack.sv hdl/decompress.sv hdl/extend.sv hdl/wally-constants.vh hdl/muldiv.sv hdl/tlbcamline.sv hdl/tlbramline.sv hdl/fcvtint.sv hdl/fcvtfp.sv hdl/regfile.sv hdl/sbtm_a0.sv hdl/subwordwrite.sv hdl/flopen.sv hdl/alu.sv hdl/cla12.sv hdl/dtim.sv hdl/csrsr.sv hdl/datapath.sv hdl/mux.sv hdl/adderparts.sv hdl/sbtm_a1.sv hdl/simpleram.sv hdl/sbtm_a3.sv hdl/busfsm.sv hdl/cachefsm.sv hdl/floprc.sv hdl/ieu.sv hdl/wallypipelinedcore.sv hdl/fsm_fpdiv.sv hdl/pmpadrdec.sv hdl/rounder_denorm.sv hdl/uncore.sv hdl/localHistoryPredictor.sv hdl/mul.sv hdl/clint.sv hdl/divconv_pipe.sv hdl/adder.sv hdl/tlb.sv hdl/uart.sv hdl/twoBitPredictor.sv hdl/sbtm_a2.sv hdl/csri.sv hdl/cacheway.sv hdl/amoalu.sv hdl/plic.sv hdl/interlockfsm.sv hdl/hptw.sv hdl/RAsPredictor.sv hdl/priorityonehot.sv hdl/fpudivsqrtrecur.sv hdl/synchronizer.sv hdl/faddcvt.sv hdl/fma16.sv hdl/intdivrestoringstep.sv hdl/ifu.sv hdl/redundantmul.sv hdl/pmpchecker.sv hdl/fclassify.sv hdl/tlbcam.sv hdl/fsgn.sv hdl/adrdecs.sv hdl/shifter.sv hdl/fma.sv hdl/wallypipelinedsoc.sv hdl/counter.sv hdl/rounder_div.sv hdl/trap.sv hdl/clockgater.sv hdl/SRAM2P1R1W.sv hdl/tlbram.sv hdl/neg.sv hdl/csrc.sv hdl/csru.sv hdl/lzd_denorm.sv hdl/comparator.sv hdl/fcvt.sv hdl/cla52.sv hdl/divconv.sv hdl/busdp.sv hdl/subcachelineread.sv hdl/subwordread.sv hdl/cache.sv hdl/exception_div.sv hdl/arrs.sv hdl/uartPC16550D.sv hdl/fhazard.sv hdl/fcmp.sv hdl/sbtm_div.sv hdl/decoder.sv hdl/controller.sv hdl/sbtm_sqrt.sv hdl/intdivrestoring.sv hdl/spillsupport.sv hdl/convert_inputs_div.sv hdl/swbytemask.sv hdl/flopr.sv hdl/lsuvirtmen.sv hdl/tlblru.sv hdl/onehotdecoder.sv hdl/fpudivsqrtrecurcore.sv hdl/flop.sv hdl/globalHistoryPredictor.sv hdl/fregfile.sv hdl/fpu.sv hdl/csrs.sv hdl/flopens.sv hdl/atomic.sv hdl/lsu.sv hdl/shifter_denorm.sv hdl/gsharePredictor.sv hdl/ram.sv hdl/hazard.sv hdl/BTBPredictor.sv hdl/flopenr.sv hdl/lrsc.sv hdl/exception.sv
# Set toplevel
set my_toplevel $::env(DESIGN)
wallypipelinedcore
# Set number of significant digits
set report_default_significant_digits 6
6
# V(HDL) Unconnectoed Pins Output
set verilogout_show_unconnected_pins "true"
true
set vhdlout_show_unconnected_pins "true"
true
# Due to parameterized Verilog must use analyze/elaborate and not
# read_verilog/vhdl (change to pull in Verilog and/or VHDL)
#
define_design_lib WORK -path ./WORK
1
analyze -f sverilog -lib WORK $my_verilog_files
Running PRESTO HDLC
Compiling source file ./hdl/gpio.sv
Opening include file ./hdl/wally-config.vh
Opening include file ./hdl/wally-shared.vh
Opening include file ./hdl/wally-constants.vh
Compiling source file ./hdl/cla64.sv
Compiling source file ./hdl/cvtfp.sv
Opening include file ./hdl/wally-config.vh
Opening include file ./hdl/wally-shared.vh
Opening include file ./hdl/wally-constants.vh
Compiling source file ./hdl/flopenrc.sv
Opening include file ./hdl/wally-config.vh
Opening include file ./hdl/wally-shared.vh
Opening include file ./hdl/wally-constants.vh
Compiling source file ./hdl/csrm.sv
Opening include file ./hdl/wally-config.vh
Opening include file ./hdl/wally-shared.vh
Opening include file ./hdl/wally-constants.vh
Compiling source file ./hdl/adrdec.sv
Opening include file ./hdl/wally-config.vh
Opening include file ./hdl/wally-shared.vh
Opening include file ./hdl/wally-constants.vh
Compiling source file ./hdl/fpdiv.sv
Compiling source file ./hdl/convert_inputs.sv
Compiling source file ./hdl/forward.sv
Opening include file ./hdl/wally-config.vh
Opening include file ./hdl/wally-shared.vh
Opening include file ./hdl/wally-constants.vh
Compiling source file ./hdl/fpdiv_pipe.sv
Compiling source file ./hdl/flopenl.sv
Opening include file ./hdl/wally-config.vh
Opening include file ./hdl/wally-shared.vh
Opening include file ./hdl/wally-constants.vh
Compiling source file ./hdl/unpacking.sv
Opening include file ./hdl/wally-config.vh
Opening include file ./hdl/wally-shared.vh
Opening include file ./hdl/wally-constants.vh
Compiling source file ./hdl/tlbcontrol.sv
Opening include file ./hdl/wally-config.vh
Opening include file ./hdl/wally-shared.vh
Opening include file ./hdl/wally-constants.vh
Compiling source file ./hdl/bpred.sv
Opening include file ./hdl/wally-config.vh
Opening include file ./hdl/wally-shared.vh
Opening include file ./hdl/wally-constants.vh
Compiling source file ./hdl/pmachecker.sv
Opening include file ./hdl/wally-config.vh
Opening include file ./hdl/wally-shared.vh
Opening include file ./hdl/wally-constants.vh
Compiling source file ./hdl/satCounter2.sv
Opening include file ./hdl/wally-config.vh
Opening include file ./hdl/wally-shared.vh
Opening include file ./hdl/wally-constants.vh
Compiling source file ./hdl/csr.sv
Opening include file ./hdl/wally-config.vh
Opening include file ./hdl/wally-shared.vh
Opening include file ./hdl/wally-constants.vh
Compiling source file ./hdl/fsm_fpdiv_pipe.sv
Compiling source file ./hdl/prioritythermometer.sv
Opening include file ./hdl/wally-config.vh
Opening include file ./hdl/wally-shared.vh
Opening include file ./hdl/wally-constants.vh
Compiling source file ./hdl/mmu.sv
Opening include file ./hdl/wally-config.vh
Opening include file ./hdl/wally-shared.vh
Opening include file ./hdl/wally-constants.vh
Compiling source file ./hdl/csrn.sv
Opening include file ./hdl/wally-config.vh
Opening include file ./hdl/wally-shared.vh
Opening include file ./hdl/wally-constants.vh
Compiling source file ./hdl/ahblite.sv
Opening include file ./hdl/wally-config.vh
Opening include file ./hdl/wally-shared.vh
Opening include file ./hdl/wally-constants.vh
Compiling source file ./hdl/wally-config.vh
Opening include file ./hdl/wally-shared.vh
Opening include file ./hdl/wally-constants.vh
Compiling source file ./hdl/wally-shared.vh
Opening include file ./hdl/wally-constants.vh
Compiling source file ./hdl/cachereplacementpolicy.sv
Opening include file ./hdl/wally-config.vh
Opening include file ./hdl/wally-shared.vh
Opening include file ./hdl/wally-constants.vh
Compiling source file ./hdl/privileged.sv
Opening include file ./hdl/wally-config.vh
Opening include file ./hdl/wally-shared.vh
Opening include file ./hdl/wally-constants.vh
Compiling source file ./hdl/tlbmixer.sv
Opening include file ./hdl/wally-config.vh
Opening include file ./hdl/wally-shared.vh
Opening include file ./hdl/wally-constants.vh
Compiling source file ./hdl/privdec.sv
Opening include file ./hdl/wally-config.vh
Opening include file ./hdl/wally-shared.vh
Opening include file ./hdl/wally-constants.vh
Compiling source file ./hdl/or_rows.sv
Opening include file ./hdl/wally-config.vh
Opening include file ./hdl/wally-shared.vh
Opening include file ./hdl/wally-constants.vh
Compiling source file ./hdl/fctrl.sv
Compiling source file ./hdl/sram1p1rw.sv
Compiling source file ./hdl/unpack.sv
Opening include file ./hdl/wally-config.vh
Opening include file ./hdl/wally-shared.vh
Opening include file ./hdl/wally-constants.vh
Compiling source file ./hdl/decompress.sv
Opening include file ./hdl/wally-config.vh
Opening include file ./hdl/wally-shared.vh
Opening include file ./hdl/wally-constants.vh
Error: ./hdl/unpack.sv:100: Procedural-continuous assignments are not supported by synthesis. (VER-966)
Error: ./hdl/unpack.sv:101: Procedural-continuous assignments are not supported by synthesis. (VER-966)
Error: ./hdl/unpack.sv:102: Procedural-continuous assignments are not supported by synthesis. (VER-966)
Error: ./hdl/unpack.sv:104: Procedural-continuous assignments are not supported by synthesis. (VER-966)
Error: ./hdl/unpack.sv:105: Procedural-continuous assignments are not supported by synthesis. (VER-966)
Error: ./hdl/unpack.sv:106: Procedural-continuous assignments are not supported by synthesis. (VER-966)
Error: ./hdl/unpack.sv:108: Procedural-continuous assignments are not supported by synthesis. (VER-966)
Error: ./hdl/unpack.sv:109: Procedural-continuous assignments are not supported by synthesis. (VER-966)
Error: ./hdl/unpack.sv:110: Procedural-continuous assignments are not supported by synthesis. (VER-966)
Error: ./hdl/unpack.sv:112: Procedural-continuous assignments are not supported by synthesis. (VER-966)
Error: ./hdl/unpack.sv:113: Procedural-continuous assignments are not supported by synthesis. (VER-966)
Error: ./hdl/unpack.sv:114: Procedural-continuous assignments are not supported by synthesis. (VER-966)
Error: ./hdl/unpack.sv:116: Procedural-continuous assignments are not supported by synthesis. (VER-966)
Error: ./hdl/unpack.sv:117: Procedural-continuous assignments are not supported by synthesis. (VER-966)
Error: ./hdl/unpack.sv:118: Procedural-continuous assignments are not supported by synthesis. (VER-966)
Error: ./hdl/unpack.sv:121: Procedural-continuous assignments are not supported by synthesis. (VER-966)
Error: ./hdl/unpack.sv:122: Procedural-continuous assignments are not supported by synthesis. (VER-966)
Error: ./hdl/unpack.sv:123: Procedural-continuous assignments are not supported by synthesis. (VER-966)
Error: ./hdl/unpack.sv:132: Procedural-continuous assignments are not supported by synthesis. (VER-966)
Error: ./hdl/unpack.sv:133: Procedural-continuous assignments are not supported by synthesis. (VER-966)
Error: Too many errors; can't continue. (VER-40)
*** Presto compilation terminated with 21 errors. ***
Loading db file '/cad/synopsys/SYN/libraries/syn/dw_foundation.sldb'
0
elaborate $my_toplevel -lib WORK
Loading db file '/cad/synopsys/SYN/libraries/syn/gtech.db'
Loading db file '/cad/synopsys/SYN/libraries/syn/standard.sldb'
Loading link library 'gtech'
Running PRESTO HDLC
Presto compilation completed successfully. (wallypipelinedcore)
Elaborated 1 design.
Current design is now 'wallypipelinedcore'.
Information: Building the design 'ifu'. (HDL-193)
Presto compilation completed successfully. (ifu)
Information: Building the design 'ieu'. (HDL-193)
Presto compilation completed successfully. (ieu)
Information: Building the design 'lsu'. (HDL-193)
Presto compilation completed successfully. (lsu)
Information: Building the design 'ahblite'. (HDL-193)
Warning: ./hdl/ahblite.sv:102: DEFAULT branch of CASE statement cannot be reached. (ELAB-311)
Statistics for case statements in always block at line 101 in file
'./hdl/ahblite.sv'
===============================================
| Line | full/ parallel |
===============================================
| 102 | auto/auto |
===============================================
Presto compilation completed successfully. (ahblite)
Information: Building the design 'hazard'. (HDL-193)
Presto compilation completed successfully. (hazard)
Information: Building the design 'busdp' instantiated from design 'ifu' with
the parameters "1,32,1". (HDL-193)
Presto compilation completed successfully. (busdp_WORDSPERLINE1_LINELEN32_LOGWPL1)
Information: Building the design 'mux2' instantiated from design 'ifu' with
the parameters "32". (HDL-193)
Presto compilation completed successfully. (mux2_WIDTH32)
Information: Building the design 'flopenl' instantiated from design 'ifu' with
the parameters "32". (HDL-193)
Inferred memory devices in process
in routine flopenl_WIDTH32 line 40 in file
'./hdl/flopenl.sv'.
===============================================================================
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
| q_reg | Flip-flop | 32 | Y | N | N | N | N | N | N |
===============================================================================
Presto compilation completed successfully. (flopenl_WIDTH32)
Information: Building the design 'flopenrc' instantiated from design 'ifu' with
the parameters "32". (HDL-193)
Inferred memory devices in process
in routine flopenrc_WIDTH32 line 39 in file
'./hdl/flopenrc.sv'.
===============================================================================
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
| q_reg | Flip-flop | 32 | Y | N | N | N | N | N | N |
===============================================================================
Presto compilation completed successfully. (flopenrc_WIDTH32)
Information: Building the design 'decompress'. (HDL-193)
Presto compilation completed successfully. (decompress)
Information: Building the design 'flopenr' instantiated from design 'ifu' with
the parameters "1". (HDL-193)
Inferred memory devices in process
in routine flopenr_WIDTH1 line 39 in file
'./hdl/flopenr.sv'.
===============================================================================
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
| q_reg | Flip-flop | 1 | N | N | N | N | N | N | N |
===============================================================================
Presto compilation completed successfully. (flopenr_WIDTH1)
Information: Building the design 'flopenr' instantiated from design 'ifu' with
the parameters "32". (HDL-193)
Inferred memory devices in process
in routine flopenr_WIDTH32 line 39 in file
'./hdl/flopenr.sv'.
===============================================================================
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
| q_reg | Flip-flop | 32 | Y | N | N | N | N | N | N |
===============================================================================
Presto compilation completed successfully. (flopenr_WIDTH32)
Information: Building the design 'controller'. (HDL-193)
Warning: ./hdl/controller.sv:145: Statement unreachable (Branch condition impossible to meet). (VER-61)
Statistics for case statements in always block at line 118 in file
'./hdl/controller.sv'
===============================================
| Line | full/ parallel |
===============================================
| 119 | auto/auto |
===============================================
Presto compilation completed successfully. (controller)
Information: Building the design 'datapath'. (HDL-193)
Presto compilation completed successfully. (datapath)
Information: Building the design 'forward'. (HDL-193)
Presto compilation completed successfully. (forward)
Information: Building the design 'busdp' instantiated from design 'lsu' with
the parameters "1,32,1,1". (HDL-193)
Presto compilation completed successfully. (busdp_WORDSPERLINE1_LINELEN32_LOGWPL1_LSU1)
Information: Building the design 'subwordread'. (HDL-193)
Statistics for case statements in always block at line 91 in file
'./hdl/subwordread.sv'
===============================================
| Line | full/ parallel |
===============================================
| 92 | auto/auto |
===============================================
Statistics for case statements in always block at line 100 in file
'./hdl/subwordread.sv'
===============================================
| Line | full/ parallel |
===============================================
| 101 | auto/auto |
===============================================
Statistics for case statements in always block at line 107 in file
'./hdl/subwordread.sv'
===============================================
| Line | full/ parallel |
===============================================
| 108 | auto/auto |
===============================================
Presto compilation completed successfully. (subwordread)
Information: Building the design 'flopenl' instantiated from design 'ahblite' with
the parameters "TYPE="enum(24%array(0%1%0%logic)%4%ahblite:_Pr0QaORKb_%cons(4%IDLE%00%cons(4%MEMREAD%01%cons(4%MEMWRITE%10%cons(4%INSTRREAD%11%null)))))%FpfRxH&"". (HDL-193)
Inferred memory devices in process
in routine flopenl_370242 line 40 in file
'./hdl/flopenl.sv'.
===============================================================================
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
| q_reg | Flip-flop | 2 | Y | N | N | N | N | N | N |
===============================================================================
Presto compilation completed successfully. (flopenl_370242)
Information: Building the design 'flop' instantiated from design 'ahblite' with
the parameters "32". (HDL-193)
Inferred memory devices in process
in routine flop_WIDTH32 line 39 in file
'./hdl/flop.sv'.
===============================================================================
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
| q_reg | Flip-flop | 32 | Y | N | N | N | N | N | N |
===============================================================================
Presto compilation completed successfully. (flop_WIDTH32)
Information: Building the design 'flop' instantiated from design 'ahblite' with
the parameters "3". (HDL-193)
Inferred memory devices in process
in routine flop_WIDTH3 line 39 in file
'./hdl/flop.sv'.
===============================================================================
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
| q_reg | Flip-flop | 3 | Y | N | N | N | N | N | N |
===============================================================================
Presto compilation completed successfully. (flop_WIDTH3)
Information: Building the design 'flop' instantiated from design 'ahblite' with
the parameters "4". (HDL-193)
Inferred memory devices in process
in routine flop_WIDTH4 line 39 in file
'./hdl/flop.sv'.
===============================================================================
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
| q_reg | Flip-flop | 4 | Y | N | N | N | N | N | N |
===============================================================================
Presto compilation completed successfully. (flop_WIDTH4)
Information: Building the design 'flop' instantiated from design 'ahblite' with
the parameters "1". (HDL-193)
Inferred memory devices in process
in routine flop_WIDTH1 line 39 in file
'./hdl/flop.sv'.
===============================================================================
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
| q_reg | Flip-flop | 1 | N | N | N | N | N | N | N |
===============================================================================
Presto compilation completed successfully. (flop_WIDTH1)
Information: Building the design 'flopen' instantiated from design 'busdp_WORDSPERLINE1_LINELEN32_LOGWPL1' with
the parameters "32". (HDL-193)
Inferred memory devices in process
in routine flopen_WIDTH32 line 39 in file
'./hdl/flopen.sv'.
===============================================================================
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
| q_reg | Flip-flop | 32 | Y | N | N | N | N | N | N |
===============================================================================
Presto compilation completed successfully. (flopen_WIDTH32)
Information: Building the design 'mux2' instantiated from design 'busdp_WORDSPERLINE1_LINELEN32_LOGWPL1' with
the parameters "34". (HDL-193)
Presto compilation completed successfully. (mux2_WIDTH34)
Information: Building the design 'mux2' instantiated from design 'busdp_WORDSPERLINE1_LINELEN32_LOGWPL1' with
the parameters "3". (HDL-193)
Presto compilation completed successfully. (mux2_WIDTH3)
Information: Building the design 'busfsm' instantiated from design 'busdp_WORDSPERLINE1_LINELEN32_LOGWPL1' with
the parameters "0,1,1'h0". (HDL-193)
Warning: ./hdl/busfsm.sv:98: DEFAULT branch of CASE statement cannot be reached. (ELAB-311)
Statistics for case statements in always block at line 97 in file
'./hdl/busfsm.sv'
===============================================
| Line | full/ parallel |
===============================================
| 98 | auto/auto |
===============================================
Inferred memory devices in process
in routine busfsm_0_1_0 line 93 in file
'./hdl/busfsm.sv'.
===============================================================================
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
| BusCurrState_reg | Flip-flop | 3 | Y | N | N | N | N | N | N |
===============================================================================
Presto compilation completed successfully. (busfsm_0_1_0)
Information: Building the design 'flopenrc' instantiated from design 'controller' with
the parameters "1". (HDL-193)
Inferred memory devices in process
in routine flopenrc_WIDTH1 line 39 in file
'./hdl/flopenrc.sv'.
===============================================================================
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
| q_reg | Flip-flop | 1 | N | N | N | N | N | N | N |
===============================================================================
Presto compilation completed successfully. (flopenrc_WIDTH1)
Information: Building the design 'flopenrc' instantiated from design 'controller' with
the parameters "27". (HDL-193)
Inferred memory devices in process
in routine flopenrc_WIDTH27 line 39 in file
'./hdl/flopenrc.sv'.
===============================================================================
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
| q_reg | Flip-flop | 27 | Y | N | N | N | N | N | N |
===============================================================================
Presto compilation completed successfully. (flopenrc_WIDTH27)
Information: Building the design 'mux4' instantiated from design 'controller' with
the parameters "1". (HDL-193)
Presto compilation completed successfully. (mux4_WIDTH1)
Information: Building the design 'flopenrc' instantiated from design 'controller' with
the parameters "18". (HDL-193)
Inferred memory devices in process
in routine flopenrc_WIDTH18 line 39 in file
'./hdl/flopenrc.sv'.
===============================================================================
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
| q_reg | Flip-flop | 18 | Y | N | N | N | N | N | N |
===============================================================================
Presto compilation completed successfully. (flopenrc_WIDTH18)
Information: Building the design 'flopenrc' instantiated from design 'controller' with
the parameters "4". (HDL-193)
Inferred memory devices in process
in routine flopenrc_WIDTH4 line 39 in file
'./hdl/flopenrc.sv'.
===============================================================================
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
| q_reg | Flip-flop | 4 | Y | N | N | N | N | N | N |
===============================================================================
Presto compilation completed successfully. (flopenrc_WIDTH4)
Information: Building the design 'regfile'. (HDL-193)
Inferred memory devices in process
in routine regfile line 54 in file
'./hdl/regfile.sv'.
===============================================================================
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
| rf_reg | Flip-flop | 480 | Y | N | N | N | N | N | N |
===============================================================================
Statistics for MUX_OPs
======================================================
| block name/line | Inputs | Outputs | # sel inputs |
======================================================
| regfile/58 | 16 | 32 | 4 |
| regfile/59 | 16 | 32 | 4 |
======================================================
Presto compilation completed successfully. (regfile)
Information: Building the design 'extend'. (HDL-193)
Statistics for case statements in always block at line 40 in file
'./hdl/extend.sv'
===============================================
| Line | full/ parallel |
===============================================
| 41 | auto/auto |
===============================================
Presto compilation completed successfully. (extend)
Information: Building the design 'flopenrc' instantiated from design 'datapath' with
the parameters "5". (HDL-193)
Inferred memory devices in process
in routine flopenrc_WIDTH5 line 39 in file
'./hdl/flopenrc.sv'.
===============================================================================
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
| q_reg | Flip-flop | 5 | Y | N | N | N | N | N | N |
===============================================================================
Presto compilation completed successfully. (flopenrc_WIDTH5)
Information: Building the design 'mux3' instantiated from design 'datapath' with
the parameters "32". (HDL-193)
Presto compilation completed successfully. (mux3_WIDTH32)
Information: Building the design 'comparator' instantiated from design 'datapath' with
the parameters "32". (HDL-193)
Presto compilation completed successfully. (comparator_WIDTH32)
Information: Building the design 'alu' instantiated from design 'datapath' with
the parameters "32". (HDL-193)
Statistics for case statements in always block at line 74 in file
'./hdl/alu.sv'
===============================================
| Line | full/ parallel |
===============================================
| 75 | auto/auto |
===============================================
Presto compilation completed successfully. (alu_WIDTH32)
Information: Building the design 'mux5' instantiated from design 'datapath' with
the parameters "32". (HDL-193)
Presto compilation completed successfully. (mux5_WIDTH32)
Information: Building the design 'shifter'. (HDL-193)
Presto compilation completed successfully. (shifter)
1
# Set the current_design
current_design $my_toplevel
Current design is 'wallypipelinedcore'.
{wallypipelinedcore}
link
Linking design 'wallypipelinedcore'
Using the following designs and libraries:
--------------------------------------------------------------------------
dw_foundation.sldb (library) /cad/synopsys/SYN/libraries/syn/dw_foundation.sldb
1
# Reset all constraints
reset_design
1
# Power Dissipation Analysis
######### OPTIONAL !!!!!!!!!!!!!!!!
if { $saifpower == 1 } {
read_saif -input power.saif -instance_name testbench/dut/core -auto_map_names -verbose
}
# Set reset false path
set_false_path -from [get_ports reset]
1
# Set Frequency in [MHz] or period in [ns]
set my_clock_pin clk
clk
set my_uncertainty 0.0
0.0
set my_clk_freq_MHz $::env(FREQ)
500
set my_period [expr 1000.0 / $my_clk_freq_MHz]
2.0
# Create clock object
set find_clock [ find port [list $my_clock_pin] ]
{clk}
if { $find_clock != [list] } {
echo "Found clock!"
set my_clk $my_clock_pin
create_clock -period $my_period $my_clk
set_clock_uncertainty $my_uncertainty [get_clocks $my_clk]
} else {
echo "Did not find clock! Design is probably combinational!"
set my_clk vclk
create_clock -period $my_period -name $my_clk
}
Found clock!
1
# Optimize paths that are close to critical
set_critical_range [expr $my_period*0.05] $current_design
1
# Partitioning - flatten or hierarchically synthesize
if { $maxopt == 1 } {
ungroup -all -flatten -simple_names
}
# Set input pins except clock
set all_in_ex_clk [remove_from_collection [all_inputs] [get_ports $my_clk]]
{reset TimerIntM ExtIntM SwIntM MTIME_CLINT[63] MTIME_CLINT[62] MTIME_CLINT[61] MTIME_CLINT[60] MTIME_CLINT[59] MTIME_CLINT[58] MTIME_CLINT[57] MTIME_CLINT[56] MTIME_CLINT[55] MTIME_CLINT[54] MTIME_CLINT[53] MTIME_CLINT[52] MTIME_CLINT[51] MTIME_CLINT[50] MTIME_CLINT[49] MTIME_CLINT[48] MTIME_CLINT[47] MTIME_CLINT[46] MTIME_CLINT[45] MTIME_CLINT[44] MTIME_CLINT[43] MTIME_CLINT[42] MTIME_CLINT[41] MTIME_CLINT[40] MTIME_CLINT[39] MTIME_CLINT[38] MTIME_CLINT[37] MTIME_CLINT[36] MTIME_CLINT[35] MTIME_CLINT[34] MTIME_CLINT[33] MTIME_CLINT[32] MTIME_CLINT[31] MTIME_CLINT[30] MTIME_CLINT[29] MTIME_CLINT[28] MTIME_CLINT[27] MTIME_CLINT[26] MTIME_CLINT[25] MTIME_CLINT[24] MTIME_CLINT[23] MTIME_CLINT[22] MTIME_CLINT[21] MTIME_CLINT[20] MTIME_CLINT[19] MTIME_CLINT[18] MTIME_CLINT[17] MTIME_CLINT[16] MTIME_CLINT[15] MTIME_CLINT[14] MTIME_CLINT[13] MTIME_CLINT[12] MTIME_CLINT[11] MTIME_CLINT[10] MTIME_CLINT[9] MTIME_CLINT[8] MTIME_CLINT[7] MTIME_CLINT[6] MTIME_CLINT[5] MTIME_CLINT[4] MTIME_CLINT[3] MTIME_CLINT[2] MTIME_CLINT[1] MTIME_CLINT[0] HRDATA[31] HRDATA[30] HRDATA[29] HRDATA[28] HRDATA[27] HRDATA[26] HRDATA[25] HRDATA[24] HRDATA[23] HRDATA[22] HRDATA[21] HRDATA[20] HRDATA[19] HRDATA[18] HRDATA[17] HRDATA[16] HRDATA[15] HRDATA[14] HRDATA[13] HRDATA[12] HRDATA[11] HRDATA[10] HRDATA[9] HRDATA[8] HRDATA[7] HRDATA[6] HRDATA[5] HRDATA[4] HRDATA[3] HRDATA[2] HRDATA[1] HRDATA[0] ...}
# Specifies delays be propagated through the clock network
# This is getting optimized poorly in the current flow, causing a lot of clock skew
# and unrealistic bad timing results.
# set_propagated_clock [get_clocks $my_clk]
# Setting constraints on input ports
if {$tech == "sky130"} {
set_driving_cell -lib_cell sky130_osu_sc_12T_ms__dff_1 -pin Q $all_in_ex_clk
} elseif {$tech == "sky90"} {
set_driving_cell -lib_cell scc9gena_dfxbp_1 -pin Q $all_in_ex_clk
}
# Set input/output delay
set_input_delay 0.1 -max -clock $my_clk $all_in_ex_clk
1
set_output_delay 0.1 -max -clock $my_clk [all_outputs]
1
# Setting load constraint on output ports
if {$tech == "sky130"} {
set_load [expr [load_of sky130_osu_sc_12T_ms_TT_1P8_25C.ccs/sky130_osu_sc_12T_ms__dff_1/D] * 1] [all_outputs]
} elseif {$tech == "sky90"} {
set_load [expr [load_of scc9gena_tt_1.2v_25C/scc9gena_dfxbp_1/D] * 1] [all_outputs]
}
# Set the wire load model
set_wire_load_mode "top"
1
# Attempt Area Recovery - if looking for minimal area
# set_max_area 2000
# Set fanout
set_max_fanout 6 $all_in_ex_clk
1
# Fix hold time violations (DH: this doesn't seem to be working right now)
#set_fix_hold [all_clocks]
# Deal with constants and buffers to isolate ports
set_fix_multiple_port_nets -all -buffer_constants
1
# setting up the group paths to find out the required timings
# group_path -name OUTPUTS -to [all_outputs]
# group_path -name INPUTS -from [all_inputs]
# group_path -name COMBO -from [all_inputs] -to [all_outputs]
# Save Unmapped Design
#set filename [format "%s%s%s%s" $outputDir "/unmapped/" $my_toplevel ".ddc"]
#write_file -format ddc -hierarchy -o $filename
# Compile statements
if { $maxopt == 1 } {
compile_ultra -retime
optimize_registers
} else {
compile_ultra -no_seq_output_inversion -no_boundary_optimization
}
Information: Auto ungrouping of the design is disabled because the '-no_boundary_optimization' is used. (OPT-1316)
Warning: The value of variable 'compile_preserve_subdesign_interfaces' has been changed to true because '-no_boundary_optimization' is used. (OPT-133)
Information: Starting from 2013.12 release, constant propagation is enabled even when boundary optimization is disabled. (OPT-1318)
Information: Performing power optimization. (PWR-850)
Error: No target library found. (OPT-1312)
0
# Eliminate need for assign statements (yuck!)
set verilogout_no_tri true
true
set verilogout_equation false
false
# setting to generate output files
set write_v 1 ;# generates structual netlist
1
set write_sdc 1 ;# generates synopsys design constraint file for p&r
1
set write_ddc 1 ;# compiler file in ddc format
1
set write_sdf 1 ;# sdf file for backannotated timing sim
1
set write_pow 1 ;# genrates estimated power report
1
set write_rep 1 ;# generates estimated area and timing report
1
set write_cst 1 ;# generate report of constraints
1
set write_hier 1 ;# generate hierarchy report
1
# Report Constraint Violators
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_constraint_all_violators.rpt"]
runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_constraint_all_violators.rpt
redirect $filename {report_constraint -all_violators}
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_constraint_all_violators.rpt" (CMD-015)
# Check design
redirect $outputDir/reports/check_design.rpt { check_design }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/check_design.rpt" (CMD-015)
# Report Final Netlist (Hierarchical)
set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".sv"]
runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/mapped/wallypipelinedcore.sv
write_file -f verilog -hierarchy -output $filename
Error: Can't open export file '/home/mmasser-frye/riscv-wally/synthDC/runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/mapped/wallypipelinedcore.sv'. (EXPT-4)
Error: Write command failed. (UID-25)
0
set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".sdc"]
runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/mapped/wallypipelinedcore.sdc
write_sdc $filename
Error: Cannot write the 'runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/mapped/wallypipelinedcore.sdc' script file. (UID-270)
0
set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".ddc"]
runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/mapped/wallypipelinedcore.ddc
write_file -format ddc -hierarchy -o $filename
Error: Unable to open DDC file 'runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/mapped/wallypipelinedcore.ddc' for writing. (DDC-1)
Error: Write command failed. (UID-25)
0
set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".sdf"]
runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/mapped/wallypipelinedcore.sdf
write_sdf $filename
Information: Annotated 'cell' delays are assumed to include load delay. (UID-282)
Error: Cannot write the '/home/mmasser-frye/riscv-wally/synthDC/runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/mapped/wallypipelinedcore.sdf' file. (UID-29)
0
# QoR
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_qor.rep"]
runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_qor.rep
redirect $filename { report_qor }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_qor.rep" (CMD-015)
# Report Timing
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_reportpath.rep"]
runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_reportpath.rep
#redirect $filename { report_path_group }
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_report_clock.rep"]
runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_report_clock.rep
# redirect $filename { report_clock }
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_timing.rep"]
runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_timing.rep
redirect $filename { report_timing -capacitance -transition_time -nets -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_timing.rep" (CMD-015)
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_mindelay.rep"]
runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mindelay.rep
redirect $filename { report_timing -capacitance -transition_time -nets -delay_type min -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mindelay.rep" (CMD-015)
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_per_module_timing.rep"]
runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_per_module_timing.rep
redirect -append $filename { echo "\n\n\n//// Critical paths through ifu ////\n\n\n" }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_per_module_timing.rep" (CMD-015)
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/*} -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_per_module_timing.rep" (CMD-015)
redirect -append $filename { echo "\n\n\n//// Critical paths through ieu ////\n\n\n" }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_per_module_timing.rep" (CMD-015)
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/*} -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_per_module_timing.rep" (CMD-015)
redirect -append $filename { echo "\n\n\n//// Critical paths through lsu ////\n\n\n" }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_per_module_timing.rep" (CMD-015)
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {lsu/*} -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_per_module_timing.rep" (CMD-015)
redirect -append $filename { echo "\n\n\n//// Critical paths through ebu (ahblite) ////\n\n\n" }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_per_module_timing.rep" (CMD-015)
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ebu/*} -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_per_module_timing.rep" (CMD-015)
redirect -append $filename { echo "\n\n\n//// Critical paths through mdu ////\n\n\n" }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_per_module_timing.rep" (CMD-015)
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/*} -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_per_module_timing.rep" (CMD-015)
redirect -append $filename { echo "\n\n\n//// Critical paths through hzu ////\n\n\n" }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_per_module_timing.rep" (CMD-015)
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {hzu/*} -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_per_module_timing.rep" (CMD-015)
redirect -append $filename { echo "\n\n\n//// Critical paths through priv ////\n\n\n" }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_per_module_timing.rep" (CMD-015)
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {priv/*} -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_per_module_timing.rep" (CMD-015)
redirect -append $filename { echo "\n\n\n//// Critical paths through fpu ////\n\n\n" }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_per_module_timing.rep" (CMD-015)
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/*} -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_per_module_timing.rep" (CMD-015)
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_mdu_timing.rep"]
runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep
redirect -append $filename { echo "\n\n\n//// Critical paths through entire mdu ////\n\n\n" }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/*} -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
redirect -append $filename { echo "\n\n\n//// Critical paths through multiply unit ////\n\n\n" }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.mul/*} -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
redirect -append $filename { echo "\n\n\n//// Critical paths through redundant multiplier ////\n\n\n" }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.mul/bigmul/*} -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
redirect -append $filename { echo "\n\n\n//// Critical path through ProdM (mul output) ////\n\n\n" }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.ProdM} -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
redirect -append $filename { echo "\n\n\n//// Critical path through PP0E (mul partial product) ////\n\n\n" }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.mul/PP0E} -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
redirect -append $filename { echo "\n\n\n//// Critical paths through divide unit ////\n\n\n" }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.div/*} -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
redirect -append $filename { echo "\n\n\n//// Critical path through QuotM (div output) ////\n\n\n" }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.QuotM} -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
redirect -append $filename { echo "\n\n\n//// Critical path through RemM (div output) ////\n\n\n" }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.RemM} -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
redirect -append $filename { echo "\n\n\n//// Critical path through div/WNextE ////\n\n\n" }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.div/WNextE} -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
redirect -append $filename { echo "\n\n\n//// Critical path through div/XQNextE ////\n\n\n" }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.div/XQNextE} -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
redirect -append $filename { echo "\n\n\n//// Critical path through div/DAbsBE ////\n\n\n" }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.div/DAbsBE} -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
# set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_fpu_timing.rep"]
# redirect $filename { echo "\n\n\n//// Critical paths through fma ////\n\n\n" }
# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.fma/*} -nworst 1 }
# redirect -append $filename { echo "\n\n\n//// Critical paths through fpdiv ////\n\n\n" }
# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.fdivsqrt/*} -nworst 1 }
# redirect -append $filename { echo "\n\n\n//// Critical paths through faddcvt ////\n\n\n" }
# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.faddcvt/*} -nworst 1 }
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_ifu_timing.rep"]
runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ifu_timing.rep
redirect -append $filename { echo "\n\n\n//// Critical path through PCF ////\n\n\n" }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ifu_timing.rep" (CMD-015)
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/PCF} -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ifu_timing.rep" (CMD-015)
redirect -append $filename { echo "\n\n\n//// Critical path through PCNextF ////\n\n\n" }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ifu_timing.rep" (CMD-015)
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/PCNextF} -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ifu_timing.rep" (CMD-015)
redirect -append $filename { echo "\n\n\n//// Critical path through FinalInstrRawF ////\n\n\n" }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ifu_timing.rep" (CMD-015)
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/FinalInstrRawF} -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ifu_timing.rep" (CMD-015)
redirect -append $filename { echo "\n\n\n//// Critical path through InstrD ////\n\n\n" }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ifu_timing.rep" (CMD-015)
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/decomp/InstrD} -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ifu_timing.rep" (CMD-015)
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_stall_flush_timing.rep"]
runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_stall_flush_timing.rep
redirect -append $filename { echo "\n\n\n//// Critical path through StallD ////\n\n\n" }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_stall_flush_timing.rep" (CMD-015)
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/StallD} -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_stall_flush_timing.rep" (CMD-015)
redirect -append $filename { echo "\n\n\n//// Critical path through StallE ////\n\n\n" }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_stall_flush_timing.rep" (CMD-015)
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/StallE} -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_stall_flush_timing.rep" (CMD-015)
redirect -append $filename { echo "\n\n\n//// Critical path through StallM ////\n\n\n" }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_stall_flush_timing.rep" (CMD-015)
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/StallM} -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_stall_flush_timing.rep" (CMD-015)
redirect -append $filename { echo "\n\n\n//// Critical path through StallW ////\n\n\n" }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_stall_flush_timing.rep" (CMD-015)
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/StallW} -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_stall_flush_timing.rep" (CMD-015)
redirect -append $filename { echo "\n\n\n//// Critical path through FlushD ////\n\n\n" }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_stall_flush_timing.rep" (CMD-015)
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/FlushD} -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_stall_flush_timing.rep" (CMD-015)
redirect -append $filename { echo "\n\n\n//// Critical path through FlushE ////\n\n\n" }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_stall_flush_timing.rep" (CMD-015)
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/FlushE} -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_stall_flush_timing.rep" (CMD-015)
redirect -append $filename { echo "\n\n\n//// Critical path through FlushM ////\n\n\n" }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_stall_flush_timing.rep" (CMD-015)
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/FlushM} -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_stall_flush_timing.rep" (CMD-015)
redirect -append $filename { echo "\n\n\n//// Critical path through FlushW ////\n\n\n" }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_stall_flush_timing.rep" (CMD-015)
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/FlushW} -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_stall_flush_timing.rep" (CMD-015)
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_ieu_timing.rep"]
runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ieu_timing.rep
redirect -append $filename { echo "\n\n\n//// Critical path through datapath/R1D ////\n\n\n" }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ieu_timing.rep" (CMD-015)
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/R1D} -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ieu_timing.rep" (CMD-015)
redirect -append $filename { echo "\n\n\n//// Critical path through datapath/R2D ////\n\n\n" }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ieu_timing.rep" (CMD-015)
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/R2D} -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ieu_timing.rep" (CMD-015)
redirect -append $filename { echo "\n\n\n//// Critical path through datapath/SrcAE ////\n\n\n" }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ieu_timing.rep" (CMD-015)
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/SrcAE} -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ieu_timing.rep" (CMD-015)
redirect -append $filename { echo "\n\n\n//// Critical path through datapath/ALUResultE ////\n\n\n" }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ieu_timing.rep" (CMD-015)
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/ALUResultE} -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ieu_timing.rep" (CMD-015)
redirect -append $filename { echo "\n\n\n//// Critical path through datapath/WriteDataW ////\n\n\n" }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ieu_timing.rep" (CMD-015)
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/WriteDataW} -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ieu_timing.rep" (CMD-015)
redirect -append $filename { echo "\n\n\n//// Critical path through datapath/ReadDataM ////\n\n\n" }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ieu_timing.rep" (CMD-015)
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/ReadDataM} -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ieu_timing.rep" (CMD-015)
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_fpu_timing.rep"]
runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_fpu_timing.rep
redirect -append $filename { echo "\n\n\n//// Critical paths through fma ////\n\n\n" }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_fpu_timing.rep" (CMD-015)
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.fma/*} -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_fpu_timing.rep" (CMD-015)
redirect -append $filename { echo "\n\n\n//// Critical paths through fpdiv ////\n\n\n" }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_fpu_timing.rep" (CMD-015)
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.fdivsqrt/*} -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_fpu_timing.rep" (CMD-015)
redirect -append $filename { echo "\n\n\n//// Critical paths through faddcvt ////\n\n\n" }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_fpu_timing.rep" (CMD-015)
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.faddcvt/*} -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_fpu_timing.rep" (CMD-015)
redirect -append $filename { echo "\n\n\n//// Critical paths through FMAResM ////\n\n\n" }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_fpu_timing.rep" (CMD-015)
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.FMAResM} -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_fpu_timing.rep" (CMD-015)
redirect -append $filename { echo "\n\n\n//// Critical paths through FDivResM ////\n\n\n" }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_fpu_timing.rep" (CMD-015)
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.FDivResM} -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_fpu_timing.rep" (CMD-015)
redirect -append $filename { echo "\n\n\n//// Critical paths through FResE ////\n\n\n" }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_fpu_timing.rep" (CMD-015)
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.FResE} -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_fpu_timing.rep" (CMD-015)
redirect -append $filename { echo "\n\n\n//// Critical paths through fma/SumE ////\n\n\n" }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_fpu_timing.rep" (CMD-015)
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.fma/SumE} -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_fpu_timing.rep" (CMD-015)
redirect -append $filename { echo "\n\n\n//// Critical paths through fma/ProdExpE ////\n\n\n" }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_fpu_timing.rep" (CMD-015)
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.fma/ProdExpE} -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_fpu_timing.rep" (CMD-015)
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_mmu_timing.rep"]
runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mmu_timing.rep
redirect -append $filename { echo "\n\n\n//// Critical paths through immu/physicaladdress ////\n\n\n" }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mmu_timing.rep" (CMD-015)
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/immu/PhysicalAddress} -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mmu_timing.rep" (CMD-015)
redirect -append $filename { echo "\n\n\n//// Critical paths through dmmu/physicaladdress ////\n\n\n" }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mmu_timing.rep" (CMD-015)
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {lsu/dmmu/PhysicalAddress} -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mmu_timing.rep" (CMD-015)
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_priv_timing.rep"]
runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_priv_timing.rep
redirect -append $filename { echo "\n\n\n//// Critical paths through priv/TrapM ////\n\n\n" }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_priv_timing.rep" (CMD-015)
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {priv/TrapM} -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_priv_timing.rep" (CMD-015)
redirect -append $filename { echo "\n\n\n//// Critical paths through priv/CSRReadValM ////\n\n\n" }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_priv_timing.rep" (CMD-015)
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {priv/csr/CSRReadValM} -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_priv_timing.rep" (CMD-015)
redirect -append $filename { echo "\n\n\n//// Critical paths through priv/CSRReadValW ////\n\n\n" }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_priv_timing.rep" (CMD-015)
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {priv/CSRReadValW} -nworst 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_priv_timing.rep" (CMD-015)
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_min_timing.rep"]
runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_min_timing.rep
redirect $filename { report_timing -delay min }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_min_timing.rep" (CMD-015)
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_area.rep"]
runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_area.rep
redirect $filename { report_area -hierarchy -nosplit -physical -designware}
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_area.rep" (CMD-015)
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_cell.rep"]
runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_cell.rep
# redirect $filename { report_cell [get_cells -hier *] }
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_power.rep"]
runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_power.rep
redirect $filename { report_power -hierarchy -levels 1 }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_power.rep" (CMD-015)
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_constraint.rep"]
runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_constraint.rep
redirect $filename { report_constraint }
Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_constraint.rep" (CMD-015)
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_hier.rep"]
runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_hier.rep
# redirect $filename { report_hierarchy }
quit
Memory usage for this session 101 Mbytes.
Memory usage for this session including child processes 101 Mbytes.
CPU usage for this session 7 seconds ( 0.00 hours ).
Elapsed time for this session 9 seconds ( 0.00 hours ).
Thank you...

198
synthDC/ppaAnalyze.py
View File

@ -2,6 +2,7 @@
# Madeleine Masser-Frye mmasserfrye@hmc.edu 5/22
from operator import index
import scipy.optimize as opt
import subprocess
import csv
import re
@ -11,14 +12,14 @@ import matplotlib.lines as lines
import matplotlib.axes as axes
import numpy as np
from collections import namedtuple
import sklearn.metrics as skm
def synthsfromcsv(filename):
Synth = namedtuple("Synth", "module tech width freq delay area lpower denergy")
with open(filename, newline='') as csvfile:
csvreader = csv.reader(csvfile)
global allSynths
allSynths = list(csvreader)
allSynths = list(csvreader)[1:]
for i in range(len(allSynths)):
for j in range(len(allSynths[0])):
try: allSynths[i][j] = int(allSynths[i][j])
@ -26,6 +27,7 @@ def synthsfromcsv(filename):
try: allSynths[i][j] = float(allSynths[i][j])
except: pass
allSynths[i] = Synth(*allSynths[i])
return allSynths
def synthsintocsv():
''' writes a CSV with one line for every available synthesis
@ -37,28 +39,32 @@ def synthsintocsv():
allSynths = output.decode("utf-8").split('\n')[:-1]
specReg = re.compile('[a-zA-Z0-9]+')
metricReg = re.compile('\d+\.\d+[e]?[-+]?\d*')
metricReg = re.compile('-?\d+\.\d+[e]?[-+]?\d*')
file = open("ppaData.csv", "w")
writer = csv.writer(file)
writer.writerow(['Module', 'Tech', 'Width', 'Target Freq', 'Delay', 'Area', 'L Power (nW)', 'D energy (mJ)'])
writer.writerow(['Module', 'Tech', 'Width', 'Target Freq', 'Delay', 'Area', 'L Power (nW)', 'D energy (fJ)'])
for oneSynth in allSynths:
module, width, risc, tech, freq = specReg.findall(oneSynth)[2:7]
tech = tech[:-2]
metrics = []
for phrase in [['Path Length', 'qor'], ['Design Area', 'qor'], ['100', 'power']]:
for phrase in [['Path Slack', 'qor'], ['Clk Period', 'qor'], ['Design Area', 'qor'], ['100', 'power']]:
bashCommand = 'grep "{}" '+ oneSynth[2:]+'/reports/*{}*'
bashCommand = bashCommand.format(*phrase)
try: output = subprocess.check_output(['bash','-c', bashCommand])
except: print("At least one synth run doesn't have reports, try cleanup() first")
except:
print(module + width + tech + freq + " doesn't have reports")
print("Consider running cleanup() first")
nums = metricReg.findall(str(output))
nums = [float(m) for m in nums]
metrics += nums
delay = metrics[0]
area = metrics[1]
lpower = metrics[4]
denergy = (metrics[2] + metrics[3])*delay # (switching + internal powers)*delay
delay = metrics[1] - metrics[0]
area = metrics[2]
lpower = metrics[5]
denergy = (metrics[3] + metrics[4])*delay*1000 # (switching + internal powers)*delay, more practical units for regression coefs
if ('flop' in module): area = area/2 # since two flops in each module
writer.writerow([module, tech, width, freq, delay, area, lpower, denergy])
file.close()
@ -119,13 +125,31 @@ def getVals(tech, module, var, freq=None):
try: metric += [met]
except: pass
if ('flop' in module) & (var == 'area'):
metric = [m/2 for m in metric] # since two flops in each module
if (var == 'denergy'):
metric = [m*1000 for m in metric] # more practical units for regression coefs
return metric
def csvOfBest():
global techSpecs, widths, modules, allSynths
bestSynths = []
for tech in [x.tech for x in techSpecs]:
for mod in modules:
for w in widths:
m = 100000 # large number to start
best = None
for oneSynth in allSynths:
if (oneSynth.width == w) & (oneSynth.tech == tech) & (oneSynth.module == mod):
if (oneSynth.delay < m) & (1000/oneSynth.delay > oneSynth.freq):
m = oneSynth.delay
best = oneSynth
if (best != None) & (best not in bestSynths):
bestSynths += [best]
file = open("bestSynths.csv", "w")
writer = csv.writer(file)
writer.writerow(['Module', 'Tech', 'Width', 'Target Freq', 'Delay', 'Area', 'L Power (nW)', 'D energy (fJ)'])
for synth in bestSynths:
writer.writerow(list(synth))
file.close()
def genLegend(fits, coefs, r2, spec):
''' generates a list of two legend elements
labels line with fit equation and dots with tech and r squared of the fit
@ -135,24 +159,18 @@ def genLegend(fits, coefs, r2, spec):
eq = ''
ind = 0
if 'c' in fits:
eq += coefsr[ind]
ind += 1
if 'l' in fits:
eq += " + " + coefsr[ind] + "*N"
ind += 1
if 's' in fits:
eq += " + " + coefsr[ind] + "*N^2"
ind += 1
if 'g' in fits:
eq += " + " + coefsr[ind] + "*log2(N)"
ind += 1
if 'n' in fits:
eq += " + " + coefsr[ind] + "*Nlog2(N)"
ind += 1
legend_elements = [lines.Line2D([0], [0], color=spec.color, label=eq),
lines.Line2D([0], [0], color=spec.color, ls='', marker=spec.shape, label=spec.tech +' $R^2$='+ str(round(r2, 4)))]
eqDict = {'c': '', 'l': 'N', 's': '$N^2$', 'g': '$log_2$(N)', 'n': 'N$log_2$(N)'}
for k in eqDict.keys():
if k in fits:
if str(coefsr[ind]) != '0.0': eq += " + " + coefsr[ind] + eqDict[k]
ind += 1
eq = eq[3:]
legend_elements = [lines.Line2D([0], [0], color=spec.color, label=eq)]
if spec.shape: legend_elements += [lines.Line2D([0], [0], color=spec.color, ls='', marker=spec.shape, label=spec.tech +' $R^2$='+ str(round(r2, 4)))]
return legend_elements
def oneMetricPlot(module, var, freq=None, ax=None, fits='clsgn', norm=True, color=None):
@ -175,6 +193,9 @@ def oneMetricPlot(module, var, freq=None, ax=None, fits='clsgn', norm=True, colo
global norms
allWidths = []
allMetrics = []
for spec in techSpecs:
metric = getVals(spec.tech, module, var, freq=freq)
@ -184,21 +205,28 @@ def oneMetricPlot(module, var, freq=None, ax=None, fits='clsgn', norm=True, colo
metric = [m/norm for m in metric] # comment out to not normalize
if len(metric) == 5:
allWidths += widths
allMetrics += metric
xp, pred, leg = regress(widths, metric, spec, fits)
fullLeg += leg
c = color if color else spec.color
ax.scatter(widths, metric, color=c, marker=spec.shape)
ax.plot(xp, pred, color=c)
combined = TechSpec('combined', 'red', 0, 0, 0, 0, 0)
xp, pred, leg = regress(allWidths, allMetrics, combined, fits)
fullLeg += leg
ax.plot(xp, pred, color='red')
ax.legend(handles=fullLeg)
ax.set_xticks(widths)
ax.set_xlabel("Width (bits)")
if norm:
ylabeldic = {"lpower": "Normalized Leakage Power", "denergy": "Normalized Dynamic Energy", "area": "INVx1 Areas", "delay": "FO4 Delays"}
ylabeldic = {"lpower": "Leakage Power (add32)", "denergy": "Energy/Op (add32)", "area": "Area (add32)", "delay": "Delay (FO4)"}
else:
ylabeldic = {"lpower": "Leakage Power (nW)", "denergy": "Dynamic Energy (nJ)", "area": "Area (sq microns)", "delay": "Delay (ns)"}
ylabeldic = {"lpower": "Leakage Power (nW)", "denergy": "Dynamic Energy (fJ)", "area": "Area (sq microns)", "delay": "Delay (ns)"}
ax.set_ylabel(ylabeldic[var])
@ -206,7 +234,7 @@ def oneMetricPlot(module, var, freq=None, ax=None, fits='clsgn', norm=True, colo
titleStr = " (target " + str(freq)+ "MHz)" if freq != None else " (best achievable delay)"
ax.set_title(module + titleStr)
plt.savefig('./plots/PPA/'+ module + '_' + var + '.png')
# plt.show()
plt.show()
def regress(widths, var, spec, fits='clsgn'):
''' fits a curve to the given points
@ -223,20 +251,22 @@ def regress(widths, var, spec, fits='clsgn'):
mat += [row]
y = np.array(var, dtype=np.float)
coefsResid = np.linalg.lstsq(mat, y, rcond=None)
coefsResid = opt.nnls(mat, y)
coefs = coefsResid[0]
try:
resid = coefsResid[1][0]
r2 = 1 - resid / (y.size * y.var())
except:
r2 = 0
xp = np.linspace(8, 140, 200)
xp = np.linspace(4, 140, 200)
pred = []
yp = []
for x in xp:
n = [func(x) for func in funcArr]
pred += [sum(np.multiply(coefs, n))]
for w in widths:
n = [func(w) for func in funcArr]
yp += [sum(np.multiply(coefs, n))]
r2 = skm.r2_score(y, yp)
leg = genLegend(fits, coefs, r2, spec)
return xp, pred, leg
@ -287,14 +317,17 @@ def noOutliers(freqs, delays, areas):
f=[]
d=[]
a=[]
ind = delays.index(min(delays))
med = freqs[ind]
for i in range(len(freqs)):
norm = freqs[i]/med
if (norm > 0.25) & (norm<1.75):
f += [freqs[i]]
d += [delays[i]]
a += [areas[i]]
try:
ind = delays.index(min(delays))
med = freqs[ind]
for i in range(len(freqs)):
norm = freqs[i]/med
# if (norm > 0.25) & (norm<1.75):
if freqs[i] < 8000:
f += [freqs[i]]
d += [delays[i]]
a += [areas[i]]
except: pass
return f, d, a
@ -303,14 +336,18 @@ def freqPlot(tech, mod, width):
'''
global allSynths
freqsL, delaysL, areasL = ([[], []] for i in range(3))
count = 0
for oneSynth in allSynths:
if (mod == oneSynth.module) & (width == oneSynth.width) & (tech == oneSynth.tech):
count += 1
ind = (1000/oneSynth.delay < oneSynth.freq) # when delay is within target clock period
freqsL[ind] += [oneSynth.freq]
delaysL[ind] += [oneSynth.delay]
areasL[ind] += [oneSynth.area]
f, (ax1, ax2, ax3, ax4) = plt.subplots(4, 1, sharex=True)
for ax in (ax1, ax2, ax3, ax4):
ax.ticklabel_format(useOffset=False, style='plain')
for ind in [0,1]:
areas = areasL[ind]
@ -318,7 +355,7 @@ def freqPlot(tech, mod, width):
freqs = freqsL[ind]
if ('flop' in mod): areas = [m/2 for m in areas] # since two flops in each module
freqs, delays, areas = noOutliers(freqs, delays, areas) # comment out to see all syntheses
# freqs, delays, areas = noOutliers(freqs, delays, areas) # comment out to see all syntheses
c = 'blue' if ind else 'green'
adprod = adprodpow(areas, delays, 1)
@ -339,7 +376,7 @@ def freqPlot(tech, mod, width):
ax3.set_ylabel('Area * Delay')
ax4.set_ylabel('Area * $Delay^2$')
ax1.set_title(mod + '_' + str(width))
plt.savefig('./plots/freqBuckshot/' + mod + '/' + str(width) + '.png')
plt.savefig('./plots/freqBuckshot/' + tech + '/' + mod + '/' + str(width) + '.png')
# plt.show()
def squareAreaDelay(tech, mod, width):
@ -433,6 +470,7 @@ def plotPPA(mod, freq=None, norm=True):
if no freq specified, uses the synthesis with best achievable delay for each width
overlays data from both techs
'''
plt.rcParams["figure.figsize"] = (12,8)
fig, axs = plt.subplots(2, 2)
global fitDict
modFit = fitDict[mod]
@ -447,44 +485,56 @@ def plotPPA(mod, freq=None, norm=True):
plt.savefig(saveStr)
# plt.show()
def plotBestAreas():
global fitDict
def plotBestAreas(mod):
fig, axs = plt.subplots(1, 1)
mods = ['priorityencoder', 'add', 'csa', 'shiftleft', 'comparator', 'flop']
colors = ['red', 'orange', 'yellow', 'green', 'blue', 'purple']
legend_elements = []
for i in range(len(mods)):
oneMetricPlot(mods[i], 'area', ax=axs, freq=10, norm=False, color=colors[i])
legend_elements += [lines.Line2D([0], [0], color=colors[i], ls='', marker='o', label=mods[i])]
plt.suptitle('Optimized Areas (target freq 10MHz)')
plt.legend(handles=legend_elements)
plt.savefig('./plots/bestareas.png')
### all areas on one
# mods = ['priorityencoder', 'add', 'csa', 'shiftleft', 'comparator', 'flop']
# colors = ['red', 'orange', 'yellow', 'green', 'blue', 'purple']
# legend_elements = []
# for i in range(len(mods)):
# oneMetricPlot(mods[i], 'area', ax=axs, freq=10, norm=False, color=colors[i])
# legend_elements += [lines.Line2D([0], [0], color=colors[i], ls='', marker='o', label=mods[i])]
# plt.suptitle('Optimized Areas (target freq 10MHz)')
# plt.legend(handles=legend_elements)
# plt.savefig('./plots/bestareas.png')
# plt.show()
oneMetricPlot(mod, 'area', freq=10)
plt.title(mod + ' Optimized Areas (target freq 10MHz)')
plt.savefig('./plots/bestAreas/' + mod + '.png')
if __name__ == '__main__':
# set up stuff, global variables
widths = [8, 16, 32, 64, 128]
# fitDict in progress
fitDict = {'add': ['gl', 'lg'], 'mult': ['clg', 's'], 'comparator': ['clsgn', 'clsgn'], 'csa': ['clsgn', 'clsgn'], 'shiftleft': ['clsgn', 'clsgn'], 'flop': ['cl', 'cl'], 'priorityencoder': ['clsgn', 'clsgn']}
fitDict = {'add': ['cg', 'l', 'l'], 'mult': ['cg', 'sl', 'ls'], 'comparator': ['cg', 'l', 'l'], 'csa': ['c', 'l', 'l'], 'shiftleft': ['cg', 'n', 'ln'], 'flop': ['c', 'l', 'l'], 'priorityencoder': ['cg', 'l', 'l']}
fitDict.update(dict.fromkeys(['mux2', 'mux4', 'mux8'], ['cg', 'l', 'l'])) #data
TechSpec = namedtuple("TechSpec", "tech color shape delay area lpower denergy")
techSpecs = [['sky90', 'green', 'o', 43.2e-3, 1.96, 1.98, 1], ['gf32', 'purple', 's', 15e-3, .351, .3116, 1], ['tsmc28', 'blue', '^', 12.2e-3, .252, 1.09, 1]]
techSpecs = [['sky90', 'green', 'o', 43.2e-3, 1330.84, 582.81, 520.66], ['tsmc28', 'blue', '^', 12.2e-3, 209.29, 1060, 81.43]]
invz1arealeakage = [['sky90', 1.96, 1.98], ['gf32', .351, .3116], ['tsmc28', .252, 1.09]] #['gf32', 'purple', 's', 15e-3]
techSpecs = [TechSpec(*t) for t in techSpecs]
modules = ['priorityencoder', 'add', 'csa', 'shiftleft', 'comparator', 'flop', 'mux2', 'mux4', 'mux8', 'mult']
# cleanup()
# synthsintocsv() # slow, run only when new synth runs to add to csv
synthsfromcsv('ppaData.csv') # your csv here!
allSynths = synthsfromcsv('ppaData.csv') # your csv here!
# ### examples
# # ### examples
# squareAreaDelay('sky90', 'add', 32)
# plotBestAreas('add')
# oneMetricPlot('add', 'delay')
plotBestAreas()
# freqPlot('sky90', 'mux4', 16)
mods = ['priorityencoder', 'add', 'csa', 'shiftleft', 'comparator', 'flop', 'mult']
for mod in mods:
for mod in modules:
plotPPA(mod, norm=False)
plotPPA(mod)
for w in [8, 16, 32, 64, 128]:
freqPlot('sky90', mod, w)
# for w in [8, 16, 32, 64, 128]:
# freqPlot('sky90', mod, w)
# freqPlot('tsmc28', mod, w)
plt.close('all')
# csvOfBest()

3141
synthDC/ppaData.csv
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1439
synthDC/ppaDataOld.csv Normal file
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99
synthDC/ppaSynth.py
View File

@ -1,9 +1,12 @@
#!/usr/bin/python3
# Madeleine Masser-Frye mmasserfrye@hmc.edu 5/22
from collections import namedtuple
import csv
import subprocess
import re
from multiprocessing import Pool
from multiprocessing import Pool, cpu_count
from ppaAnalyze import synthsfromcsv
def runCommand(module, width, tech, freq):
@ -17,59 +20,59 @@ def deleteRedundant(LoT):
bashCommand = synthStr.format(*synth)
outputCPL = subprocess.check_output(['bash','-c', bashCommand])
def getData():
bashCommand = "grep 'Critical Path Length' runs/ppa_*/reports/*qor*"
outputCPL = subprocess.check_output(['bash','-c', bashCommand])
linesCPL = outputCPL.decode("utf-8").split('\n')[:-1]
def getData(filename):
Synth = namedtuple("Synth", "module tech width freq delay area lpower denergy")
with open(filename, newline='') as csvfile:
csvreader = csv.reader(csvfile)
global allSynths
allSynths = list(csvreader)
for i in range(len(allSynths)):
for j in range(len(allSynths[0])):
try: allSynths[i][j] = int(allSynths[i][j])
except:
try: allSynths[i][j] = float(allSynths[i][j])
except: pass
allSynths[i] = Synth(*allSynths[i])
cpl = re.compile('\d{1}\.\d{6}')
f = re.compile('_\d*_MHz')
wm = re.compile('ppa_\w*_\d*_qor')
allSynths = []
# arr = [-5, -3, -1, 1, 3, 5]
arr2 = [-8, -6, -4, -2, 0, 2, 4, 6, 8]
for i in range(len(linesCPL)):
line = linesCPL[i]
mwm = wm.findall(line)[0][4:-4].split('_')
freq = int(f.findall(line)[0][1:-4])
delay = float(cpl.findall(line)[0])
mod = mwm[0]
width = int(mwm[1])
oneSynth = [mod, width, freq, delay]
allSynths += [oneSynth]
return allSynths
allSynths = getData()
arr = [-40, -20, -8, -6, -4, -2, 0, 2, 4, 6, 8, 12, 20, 40]
widths = [16, 8, 32, 64, 128]
modules = ['add']
tech = 'tsmc28'
widths = [32]
modules = ['mux2']#, 'comparator'] #, 'mux2', 'mux4', 'mux8', 'shiftleft', 'flop', 'comparator'] # need mult, 'shiftleft', add
techs = ['sky90']
LoT = []
# # # initial sweep to get estimate of min delay
# freqs = [25000, 35000]
# for module in modules:
# for width in widths:
# for freq in freqs:
# LoT += [[module, width, tech, freq]]
allSynths = synthsfromcsv('ppaData.csv')
for w in widths:
for module in modules:
for tech in techs:
m = 100000 # large number to start
for oneSynth in allSynths:
if (oneSynth.width == w) & (oneSynth.tech == tech) & (oneSynth.module == module):
if (oneSynth.delay < m):
m = oneSynth.delay
synth = oneSynth
# f = 1000/synth.delay
f = 4950
for freq in [round(f+f*x/100) for x in arr2]:
LoT += [[synth.module, str(synth.width), synth.tech, str(freq)]]
# # thorough sweep based on estimate of min delay
for m in modules:
for w in widths:
delays = []
for oneSynth in allSynths:
if (oneSynth[0] == m) & (oneSynth[1] == w):
delays += [oneSynth[3]]
try: f = 1000/min(delays)
except: print(m)
for freq in [str(round(f+f*x/100)) for x in arr]:
LoT += [[m, w, tech, freq]]
bashCommand = "find . -path '*runs/ppa*rv32e*' -prune"
output = subprocess.check_output(['bash','-c', bashCommand])
specReg = re.compile('[a-zA-Z0-9]+')
allSynths = output.decode("utf-8").split('\n')[:-1]
allSynths = [specReg.findall(oneSynth)[2:7] for oneSynth in allSynths]
allSynths = [oneSynth[0:2] + [oneSynth[3][:-2]] + [oneSynth[4]] for oneSynth in allSynths]
deleteRedundant(LoT)
pool = Pool()
pool.starmap(runCommand, LoT)
synthsToRun = []
for synth in LoT:
if synth not in allSynths:
synthsToRun += [synth]
pool = Pool(processes=25)
pool.starmap(runCommand, synthsToRun)
pool.close()

38
synthDC/scripts/synth.tcl
View File

@ -30,7 +30,7 @@ eval file copy -force [glob ${hdl_src}/*/*.sv] {hdl/}
eval file copy -force [glob ${hdl_src}/*/flop/*.sv] {hdl/}
# Only for FMA class project; comment out when done
eval file copy -force [glob ${hdl_src}/fma/fma16.v] {hdl/}
# eval file copy -force [glob ${hdl_src}/fma/fma16.v] {hdl/}
# Enables name mapping
if { $saifpower == 1 } {
@ -71,7 +71,9 @@ if { $saifpower == 1 } {
}
# Set reset false path
set_false_path -from [get_ports reset]
if {$drive != "INV"} {
set_false_path -from [get_ports reset]
}
# Set Frequency in [MHz] or period in [ns]
set my_clock_pin clk
@ -112,13 +114,13 @@ set all_in_ex_clk [remove_from_collection [all_inputs] [get_ports $my_clk]]
if {$tech == "sky130"} {
set_driving_cell -lib_cell sky130_osu_sc_12T_ms__dff_1 -pin Q $all_in_ex_clk
} elseif {$tech == "sky90"} {
if ($drive == "INV") {
if {$drive == "INV"} {
set_driving_cell -lib_cell scc9gena_inv_1 -pin Y $all_in_ex_clk
} else {
set_driving_cell -lib_cell scc9gena_dfxbp_1 -pin Q $all_in_ex_clk
}
} elseif {$tech == "tsmc28"} {
if ($drive == "INV") {
if {$drive == "INV"} {
set_driving_cell -lib_cell INVD1BWP30P140 -pin ZN $all_in_ex_clk
}
}
@ -131,13 +133,13 @@ set_output_delay 0.0 -max -clock $my_clk [all_outputs]
if {$tech == "sky130"} {
set_load [expr [load_of sky130_osu_sc_12T_ms_TT_1P8_25C.ccs/sky130_osu_sc_12T_ms__dff_1/D] * 1] [all_outputs]
} elseif {$tech == "sky90"} {
if ($drive == "INV") {
if {$drive == "INV"} {
set_load [expr [load_of scc9gena_tt_1.2v_25C/scc9gena_inv_4/A] * 1] [all_outputs]
} else {
set_load [expr [load_of scc9gena_tt_1.2v_25C/scc9gena_dfxbp_1/D] * 1] [all_outputs]
}
} elseif {$tech == "tsmc28"} {
if ($drive == "INV") {
if {$drive == "INV"} {
set_load [expr [load_of tcbn28hpcplusbwp30p140tt0p9v25c/INVD4BWP30P140/I] * 1] [all_outputs]
}
}
@ -323,21 +325,15 @@ redirect -append $filename { report_timing -capacitance -transition_time -nets -
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_fpu_timing.rep"]
redirect -append $filename { echo "\n\n\n//// Critical paths through fma ////\n\n\n" }
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.fma/*} -nworst 1 }
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fma/*} -nworst 1 }
redirect -append $filename { echo "\n\n\n//// Critical paths through fma1 ////\n\n\n" }
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fma/fma1/*} -nworst 1 }
redirect -append $filename { echo "\n\n\n//// Critical paths through fma2 ////\n\n\n" }
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fma/fma2/*} -nworst 1 }
redirect -append $filename { echo "\n\n\n//// Critical paths through fpdiv ////\n\n\n" }
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.fdivsqrt/*} -nworst 1 }
redirect -append $filename { echo "\n\n\n//// Critical paths through faddcvt ////\n\n\n" }
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.faddcvt/*} -nworst 1 }
redirect -append $filename { echo "\n\n\n//// Critical paths through FMAResM ////\n\n\n" }
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.FMAResM} -nworst 1 }
redirect -append $filename { echo "\n\n\n//// Critical paths through FDivResM ////\n\n\n" }
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.FDivResM} -nworst 1 }
redirect -append $filename { echo "\n\n\n//// Critical paths through FResE ////\n\n\n" }
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.FResE} -nworst 1 }
redirect -append $filename { echo "\n\n\n//// Critical paths through fma/SumE ////\n\n\n" }
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.fma/SumE} -nworst 1 }
redirect -append $filename { echo "\n\n\n//// Critical paths through fma/ProdExpE ////\n\n\n" }
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.fma/ProdExpE} -nworst 1 }
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fdivsqrt/*} -nworst 1 }
redirect -append $filename { echo "\n\n\n//// Critical paths through fcvt ////\n\n\n" }
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fcvt/*} -nworst 1 }
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_mmu_timing.rep"]
redirect -append $filename { echo "\n\n\n//// Critical paths through immu/physicaladdress ////\n\n\n" }
@ -371,4 +367,4 @@ redirect $filename { report_constraint }
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_hier.rep"]
# redirect $filename { report_hierarchy }
#quit
quit

484
tests/fp/append_ctrlSig.sh
View File

@ -1,484 +0,0 @@
#!/bin/sh
BUILD="../../addins/TestFloat-3e/build/Linux-x86_64-GCC"
OUTPUT="./vectors"
echo "Editing ui32_to_f16 test vectors"
sed -ie 's/$/_0_2_2/' $OUTPUT/ui32_to_f16_rne.tv
sed -ie 's/$/_1_2_2/' $OUTPUT/ui32_to_f16_rz.tv
sed -ie 's/$/_3_2_2/' $OUTPUT/ui32_to_f16_ru.tv
sed -ie 's/$/_2_2_2/' $OUTPUT/ui32_to_f16_rd.tv
sed -ie 's/$/_4_2_2/' $OUTPUT/ui32_to_f16_rnm.tv
echo "Editing ui32_to_f32 test vectors"
sed -ie 's/$/_0_0_2/' $OUTPUT/ui32_to_f32_rne.tv
sed -ie 's/$/_1_0_2/' $OUTPUT/ui32_to_f32_rz.tv
sed -ie 's/$/_3_0_2/' $OUTPUT/ui32_to_f32_ru.tv
sed -ie 's/$/_2_0_2/' $OUTPUT/ui32_to_f32_rd.tv
sed -ie 's/$/_4_0_2/' $OUTPUT/ui32_to_f32_rnm.tv
echo "Editing ui32_to_f64 test vectors"
sed -ie 's/$/_0_1_2/' $OUTPUT/ui32_to_f64_rne.tv
sed -ie 's/$/_1_1_2/' $OUTPUT/ui32_to_f64_rz.tv
sed -ie 's/$/_3_1_2/' $OUTPUT/ui32_to_f64_ru.tv
sed -ie 's/$/_2_1_2/' $OUTPUT/ui32_to_f64_rd.tv
sed -ie 's/$/_4_1_2/' $OUTPUT/ui32_to_f64_rnm.tv
echo "Editing ui32_to_f128 test vectors"
sed -ie 's/$/_0_3_2/' $OUTPUT/ui32_to_f128_rne.tv
sed -ie 's/$/_1_3_2/' $OUTPUT/ui32_to_f128_rz.tv
sed -ie 's/$/_3_3_2/' $OUTPUT/ui32_to_f128_ru.tv
sed -ie 's/$/_2_3_2/' $OUTPUT/ui32_to_f128_rd.tv
sed -ie 's/$/_4_3_2/' $OUTPUT/ui32_to_f128_rnm.tv
echo "Editing ui64_to_f16 test vectors"
sed -ie 's/$/_0_2_6/' $OUTPUT/ui64_to_f16_rne.tv
sed -ie 's/$/_1_2_6/' $OUTPUT/ui64_to_f16_rz.tv
sed -ie 's/$/_3_2_6/' $OUTPUT/ui64_to_f16_ru.tv
sed -ie 's/$/_2_2_6/' $OUTPUT/ui64_to_f16_rd.tv
sed -ie 's/$/_4_2_6/' $OUTPUT/ui64_to_f16_rnm.tv
echo "Editing ui64_to_f32 test vectors"
sed -ie 's/$/_0_0_6/' $OUTPUT/ui64_to_f32_rne.tv
sed -ie 's/$/_1_0_6/' $OUTPUT/ui64_to_f32_rz.tv
sed -ie 's/$/_3_0_6/' $OUTPUT/ui64_to_f32_ru.tv
sed -ie 's/$/_2_0_6/' $OUTPUT/ui64_to_f32_rd.tv
sed -ie 's/$/_4_0_6/' $OUTPUT/ui64_to_f32_rnm.tv
echo "Editing ui64_to_f64 test vectors"
sed -ie 's/$/_0_1_6/' $OUTPUT/ui64_to_f64_rne.tv
sed -ie 's/$/_1_1_6/' $OUTPUT/ui64_to_f64_rz.tv
sed -ie 's/$/_3_1_6/' $OUTPUT/ui64_to_f64_ru.tv
sed -ie 's/$/_2_1_6/' $OUTPUT/ui64_to_f64_rd.tv
sed -ie 's/$/_4_1_6/' $OUTPUT/ui64_to_f64_rnm.tv
echo "Editing ui64_to_f128 test vectors"
sed -ie 's/$/_0_3_6/' $OUTPUT/ui64_to_f128_rne.tv
sed -ie 's/$/_1_3_6/' $OUTPUT/ui64_to_f128_rz.tv
sed -ie 's/$/_3_3_6/' $OUTPUT/ui64_to_f128_ru.tv
sed -ie 's/$/_2_3_6/' $OUTPUT/ui64_to_f128_rd.tv
sed -ie 's/$/_4_3_6/' $OUTPUT/ui64_to_f128_rnm.tv
echo "Editing i32_to_f16 test vectors"
sed -ie 's/$/_0_2_0/' $OUTPUT/i32_to_f16_rne.tv
sed -ie 's/$/_1_2_0/' $OUTPUT/i32_to_f16_rz.tv
sed -ie 's/$/_3_2_0/' $OUTPUT/i32_to_f16_ru.tv
sed -ie 's/$/_2_2_0/' $OUTPUT/i32_to_f16_rd.tv
sed -ie 's/$/_4_2_0/' $OUTPUT/i32_to_f16_rnm.tv
echo "Editing i32_to_f32 test vectors"
sed -ie 's/$/_0_0_0/' $OUTPUT/i32_to_f32_rne.tv
sed -ie 's/$/_1_0_0/' $OUTPUT/i32_to_f32_rz.tv
sed -ie 's/$/_3_0_0/' $OUTPUT/i32_to_f32_ru.tv
sed -ie 's/$/_2_0_0/' $OUTPUT/i32_to_f32_rd.tv
sed -ie 's/$/_4_0_0/' $OUTPUT/i32_to_f32_rnm.tv
echo "Editing i32_to_f64 test vectors"
sed -ie 's/$/_0_1_0/' $OUTPUT/i32_to_f64_rne.tv
sed -ie 's/$/_1_1_0/' $OUTPUT/i32_to_f64_rz.tv
sed -ie 's/$/_3_1_0/' $OUTPUT/i32_to_f64_ru.tv
sed -ie 's/$/_2_1_0/' $OUTPUT/i32_to_f64_rd.tv
sed -ie 's/$/_4_1_0/' $OUTPUT/i32_to_f64_rnm.tv
echo "Editing i32_to_f128 test vectors"
sed -ie 's/$/_0_3_0/' $OUTPUT/i32_to_f128_rne.tv
sed -ie 's/$/_1_3_0/' $OUTPUT/i32_to_f128_rz.tv
sed -ie 's/$/_3_3_0/' $OUTPUT/i32_to_f128_ru.tv
sed -ie 's/$/_2_3_0/' $OUTPUT/i32_to_f128_rd.tv
sed -ie 's/$/_4_3_0/' $OUTPUT/i32_to_f128_rnm.tv
echo "Editing i64_to_f16 test vectors"
sed -ie 's/$/_0_2_4/' $OUTPUT/i64_to_f16_rne.tv
sed -ie 's/$/_1_2_4/' $OUTPUT/i64_to_f16_rz.tv
sed -ie 's/$/_3_2_4/' $OUTPUT/i64_to_f16_ru.tv
sed -ie 's/$/_2_2_4/' $OUTPUT/i64_to_f16_rd.tv
sed -ie 's/$/_4_2_4/' $OUTPUT/i64_to_f16_rnm.tv
echo "Editing i64_to_f32 test vectors"
sed -ie 's/$/_0_0_4/' $OUTPUT/i64_to_f32_rne.tv
sed -ie 's/$/_1_0_4/' $OUTPUT/i64_to_f32_rz.tv
sed -ie 's/$/_3_0_4/' $OUTPUT/i64_to_f32_ru.tv
sed -ie 's/$/_2_0_4/' $OUTPUT/i64_to_f32_rd.tv
sed -ie 's/$/_4_0_4/' $OUTPUT/i64_to_f32_rnm.tv
echo "Editing i64_to_f64 test vectors"
sed -ie 's/$/_0_1_4/' $OUTPUT/i64_to_f64_rne.tv
sed -ie 's/$/_1_1_4/' $OUTPUT/i64_to_f64_rz.tv
sed -ie 's/$/_3_1_4/' $OUTPUT/i64_to_f64_ru.tv
sed -ie 's/$/_2_1_4/' $OUTPUT/i64_to_f64_rd.tv
sed -ie 's/$/_4_1_4/' $OUTPUT/i64_to_f64_rnm.tv
echo "Editing i64_to_f128 test vectors"
sed -ie 's/$/_0_3_4/' $OUTPUT/i64_to_f128_rne.tv
sed -ie 's/$/_1_3_4/' $OUTPUT/i64_to_f128_rz.tv
sed -ie 's/$/_3_3_4/' $OUTPUT/i64_to_f128_ru.tv
sed -ie 's/$/_2_3_4/' $OUTPUT/i64_to_f128_rd.tv
sed -ie 's/$/_4_3_4/' $OUTPUT/i64_to_f128_rnm.tv
echo "Editing f16_to_ui32 test vectors"
sed -ie 's/$/_0_2_3/' $OUTPUT/f16_to_ui32_rne.tv
sed -ie 's/$/_1_2_3/' $OUTPUT/f16_to_ui32_rz.tv
sed -ie 's/$/_3_2_3/' $OUTPUT/f16_to_ui32_ru.tv
sed -ie 's/$/_2_2_3/' $OUTPUT/f16_to_ui32_rd.tv
sed -ie 's/$/_4_2_3/' $OUTPUT/f16_to_ui32_rnm.tv
echo "Editing f32_to_ui32 test vectors"
sed -ie 's/$/_0_0_3/' $OUTPUT/f32_to_ui32_rne.tv
sed -ie 's/$/_1_0_3/' $OUTPUT/f32_to_ui32_rz.tv
sed -ie 's/$/_3_0_3/' $OUTPUT/f32_to_ui32_ru.tv
sed -ie 's/$/_2_0_3/' $OUTPUT/f32_to_ui32_rd.tv
sed -ie 's/$/_4_0_3/' $OUTPUT/f32_to_ui32_rnm.tv
echo "Editing f64_to_ui32 test vectors"
sed -ie 's/$/_0_1_3/' $OUTPUT/f64_to_ui32_rne.tv
sed -ie 's/$/_1_1_3/' $OUTPUT/f64_to_ui32_rz.tv
sed -ie 's/$/_3_1_3/' $OUTPUT/f64_to_ui32_ru.tv
sed -ie 's/$/_2_1_3/' $OUTPUT/f64_to_ui32_rd.tv
sed -ie 's/$/_4_1_3/' $OUTPUT/f64_to_ui32_rnm.tv
echo "Editing f128_to_ui32 test vectors"
sed -ie 's/$/_0_3_3/' $OUTPUT/f128_to_ui32_rne.tv
sed -ie 's/$/_1_3_3/' $OUTPUT/f128_to_ui32_rz.tv
sed -ie 's/$/_3_3_3/' $OUTPUT/f128_to_ui32_ru.tv
sed -ie 's/$/_2_3_3/' $OUTPUT/f128_to_ui32_rd.tv
sed -ie 's/$/_4_3_3/' $OUTPUT/f128_to_ui32_rnm.tv
echo "Editing f16_to_ui64 test vectors"
sed -ie 's/$/_0_2_7/' $OUTPUT/f16_to_ui64_rne.tv
sed -ie 's/$/_1_2_7/' $OUTPUT/f16_to_ui64_rz.tv
sed -ie 's/$/_3_2_7/' $OUTPUT/f16_to_ui64_ru.tv
sed -ie 's/$/_2_2_7/' $OUTPUT/f16_to_ui64_rd.tv
sed -ie 's/$/_4_2_7/' $OUTPUT/f16_to_ui64_rnm.tv
echo "Editing f32_to_ui64 test vectors"
sed -ie 's/$/_0_0_7/' $OUTPUT/f32_to_ui64_rne.tv
sed -ie 's/$/_1_0_7/' $OUTPUT/f32_to_ui64_rz.tv
sed -ie 's/$/_3_0_7/' $OUTPUT/f32_to_ui64_ru.tv
sed -ie 's/$/_2_0_7/' $OUTPUT/f32_to_ui64_rd.tv
sed -ie 's/$/_4_0_7/' $OUTPUT/f32_to_ui64_rnm.tv
echo "Editing f64_to_ui64 test vectors"
sed -ie 's/$/_0_1_7/' $OUTPUT/f64_to_ui64_rne.tv
sed -ie 's/$/_1_1_7/' $OUTPUT/f64_to_ui64_rz.tv
sed -ie 's/$/_3_1_7/' $OUTPUT/f64_to_ui64_ru.tv
sed -ie 's/$/_2_1_7/' $OUTPUT/f64_to_ui64_rd.tv
sed -ie 's/$/_4_1_7/' $OUTPUT/f64_to_ui64_rnm.tv
echo "Editing f128_to_ui64 test vectors"
sed -ie 's/$/_0_3_7/' $OUTPUT/f128_to_ui64_rne.tv
sed -ie 's/$/_1_3_7/' $OUTPUT/f128_to_ui64_rz.tv
sed -ie 's/$/_3_3_7/' $OUTPUT/f128_to_ui64_ru.tv
sed -ie 's/$/_2_3_7/' $OUTPUT/f128_to_ui64_rd.tv
sed -ie 's/$/_4_3_7/' $OUTPUT/f128_to_ui64_rnm.tv
echo "Editing f16_to_i32 test vectors"
sed -ie 's/$/_0_2_1/' $OUTPUT/f16_to_i32_rne.tv
sed -ie 's/$/_1_2_1/' $OUTPUT/f16_to_i32_rz.tv
sed -ie 's/$/_3_2_1/' $OUTPUT/f16_to_i32_ru.tv
sed -ie 's/$/_2_2_1/' $OUTPUT/f16_to_i32_rd.tv
sed -ie 's/$/_4_2_1/' $OUTPUT/f16_to_i32_rnm.tv
echo "Editing f32_to_i32 test vectors"
sed -ie 's/$/_0_0_1/' $OUTPUT/f32_to_i32_rne.tv
sed -ie 's/$/_1_0_1/' $OUTPUT/f32_to_i32_rz.tv
sed -ie 's/$/_3_0_1/' $OUTPUT/f32_to_i32_ru.tv
sed -ie 's/$/_2_0_1/' $OUTPUT/f32_to_i32_rd.tv
sed -ie 's/$/_4_0_1/' $OUTPUT/f32_to_i32_rnm.tv
echo "Editing f64_to_i32 test vectors"
sed -ie 's/$/_0_1_1/' $OUTPUT/f64_to_i32_rne.tv
sed -ie 's/$/_1_1_1/' $OUTPUT/f64_to_i32_rz.tv
sed -ie 's/$/_3_1_1/' $OUTPUT/f64_to_i32_ru.tv
sed -ie 's/$/_2_1_1/' $OUTPUT/f64_to_i32_rd.tv
sed -ie 's/$/_4_1_1/' $OUTPUT/f64_to_i32_rnm.tv
echo "Editing f128_to_i32 test vectors"
sed -ie 's/$/_0_3_1/' $OUTPUT/f128_to_i32_rne.tv
sed -ie 's/$/_1_3_1/' $OUTPUT/f128_to_i32_rz.tv
sed -ie 's/$/_3_3_1/' $OUTPUT/f128_to_i32_ru.tv
sed -ie 's/$/_2_3_1/' $OUTPUT/f128_to_i32_rd.tv
sed -ie 's/$/_4_3_1/' $OUTPUT/f128_to_i32_rnm.tv
echo "Editing f16_to_i64 test vectors"
sed -ie 's/$/_0_2_5/' $OUTPUT/f16_to_i64_rne.tv
sed -ie 's/$/_1_2_5/' $OUTPUT/f16_to_i64_rz.tv
sed -ie 's/$/_3_2_5/' $OUTPUT/f16_to_i64_ru.tv
sed -ie 's/$/_2_2_5/' $OUTPUT/f16_to_i64_rd.tv
sed -ie 's/$/_4_2_5/' $OUTPUT/f16_to_i64_rnm.tv
echo "Editing f32_to_i64 test vectors"
sed -ie 's/$/_0_0_5/' $OUTPUT/f32_to_i64_rne.tv
sed -ie 's/$/_1_0_5/' $OUTPUT/f32_to_i64_rz.tv
sed -ie 's/$/_3_0_5/' $OUTPUT/f32_to_i64_ru.tv
sed -ie 's/$/_2_0_5/' $OUTPUT/f32_to_i64_rd.tv
sed -ie 's/$/_4_0_5/' $OUTPUT/f32_to_i64_rnm.tv
echo "Editing f64_to_i64 test vectors"
sed -ie 's/$/_0_1_5/' $OUTPUT/f64_to_i64_rne.tv
sed -ie 's/$/_1_1_5/' $OUTPUT/f64_to_i64_rz.tv
sed -ie 's/$/_3_1_5/' $OUTPUT/f64_to_i64_ru.tv
sed -ie 's/$/_2_1_5/' $OUTPUT/f64_to_i64_rd.tv
sed -ie 's/$/_4_1_5/' $OUTPUT/f64_to_i64_rnm.tv
echo "Editing f128_to_i64 test vectors"
sed -ie 's/$/_0_3_5/' $OUTPUT/f128_to_i64_rne.tv
sed -ie 's/$/_1_3_5/' $OUTPUT/f128_to_i64_rz.tv
sed -ie 's/$/_3_3_5/' $OUTPUT/f128_to_i64_ru.tv
sed -ie 's/$/_2_3_5/' $OUTPUT/f128_to_i64_rd.tv
sed -ie 's/$/_4_3_5/' $OUTPUT/f128_to_i64_rnm.tv
echo "Editing f16_to_f32 test vectors"
sed -ie 's/$/_0_2_2/' $OUTPUT/f16_to_f32_rne.tv
sed -ie 's/$/_1_2_2/' $OUTPUT/f16_to_f32_rz.tv
sed -ie 's/$/_3_2_2/' $OUTPUT/f16_to_f32_ru.tv
sed -ie 's/$/_2_2_2/' $OUTPUT/f16_to_f32_rd.tv
sed -ie 's/$/_4_2_2/' $OUTPUT/f16_to_f32_rnm.tv
echo "Editing f16_to_f64 test vectors"
sed -ie 's/$/_0_2_2/' $OUTPUT/f16_to_f64_rne.tv
sed -ie 's/$/_1_2_2/' $OUTPUT/f16_to_f64_rz.tv
sed -ie 's/$/_3_2_2/' $OUTPUT/f16_to_f64_ru.tv
sed -ie 's/$/_2_2_2/' $OUTPUT/f16_to_f64_rd.tv
sed -ie 's/$/_4_2_2/' $OUTPUT/f16_to_f64_rnm.tv
echo "Editing f16_to_f128 test vectors"
sed -ie 's/$/_0_2_2/' $OUTPUT/f16_to_f128_rne.tv
sed -ie 's/$/_1_2_2/' $OUTPUT/f16_to_f128_rz.tv
sed -ie 's/$/_3_2_2/' $OUTPUT/f16_to_f128_ru.tv
sed -ie 's/$/_2_2_2/' $OUTPUT/f16_to_f128_rd.tv
sed -ie 's/$/_4_2_2/' $OUTPUT/f16_to_f128_rnm.tv
echo "Editing f32_to_f16 test vectors"
sed -ie 's/$/_0_0_0/' $OUTPUT/f32_to_f16_rne.tv
sed -ie 's/$/_1_0_0/' $OUTPUT/f32_to_f16_rz.tv
sed -ie 's/$/_3_0_0/' $OUTPUT/f32_to_f16_ru.tv
sed -ie 's/$/_2_0_0/' $OUTPUT/f32_to_f16_rd.tv
sed -ie 's/$/_4_0_0/' $OUTPUT/f32_to_f16_rnm.tv
echo "Editing f32_to_f64 test vectors"
sed -ie 's/$/_0_0_0/' $OUTPUT/f32_to_f64_rne.tv
sed -ie 's/$/_1_0_0/' $OUTPUT/f32_to_f64_rz.tv
sed -ie 's/$/_3_0_0/' $OUTPUT/f32_to_f64_ru.tv
sed -ie 's/$/_2_0_0/' $OUTPUT/f32_to_f64_rd.tv
sed -ie 's/$/_4_0_0/' $OUTPUT/f32_to_f64_rnm.tv
echo "Editing f32_to_f128 test vectors"
sed -ie 's/$/_0_0_0/' $OUTPUT/f32_to_f128_rne.tv
sed -ie 's/$/_1_0_0/' $OUTPUT/f32_to_f128_rz.tv
sed -ie 's/$/_3_0_0/' $OUTPUT/f32_to_f128_ru.tv
sed -ie 's/$/_2_0_0/' $OUTPUT/f32_to_f128_rd.tv
sed -ie 's/$/_4_0_0/' $OUTPUT/f32_to_f128_rnm.tv
echo "Editing f64_to_f16 test vectors"
sed -ie 's/$/_0_1_1/' $OUTPUT/f64_to_f16_rne.tv
sed -ie 's/$/_1_1_1/' $OUTPUT/f64_to_f16_rz.tv
sed -ie 's/$/_3_1_1/' $OUTPUT/f64_to_f16_ru.tv
sed -ie 's/$/_2_1_1/' $OUTPUT/f64_to_f16_rd.tv
sed -ie 's/$/_4_1_1/' $OUTPUT/f64_to_f16_rnm.tv
echo "Editing f64_to_f32 test vectors"
sed -ie 's/$/_0_1_1/' $OUTPUT/f64_to_f32_rne.tv
sed -ie 's/$/_1_1_1/' $OUTPUT/f64_to_f32_rz.tv
sed -ie 's/$/_3_1_1/' $OUTPUT/f64_to_f32_ru.tv
sed -ie 's/$/_2_1_1/' $OUTPUT/f64_to_f32_rd.tv
sed -ie 's/$/_4_1_1/' $OUTPUT/f64_to_f32_rnm.tv
echo "Editing f64_to_f128 test vectors"
sed -ie 's/$/_0_1_1/' $OUTPUT/f64_to_f128_rne.tv
sed -ie 's/$/_1_1_1/' $OUTPUT/f64_to_f128_rz.tv
sed -ie 's/$/_3_1_1/' $OUTPUT/f64_to_f128_ru.tv
sed -ie 's/$/_2_1_1/' $OUTPUT/f64_to_f128_rd.tv
sed -ie 's/$/_4_1_1/' $OUTPUT/f64_to_f128_rnm.tv
echo "Editing f128_to_f16 test vectors"
sed -ie 's/$/_0_3_3/' $OUTPUT/f128_to_f16_rne.tv
sed -ie 's/$/_1_3_3/' $OUTPUT/f128_to_f16_rz.tv
sed -ie 's/$/_3_3_3/' $OUTPUT/f128_to_f16_ru.tv
sed -ie 's/$/_2_3_3/' $OUTPUT/f128_to_f16_rd.tv
sed -ie 's/$/_4_3_3/' $OUTPUT/f128_to_f16_rnm.tv
echo "Editing f128_to_f32 test vectors"
sed -ie 's/$/_0_3_3/' $OUTPUT/f128_to_f32_rne.tv
sed -ie 's/$/_1_3_3/' $OUTPUT/f128_to_f32_rz.tv
sed -ie 's/$/_3_3_3/' $OUTPUT/f128_to_f32_ru.tv
sed -ie 's/$/_2_3_3/' $OUTPUT/f128_to_f32_rd.tv
sed -ie 's/$/_4_3_3/' $OUTPUT/f128_to_f32_rnm.tv
echo "Editing f128_to_f64 test vectors"
sed -ie 's/$/_0_3_3/' $OUTPUT/f128_to_f64_rne.tv
sed -ie 's/$/_1_3_3/' $OUTPUT/f128_to_f64_rz.tv
sed -ie 's/$/_3_3_3/' $OUTPUT/f128_to_f64_ru.tv
sed -ie 's/$/_2_3_3/' $OUTPUT/f128_to_f64_rd.tv
sed -ie 's/$/_4_3_3/' $OUTPUT/f128_to_f64_rnm.tv
echo "Editing f16_add test vectors"
sed -ie 's/$/_0_2_6/' $OUTPUT/f16_add_rne.tv
sed -ie 's/$/_1_2_6/' $OUTPUT/f16_add_rz.tv
sed -ie 's/$/_3_2_6/' $OUTPUT/f16_add_ru.tv
sed -ie 's/$/_2_2_6/' $OUTPUT/f16_add_rd.tv
sed -ie 's/$/_4_2_6/' $OUTPUT/f16_add_rnm.tv
echo "Editing f32_add test vectors"
sed -ie 's/$/_0_0_6/' $OUTPUT/f32_add_rne.tv
sed -ie 's/$/_1_0_6/' $OUTPUT/f32_add_rz.tv
sed -ie 's/$/_3_0_6/' $OUTPUT/f32_add_ru.tv
sed -ie 's/$/_2_0_6/' $OUTPUT/f32_add_rd.tv
sed -ie 's/$/_4_0_6/' $OUTPUT/f32_add_rnm.tv
echo "Editing f64_add test vectors"
sed -ie 's/$/_0_1_6/' $OUTPUT/f64_add_rne.tv
sed -ie 's/$/_1_1_6/' $OUTPUT/f64_add_rz.tv
sed -ie 's/$/_3_1_6/' $OUTPUT/f64_add_ru.tv
sed -ie 's/$/_2_1_6/' $OUTPUT/f64_add_rd.tv
sed -ie 's/$/_4_1_6/' $OUTPUT/f64_add_rnm.tv
echo "Editing f128_add test vectors"
sed -ie 's/$/_0_3_6/' $OUTPUT/f128_add_rne.tv
sed -ie 's/$/_1_3_6/' $OUTPUT/f128_add_rz.tv
sed -ie 's/$/_3_3_6/' $OUTPUT/f128_add_ru.tv
sed -ie 's/$/_2_3_6/' $OUTPUT/f128_add_rd.tv
sed -ie 's/$/_4_3_6/' $OUTPUT/f128_add_rnm.tv
echo "Editing f16_sub test vectors"
sed -ie 's/$/_0_2_7/' $OUTPUT/f16_sub_rne.tv
sed -ie 's/$/_1_2_7/' $OUTPUT/f16_sub_rz.tv
sed -ie 's/$/_3_2_7/' $OUTPUT/f16_sub_ru.tv
sed -ie 's/$/_2_2_7/' $OUTPUT/f16_sub_rd.tv
sed -ie 's/$/_4_2_7/' $OUTPUT/f16_sub_rnm.tv
echo "Editing f32_sub test vectors"
sed -ie 's/$/_0_0_7/' $OUTPUT/f32_sub_rne.tv
sed -ie 's/$/_1_0_7/' $OUTPUT/f32_sub_rz.tv
sed -ie 's/$/_3_0_7/' $OUTPUT/f32_sub_ru.tv
sed -ie 's/$/_2_0_7/' $OUTPUT/f32_sub_rd.tv
sed -ie 's/$/_4_0_7/' $OUTPUT/f32_sub_rnm.tv
echo "Editing f64_sub test vectors"
sed -ie 's/$/_0_1_7/' $OUTPUT/f64_sub_rne.tv
sed -ie 's/$/_1_1_7/' $OUTPUT/f64_sub_rz.tv
sed -ie 's/$/_3_1_7/' $OUTPUT/f64_sub_ru.tv
sed -ie 's/$/_2_1_7/' $OUTPUT/f64_sub_rd.tv
sed -ie 's/$/_4_1_7/' $OUTPUT/f64_sub_rnm.tv
echo "Editing f128_sub test vectors"
sed -ie 's/$/_0_3_7/' $OUTPUT/f128_sub_rne.tv
sed -ie 's/$/_1_3_7/' $OUTPUT/f128_sub_rz.tv
sed -ie 's/$/_3_3_7/' $OUTPUT/f128_sub_ru.tv
sed -ie 's/$/_2_3_7/' $OUTPUT/f128_sub_rd.tv
sed -ie 's/$/_4_3_7/' $OUTPUT/f128_sub_rnm.tv
echo "Editing f16_mul test vectors"
sed -ie 's/$/_0_2_4/' $OUTPUT/f16_mul_rne.tv
sed -ie 's/$/_1_2_4/' $OUTPUT/f16_mul_rz.tv
sed -ie 's/$/_3_2_4/' $OUTPUT/f16_mul_ru.tv
sed -ie 's/$/_2_2_4/' $OUTPUT/f16_mul_rd.tv
sed -ie 's/$/_4_2_4/' $OUTPUT/f16_mul_rnm.tv
echo "Editing f32_mul test vectors"
sed -ie 's/$/_0_0_4/' $OUTPUT/f32_mul_rne.tv
sed -ie 's/$/_1_0_4/' $OUTPUT/f32_mul_rz.tv
sed -ie 's/$/_3_0_4/' $OUTPUT/f32_mul_ru.tv
sed -ie 's/$/_2_0_4/' $OUTPUT/f32_mul_rd.tv
sed -ie 's/$/_4_0_4/' $OUTPUT/f32_mul_rnm.tv
echo "Editing f64_mul test vectors"
sed -ie 's/$/_0_1_4/' $OUTPUT/f64_mul_rne.tv
sed -ie 's/$/_1_1_4/' $OUTPUT/f64_mul_rz.tv
sed -ie 's/$/_3_1_4/' $OUTPUT/f64_mul_ru.tv
sed -ie 's/$/_2_1_4/' $OUTPUT/f64_mul_rd.tv
sed -ie 's/$/_4_1_4/' $OUTPUT/f64_mul_rnm.tv
echo "Editing f128_mul test vectors"
sed -ie 's/$/_0_3_4/' $OUTPUT/f128_mul_rne.tv
sed -ie 's/$/_1_3_4/' $OUTPUT/f128_mul_rz.tv
sed -ie 's/$/_3_3_4/' $OUTPUT/f128_mul_ru.tv
sed -ie 's/$/_2_3_4/' $OUTPUT/f128_mul_rd.tv
sed -ie 's/$/_4_3_4/' $OUTPUT/f128_mul_rnm.tv
echo "Editing f16_div test vectors"
sed -ie 's/$/_0_2_0/' $OUTPUT/f16_div_rne.tv
sed -ie 's/$/_1_2_0/' $OUTPUT/f16_div_rz.tv
sed -ie 's/$/_3_2_0/' $OUTPUT/f16_div_ru.tv
sed -ie 's/$/_2_2_0/' $OUTPUT/f16_div_rd.tv
sed -ie 's/$/_4_2_0/' $OUTPUT/f16_div_rnm.tv
echo "Editing f32_div test vectors"
sed -ie 's/$/_0_0_0/' $OUTPUT/f32_div_rne.tv
sed -ie 's/$/_1_0_0/' $OUTPUT/f32_div_rz.tv
sed -ie 's/$/_3_0_0/' $OUTPUT/f32_div_ru.tv
sed -ie 's/$/_2_0_0/' $OUTPUT/f32_div_rd.tv
sed -ie 's/$/_4_0_0/' $OUTPUT/f32_div_rnm.tv
echo "Editing f64_div test vectors"
sed -ie 's/$/_0_1_0/' $OUTPUT/f64_div_rne.tv
sed -ie 's/$/_1_1_0/' $OUTPUT/f64_div_rz.tv
sed -ie 's/$/_3_1_0/' $OUTPUT/f64_div_ru.tv
sed -ie 's/$/_2_1_0/' $OUTPUT/f64_div_rd.tv
sed -ie 's/$/_4_1_0/' $OUTPUT/f64_div_rnm.tv
echo "Editing f128_div test vectors"
sed -ie 's/$/_0_3_0/' $OUTPUT/f128_div_rne.tv
sed -ie 's/$/_1_3_0/' $OUTPUT/f128_div_rz.tv
sed -ie 's/$/_3_3_0/' $OUTPUT/f128_div_ru.tv
sed -ie 's/$/_2_3_0/' $OUTPUT/f128_div_rd.tv
sed -ie 's/$/_4_3_0/' $OUTPUT/f128_div_rnm.tv
echo "Editing f16_sqrt test vectors"
sed -ie 's/$/_0_2_1/' $OUTPUT/f16_sqrt_rne.tv
sed -ie 's/$/_1_2_1/' $OUTPUT/f16_sqrt_rz.tv
sed -ie 's/$/_3_2_1/' $OUTPUT/f16_sqrt_ru.tv
sed -ie 's/$/_2_2_1/' $OUTPUT/f16_sqrt_rd.tv
sed -ie 's/$/_4_2_1/' $OUTPUT/f16_sqrt_rnm.tv
echo "Editing f32_sqrt test vectors"
sed -ie 's/$/_0_0_1/' $OUTPUT/f32_sqrt_rne.tv
sed -ie 's/$/_1_0_1/' $OUTPUT/f32_sqrt_rz.tv
sed -ie 's/$/_3_0_1/' $OUTPUT/f32_sqrt_ru.tv
sed -ie 's/$/_2_0_1/' $OUTPUT/f32_sqrt_rd.tv
sed -ie 's/$/_4_0_1/' $OUTPUT/f32_sqrt_rnm.tv
echo "Editing f64_sqrt test vectors"
sed -ie 's/$/_0_1_1/' $OUTPUT/f64_sqrt_rne.tv
sed -ie 's/$/_1_1_1/' $OUTPUT/f64_sqrt_rz.tv
sed -ie 's/$/_3_1_1/' $OUTPUT/f64_sqrt_ru.tv
sed -ie 's/$/_2_1_1/' $OUTPUT/f64_sqrt_rd.tv
sed -ie 's/$/_4_1_1/' $OUTPUT/f64_sqrt_rnm.tv
echo "Editing f128_sqrt test vectors"
sed -ie 's/$/_0_3_1/' $OUTPUT/f128_sqrt_rne.tv
sed -ie 's/$/_1_3_1/' $OUTPUT/f128_sqrt_rz.tv
sed -ie 's/$/_3_3_1/' $OUTPUT/f128_sqrt_ru.tv
sed -ie 's/$/_2_3_1/' $OUTPUT/f128_sqrt_rd.tv
sed -ie 's/$/_4_3_1/' $OUTPUT/f128_sqrt_rnm.tv
echo "Editing f16_eq test vectors"
sed -ie 's/$/_0_2_2/' $OUTPUT/f16_eq_rne.tv
sed -ie 's/$/_1_2_2/' $OUTPUT/f16_eq_rz.tv
sed -ie 's/$/_3_2_2/' $OUTPUT/f16_eq_ru.tv
sed -ie 's/$/_2_2_2/' $OUTPUT/f16_eq_rd.tv
sed -ie 's/$/_4_2_2/' $OUTPUT/f16_eq_rnm.tv
echo "Editing f32_eq test vectors"
sed -ie 's/$/_0_0_2/' $OUTPUT/f32_eq_rne.tv
sed -ie 's/$/_1_0_2/' $OUTPUT/f32_eq_rz.tv
sed -ie 's/$/_3_0_2/' $OUTPUT/f32_eq_ru.tv
sed -ie 's/$/_2_0_2/' $OUTPUT/f32_eq_rd.tv
sed -ie 's/$/_4_0_2/' $OUTPUT/f32_eq_rnm.tv
echo "Editing f64_eq test vectors"
sed -ie 's/$/_0_1_2/' $OUTPUT/f64_eq_rne.tv
sed -ie 's/$/_1_1_2/' $OUTPUT/f64_eq_rz.tv
sed -ie 's/$/_3_1_2/' $OUTPUT/f64_eq_ru.tv
sed -ie 's/$/_2_1_2/' $OUTPUT/f64_eq_rd.tv
sed -ie 's/$/_4_1_2/' $OUTPUT/f64_eq_rnm.tv
echo "Editing f128_eq test vectors"
sed -ie 's/$/_0_3_2/' $OUTPUT/f128_eq_rne.tv
sed -ie 's/$/_1_3_2/' $OUTPUT/f128_eq_rz.tv
sed -ie 's/$/_3_3_2/' $OUTPUT/f128_eq_ru.tv
sed -ie 's/$/_2_3_2/' $OUTPUT/f128_eq_rd.tv
sed -ie 's/$/_4_3_2/' $OUTPUT/f128_eq_rnm.tv
echo "Editing f16_le test vectors"
sed -ie 's/$/_0_2_3/' $OUTPUT/f16_le_rne.tv
sed -ie 's/$/_1_2_3/' $OUTPUT/f16_le_rz.tv
sed -ie 's/$/_3_2_3/' $OUTPUT/f16_le_ru.tv
sed -ie 's/$/_2_2_3/' $OUTPUT/f16_le_rd.tv
sed -ie 's/$/_4_2_3/' $OUTPUT/f16_le_rnm.tv
echo "Editing f32_le test vectors"
sed -ie 's/$/_0_0_3/' $OUTPUT/f32_le_rne.tv
sed -ie 's/$/_1_0_3/' $OUTPUT/f32_le_rz.tv
sed -ie 's/$/_3_0_3/' $OUTPUT/f32_le_ru.tv
sed -ie 's/$/_2_0_3/' $OUTPUT/f32_le_rd.tv
sed -ie 's/$/_4_0_3/' $OUTPUT/f32_le_rnm.tv
echo "Editing f64_le test vectors"
sed -ie 's/$/_0_1_3/' $OUTPUT/f64_le_rne.tv
sed -ie 's/$/_1_1_3/' $OUTPUT/f64_le_rz.tv
sed -ie 's/$/_3_1_3/' $OUTPUT/f64_le_ru.tv
sed -ie 's/$/_2_1_3/' $OUTPUT/f64_le_rd.tv
sed -ie 's/$/_4_1_3/' $OUTPUT/f64_le_rnm.tv
echo "Editing f128_le test vectors"
sed -ie 's/$/_0_3_3/' $OUTPUT/f128_le_rne.tv
sed -ie 's/$/_1_3_3/' $OUTPUT/f128_le_rz.tv
sed -ie 's/$/_3_3_3/' $OUTPUT/f128_le_ru.tv
sed -ie 's/$/_2_3_3/' $OUTPUT/f128_le_rd.tv
sed -ie 's/$/_4_3_3/' $OUTPUT/f128_le_rnm.tv
echo "Editing f16_lt test vectors"
sed -ie 's/$/_0_2_1/' $OUTPUT/f16_lt_rne.tv
sed -ie 's/$/_1_2_1/' $OUTPUT/f16_lt_rz.tv
sed -ie 's/$/_3_2_1/' $OUTPUT/f16_lt_ru.tv
sed -ie 's/$/_2_2_1/' $OUTPUT/f16_lt_rd.tv
sed -ie 's/$/_4_2_1/' $OUTPUT/f16_lt_rnm.tv
echo "Editing f32_lt test vectors"
sed -ie 's/$/_0_0_1/' $OUTPUT/f32_lt_rne.tv
sed -ie 's/$/_1_0_1/' $OUTPUT/f32_lt_rz.tv
sed -ie 's/$/_3_0_1/' $OUTPUT/f32_lt_ru.tv
sed -ie 's/$/_2_0_1/' $OUTPUT/f32_lt_rd.tv
sed -ie 's/$/_4_0_1/' $OUTPUT/f32_lt_rnm.tv
echo "Editing f64_lt test vectors"
sed -ie 's/$/_0_1_1/' $OUTPUT/f64_lt_rne.tv
sed -ie 's/$/_1_1_1/' $OUTPUT/f64_lt_rz.tv
sed -ie 's/$/_3_1_1/' $OUTPUT/f64_lt_ru.tv
sed -ie 's/$/_2_1_1/' $OUTPUT/f64_lt_rd.tv
sed -ie 's/$/_4_1_1/' $OUTPUT/f64_lt_rnm.tv
echo "Editing f128_lt test vectors"
sed -ie 's/$/_0_3_1/' $OUTPUT/f128_lt_rne.tv
sed -ie 's/$/_1_3_1/' $OUTPUT/f128_lt_rz.tv
sed -ie 's/$/_3_3_1/' $OUTPUT/f128_lt_ru.tv
sed -ie 's/$/_2_3_1/' $OUTPUT/f128_lt_rd.tv
sed -ie 's/$/_4_3_1/' $OUTPUT/f128_lt_rnm.tv
echo "Editing f16_mulAdd test vectors"
sed -ie 's/$/_0_2_0/' $OUTPUT/f16_mulAdd_rne.tv
sed -ie 's/$/_1_2_0/' $OUTPUT/f16_mulAdd_rz.tv
sed -ie 's/$/_3_2_0/' $OUTPUT/f16_mulAdd_ru.tv
sed -ie 's/$/_2_2_0/' $OUTPUT/f16_mulAdd_rd.tv
sed -ie 's/$/_4_2_0/' $OUTPUT/f16_mulAdd_rnm.tv
echo "Editing f32_mulAdd test vectors"
sed -ie 's/$/_0_0_0/' $OUTPUT/f32_mulAdd_rne.tv
sed -ie 's/$/_1_0_0/' $OUTPUT/f32_mulAdd_rz.tv
sed -ie 's/$/_3_0_0/' $OUTPUT/f32_mulAdd_ru.tv
sed -ie 's/$/_2_0_0/' $OUTPUT/f32_mulAdd_rd.tv
sed -ie 's/$/_4_0_0/' $OUTPUT/f32_mulAdd_rnm.tv
echo "Editing f64_mulAdd test vectors"
sed -ie 's/$/_0_1_0/' $OUTPUT/f64_mulAdd_rne.tv
sed -ie 's/$/_1_1_0/' $OUTPUT/f64_mulAdd_rz.tv
sed -ie 's/$/_3_1_0/' $OUTPUT/f64_mulAdd_ru.tv
sed -ie 's/$/_2_1_0/' $OUTPUT/f64_mulAdd_rd.tv
sed -ie 's/$/_4_1_0/' $OUTPUT/f64_mulAdd_rnm.tv
echo "Editing f128_mulAdd test vectors"
sed -ie 's/$/_0_3_0/' $OUTPUT/f128_mulAdd_rne.tv
sed -ie 's/$/_1_3_0/' $OUTPUT/f128_mulAdd_rz.tv
sed -ie 's/$/_3_3_0/' $OUTPUT/f128_mulAdd_ru.tv
sed -ie 's/$/_2_3_0/' $OUTPUT/f128_mulAdd_rd.tv
sed -ie 's/$/_4_3_0/' $OUTPUT/f128_mulAdd_rnm.tv
rm vectors/*.tve

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