Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Implemented on-the-fly conversion for unsigned numbers

Browse Source
This commit is contained in:
cturek 2022-05-26 22:20:43 +00:00
parent 19a759d405
commit 3301d7c52a
2 changed files with 41 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

45
pipelined/srt/srt.sv
View File

@ -85,14 +85,14 @@ module srt #(parameter Nf=52) (
// Partial Product Generation
csa csa(WS, WC, Dsel, qp, WSA, WCA);
otfc2 otfc2(clk, Start, qp, qz, qm, QuotOTFC);
expcalc expcalc(.XExp, .YExp, .calcExp);
signcalc signcalc(.XSign, .YSign, .calcSign);
srtpostproc postproc(rp, rm, Quot);
otfc otfc(qp, qz, qm, Quot, QuotOTFC);
endmodule
module srtpostproc #(parameter N=52) (
@ -216,13 +216,46 @@ endmodule
// otfc //
//////////
module otfc #(parameter N=52) (
module otfc2 #(parameter N=52) (
input logic clk,
input logic Start,
input logic qp, qz, qm,
input logic [N-1:0] Quot,
output logic [N-1:0] QuotOTFC
output logic [N-1:0] r
);
assign QuotOTFC = Quot;
// The on-the-fly converter transfers the quotient
// bits to the quotient as they come.
//
// This code follows the psuedocode presented in the
// floating point chapter of the book. Right now,
// it is written for Radix-2 division.
//
// QM is Q-1. It allows us to write negative bits
// without using a costly CPA.
logic [N+2:0] Q, QM, QNext, QMNext;
// QR and QMR are the shifted versions of Q and QM.
// They are treated as [N-1:r] size signals, and
// discard the r most significant bits of Q and QM.
logic [N+1:0] QR, QMR;
flopr #(N+3) Qreg(clk, Start, QNext, Q);
flopr #(N+3) QMreg(clk, Start, QMNext, QM);
always_comb begin
QR = Q[N+1:0];
QMR = QM[N+1:0]; // Shift Q and QM
if (qp) begin
QNext = {QR, 1'b1};
QMNext = {QR, 1'b0};
end else if (qz) begin
QNext = {QR, 1'b0};
QMNext = {QMR, 1'b1};
end else begin // If qp and qz are not true, then qm is
QNext = {QMR, 1'b1};
QMNext = {QMR, 1'b0};
end
end
assign r = Q[54] ? Q[53:2] : Q[52:1];
endmodule

4
pipelined/srt/testbench.sv
View File

@ -121,8 +121,8 @@ module testbench;
begin
errors = errors+1;
$display("OTFC is %h, should be %h\n", rOTFC, r);
$display("failed/n");
$stop;
$display("failed\n");
// $stop;
end
if (afrac === 52'hxxxxxxxxxxxxx)
begin