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1591 Commits

Author SHA1 Message Date
David Harris
e93014d6d8 Moved divide iteration register names to M stage 2021-10-10 11:30:53 -07:00
David Harris
e8d013b106 Simplified remainder for divide by 0 2021-10-10 11:20:07 -07:00
David Harris
94fd682cdc divider control signal simplificaiton 2021-10-10 10:55:02 -07:00
David Harris
bfe8bf3855 Removed negedge flops from divider 2021-10-10 10:41:13 -07:00
bbracker
179223bef0 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-10 10:10:06 -07:00
bbracker
5a987cf0ca use correct string formatting function 2021-10-10 10:09:59 -07:00
David Harris
99fd79c20b Simplified divider sign handling 2021-10-10 08:35:26 -07:00
David Harris
eaa8be14b9 renamed DivStart 2021-10-10 08:32:04 -07:00
David Harris
5cb30164d4 renamed DivSigned 2021-10-10 08:30:19 -07:00
Katherine Parry
44b023ace1 FMA matches diagram and lint warnings fixed 2021-10-09 17:38:10 -07:00
bbracker
54e0e8eb5b make testbench-linux halt on some discrepancies with QEMUw 2021-10-09 17:22:30 -07:00
kipmacsaigoren
086e6d130a rename adder in fpu for synthesis 2021-10-08 17:47:54 -05:00
kipmacsaigoren
8e35701103 Merging new changes into the old one's I've made in the OKstate servers 2021-10-08 17:47:11 -05:00
Kip Macsai-Goren
381a8fcd27 updated pmp output to correspond to test changes, commented out execute tests until cache/fence interaction works fully. 2021-10-08 15:40:18 -07:00
Kip Macsai-Goren
3623dfa51e removed loops and simplified mask generation logic. PMP's now pass my tests and linux tests up to around 300M instructions. 2021-10-08 15:33:18 -07:00
kipmacsaigoren
3103b78493 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-10-08 12:01:44 -05:00
David Harris
7e340d16fd moved fp vectors into vectors subdirectory 2021-10-07 23:28:06 -04:00
David Harris
626780381a Included TestFloat and SoftFloat 2021-10-07 23:03:45 -04:00
bbracker
64a3043a88 update wave-do 2021-10-07 19:16:52 -04:00
bbracker
25e0745a6a fix div restarting bug 2021-10-07 18:55:00 -04:00
James E. Stine
0c408a9816 update scripts 2021-10-07 15:14:54 -05:00
bbracker
ec1e04e8b8 update linker scripts to look for vmlinux files 2021-10-06 16:55:38 -04:00
James E. Stine
4dcfcfacfc TV for conversion and compare 2021-10-06 14:38:32 -05:00
James E. Stine
739e17ddac Add generic wave command file 2021-10-06 13:17:49 -05:00
James E. Stine
658dcc8c1b Update to testbench for FP stuff 2021-10-06 13:16:38 -05:00
kipmacsaigoren
086a0234ba Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-10-06 11:52:34 -05:00
James E. Stine
4ece7b5341 Add TV for testbenches (to be added shortly) however had to leave off fma due to size. The TV were slightly modified within TestFloat to add underscores for readability. The scripts I created to create these TV were also included 2021-10-06 08:56:01 -05:00
James E. Stine
b90d7b8083 Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat 2021-10-06 08:26:09 -05:00
Skylar Litz
a924e79e26 added delayed MIP signal 2021-10-04 18:23:31 -04:00
kipmacsaigoren
4a9dd49785 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-10-04 12:28:03 -05:00
David Harris
cc41d40d61 Divider cleaup 2021-10-03 11:22:34 -04:00
David Harris
3398328bf1 Divider cleanup 2021-10-03 11:16:48 -04:00
David Harris
9809e57d0c Replacing XE and DE with SrcAE and SrcBE in divider 2021-10-03 11:11:53 -04:00
David Harris
bf0061be66 Reduced cycle count for DIVW/DIVUW by two 2021-10-03 09:42:22 -04:00
David Harris
bd61ec544b Divider comments cleanup 2021-10-03 01:12:40 -04:00
David Harris
30ec68d567 Parameterized number of bits per cycle for integer division 2021-10-03 01:10:15 -04:00
David Harris
a15068717b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-03 00:43:47 -04:00
David Harris
078ddfd341 Divider cleanup 2021-10-03 00:41:41 -04:00
David Harris
8f36297569 Added suffixes to more divider signals 2021-10-03 00:32:58 -04:00
bbracker
07ff0940a3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-03 00:30:49 -04:00
bbracker
a202c705cd checkpoint generator bugfixes 2021-10-03 00:30:04 -04:00
David Harris
dcbbee6623 More divider cleanup 2021-10-03 00:20:35 -04:00
David Harris
6aa2521959 Eliminated extra inversion for subtraction in divider 2021-10-03 00:10:12 -04:00
David Harris
371f9d9a4a Added more pipeline stage suffixes to divider 2021-10-03 00:06:57 -04:00
David Harris
24bb3f4baf Added more pipeline stage suffixes to divider 2021-10-02 22:54:01 -04:00
David Harris
3441991d93 Divider mostly cleaned up 2021-10-02 21:10:35 -04:00
David Harris
67690c2ed7 Partial divider cleanup 3 2021-10-02 21:00:13 -04:00
David Harris
775520c05a Partial divider cleanup 2 2021-10-02 20:57:54 -04:00
David Harris
fe69513bb7 Partial divider cleanup 2021-10-02 20:55:37 -04:00
David Harris
a86ce5cd37 Divider code cleanup 2021-10-02 10:41:09 -04:00
David Harris
d532bde931 Added negative edge triggered flop to save inputs; do absolute value in first cycle for signed division 2021-10-02 10:36:51 -04:00
David Harris
d4437b842a Divider code cleanup 2021-10-02 10:13:49 -04:00
David Harris
0e0e204d3d Moved negating divider otuput to M stage 2021-10-02 10:03:02 -04:00
David Harris
735132191c Moved muldiv result selection to M stage for performance 2021-10-02 09:38:02 -04:00
David Harris
73d852b1ef Divide performs 2 steps per cycle 2021-10-02 09:19:25 -04:00
David Harris
35e5a5cef3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-30 23:15:34 -04:00
bbracker
5022647041 Revert "first attempt at verilog side of checkpoint functionality" 
This reverts commit f6ef8e5656.
 2021-09-30 20:45:26 -04:00
David Harris
a39e14663d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-30 20:07:43 -04:00
David Harris
a8573a27d4 Integer Divide/Rem passing all regression. 2021-09-30 20:07:22 -04:00
David Harris
953c8931ed RV32 div/rem working signed and unsigned 2021-09-30 15:24:43 -04:00
David Harris
e1ad732178 SRT Division unsigned passing Imperas tests 2021-09-30 12:17:24 -04:00
bbracker
f6ef8e5656 first attempt at verilog side of checkpoint functionality 2021-09-28 23:17:58 -04:00
bbracker
a47448c4d0 first attemtpt at checkpoint infrastructure 2021-09-28 22:33:47 -04:00
bbracker
2ffdbdf6d2 condense testbench code; debug_level of 0 means don't check at all 2021-09-27 03:03:11 -04:00
bbracker
441759b81c switch testbench-linux's interrupts from xcause to mip and improve warning messages 2021-09-22 12:33:11 -04:00
bbracker
b1c2a77fc2 update setup scripts to new testvector files 2021-09-22 12:31:10 -04:00
kipmacsaigoren
afd73ddada Merge branch 'ppa' into main 2021-09-20 01:01:47 -05:00
Ross Thompson
d09b381183 Fixed the amo on dcache miss cpu stall issue. 2021-09-17 22:15:03 -05:00
Ross Thompson
99d675b872 Finished adding the d cache flush. Required ensuring the write data, address, and size are 
correct when transmitting to AHBLite interface.
 2021-09-17 13:03:04 -05:00
Kip Macsai-Goren
f1981a1267 more input changes on prioirty thermometer. passes lint 2021-09-17 13:07:21 -04:00
kipmacsaigoren
f48c780ec2 added new fun ways of putting inputs into the priority thermometer 2021-09-17 12:00:38 -05:00
Ross Thompson
8fa287a449 The E stage needs to be flushed on InvalidateICacheM. FlushM should be asserted. 2021-09-17 10:33:57 -05:00
Ross Thompson
b92070a67a Updated Dcache to fully support flush. This appears to work. 
Updated PCNextF so it points to the correct PC after icache invalidate.
Build root crashes with PCW mismatch and invalid register writes.
 2021-09-17 10:25:21 -05:00
Ross Thompson
d4398c23fb Added states and all control and data path logic to support d cache flush. This is currently untested; however the existing regresss test passes. 2021-09-16 18:32:29 -05:00
Ross Thompson
55cbd957f0 Added counters to walk through d cache flush. 2021-09-16 17:12:51 -05:00
Ross Thompson
4ca0c0ea7d Added flush controls to cachway. 2021-09-16 16:56:48 -05:00
Ross Thompson
eb7b5f1d63 Added invalidate to icache. 2021-09-16 16:15:54 -05:00
bbracker
92ddc9b20a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-15 17:31:11 -04:00
bbracker
b1be8f4858 fix regression 2021-09-15 17:30:59 -04:00
kipmacsaigoren
437f2d5814 changed priority circuits for synthesis and light cleanup 2021-09-15 12:24:24 -05:00
David Harris
72c1cc33f5 Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression. 2021-09-15 13:14:00 -04:00
bbracker
f94a13e242 created script to determine which functions are most frequently used 2021-09-14 19:41:05 -04:00
David Harris
e32ab128e9 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-13 12:41:07 -04:00
David Harris
654f3d1940 Fixed MTVAL contents during breakpoint. Now all riscv-arch-test vectors pass in rv32 and rv64 2021-09-13 12:40:40 -04:00
Ross Thompson
d4c87d17b2 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-09-13 09:41:34 -05:00
David Harris
1847198da9 Cleaned up wally-arch test scripts 2021-09-13 00:02:32 -04:00
David Harris
b2fe8eddc0 Restored old integer divider 2021-09-12 22:07:52 -04:00
Ross Thompson
144003cb41 FPGA test bench and test program. 2021-09-12 20:41:54 -05:00
David Harris
1f6e4c71fc Modified rxfull determination in UART, started division 2021-09-12 20:00:24 -04:00
Ross Thompson
225657b8f9 Fixed bug with or_rows. 
If ROWS == 1 then the output was always X.  Fixed by adding if to check if ROWS==1.
 2021-09-11 15:51:11 -05:00
Ross Thompson
3b12235954 Fixed FPGA synthesis bug in the fpdiv fsm. Was creating latches. 2021-09-11 15:40:27 -05:00
Ross Thompson
3ff8d0095d Fixed dcache to prevent latches in FPGA synthesized design. 2021-09-11 12:03:48 -05:00
Ross Thompson
29efd1d222 Third attempt at fixing the write enables for the icache cacheway. 2021-09-09 15:08:10 -05:00
Ross Thompson
230c794edd Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Refixed some bit width issues in the icache.
 2021-09-09 12:44:02 -05:00
Ross Thompson
90f2821bea fixed some lint bugs. 2021-09-09 12:38:57 -05:00
bbracker
886e8125db Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-09 13:22:31 -04:00
bbracker
83520aeb42 changed fix_mem to not use hardcoded file names 2021-09-09 13:22:24 -04:00
David Harris
cb624fe679 Lint cleaning, riscv-arch-test testing 2021-09-09 11:05:12 -04:00
David Harris
a31828e925 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-08 16:00:12 -04:00
David Harris
30e2ec3987 Added testbench-arch for riscv-arch-test suite 2021-09-08 15:59:40 -04:00