David Harris
45b5658d06
Updated Imperas testbench to use MIP bits to communicate pending interrupts
2023-12-21 11:05:26 -08:00
David Harris
c1ad6602a3
Added commented out B extension MISA to imperas.ic; not yet working
2023-12-21 11:04:41 -08:00
David Harris
dc3284049c
Rolled back B extension in rv32/64gc MISA because imperasDV isn't matching
2023-12-21 11:03:50 -08:00
David Harris
b025cd8a0d
Updated tlbNAPOT to test instructions as well
2023-12-20 23:01:35 -08:00
David Harris
9ced88c55c
Fixed tlbNAPOT test to run and makefile to gather coverage stats
2023-12-20 21:45:14 -08:00
David Harris
06ddccd983
Fixed typo in IFU
2023-12-20 20:22:17 -08:00
David Harris
09ea6e6485
Set B in MISA for rv32gc and rv64gc
2023-12-20 16:29:31 -08:00
David Harris
d130a78616
Updated to current version of toolchain and prepare to be able to compile Zcb and Zicboz when supported
2023-12-20 16:29:03 -08:00
David Harris
8eace30f49
Moved UnalignedPCNextF mux into IFU
2023-12-20 16:18:31 -08:00
David Harris
0ff049db86
Removed unused tests from wally-riscv-arch-test
2023-12-20 13:34:12 -08:00
David Harris
8552369687
Merged PR538, delete unused tests
2023-12-20 13:30:31 -08:00
David Harris
2236e2c93c
Merge pull request #538 from ross144/main
...
Got Verilator compiling! and Questa still simulates
2023-12-20 13:18:08 -08:00
Rose Thompson
70d0169019
All regression tests which matter are running!
2023-12-20 14:57:52 -06:00
Rose Thompson
1b59182d59
Updated tests with ending label.
2023-12-20 14:55:37 -06:00
Rose Thompson
b68dd74f89
Reverted logic to bit change.
2023-12-20 13:16:32 -06:00
Rose Thompson
f52ad13a65
Merge branch 'fix'
2023-12-20 13:10:30 -06:00
Rose Thompson
18a96740d5
Revert RAM logic to bit change.
...
Added logic to hptw to prevent x propagation.
2023-12-20 13:10:20 -06:00
Rose Thompson
a8ab3c8342
Ok that is a stange bug.
...
The testbench used logic for the shadow ram, but the memory used bit. This caused questa to allocate huge amounts of memory and crash. Changing shadow ram to bit fixed the issue.
2023-12-20 12:25:34 -06:00
Rose Thompson
9de434a61b
"Resolved" ram preload issues by replacing the RAM's types with bit from logic. Tested fpga synthesis.
2023-12-20 12:05:25 -06:00
Rose Thompson
9ee1ffe8fe
Almost working with modelsim and verilator.
2023-12-20 11:29:31 -06:00
Rose Thompson
d617eb0977
DON'T keep this commit.
2023-12-19 16:56:40 -06:00
Rose Thompson
49b1b7c7f9
Fixed the last uninitialized memory issue in the priv tests.
2023-12-19 16:51:56 -06:00
Rose Thompson
b04ad23c33
Fixed bugs in the wally64periph signature.
2023-12-19 16:16:59 -06:00
Rose Thompson
726efee1e2
Fixed bugs in the cbom test.
2023-12-19 15:53:48 -06:00
David Harris
f238927013
Updated to latest Sail to support new features
2023-12-19 13:25:10 -08:00
David Harris
5dbca251d8
Defined new Zicboz and Zcb tests
2023-12-19 13:24:11 -08:00
David Harris
4186b604e0
Updated imperas.ic to throw misalignment faults on uncachable memory regions
2023-12-19 12:53:21 -08:00
David Harris
b0f34a6377
Made priority of misalignment depend on ZICCLSM_SUPPORTED and made StoreAmo take prioirty over load faults
2023-12-19 12:51:45 -08:00
Rose Thompson
418ae0decc
Fixed some regression tests with David's help.
2023-12-19 14:18:21 -06:00
Rose Thompson
4f59bd492d
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-12-19 12:06:04 -06:00
Rose Thompson
2e792606dd
More progress. Most tests are passing in modelsim.
2023-12-19 12:06:00 -06:00
Rose Thompson
74238defc3
Progress.
2023-12-18 20:23:19 -06:00
David Harris
6186181d46
Merge pull request #537 from ross144/main
...
Almost having working Verilator. One issue in the testbench remains.
2023-12-18 18:13:56 -08:00
Rose Thompson
1e1759c258
Restored the one hack change which prevents verilator from working.
2023-12-18 17:00:53 -06:00
Rose Thompson
408bb2c35b
Yay! I got verilator to compile our testbench! Does it actually work I don't know.
2023-12-18 16:44:34 -06:00
Rose Thompson
0f7b6ada04
Cleanup.
...
Verilator still has issues with riscassertions.sv and the testbench
2023-12-18 16:38:56 -06:00
Rose Thompson
b7b245fe2f
functionName.sv is now linting for rv64gc.
2023-12-18 16:37:26 -06:00
Rose Thompson
c1ac153a4f
Closer to verilator support.
2023-12-18 16:26:56 -06:00
Rose Thompson
58942b246b
Kind of a frustrating set of changes to get the verilator errors out of the copyShadow module.
2023-12-18 13:34:14 -06:00
Rose Thompson
4a3cc8b9c8
More progress towards verilator.
2023-12-18 13:26:43 -06:00
Rose Thompson
5062a8c89c
Added parameter for cache's SRAM length.
...
Progress towards verilator support.
2023-12-18 12:50:49 -06:00
Rose Thompson
1d36ce3328
Fixed lint issue.
2023-12-18 12:03:54 -06:00
David Harris
6ba3ae662f
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-12-17 19:04:50 -08:00
Rose Thompson
42d115bc27
Merge pull request #536 from stineje/main
...
Fix issue with running all and then going from one operand width to a…
2023-12-17 18:59:47 -08:00
James E. Stine
f4c1713ed4
Fix issue with running all and then going from one operand width to another. Issue is due to signals resolving between sizes. I did not catch it before because I did not run through the complete exhaustive tests. This time, went through all tests and tested all the data sizes.
2023-12-17 20:55:06 -06:00
David Harris
0eed57a0b7
Merge pull request #535 from stineje/main
...
fix bad typo on spef integration for tsmc28psyn
2023-12-15 21:13:38 -08:00
James E. Stine
54b0285300
fix bad typo on spef integration for tsmc28psyn
2023-12-15 23:06:05 -06:00
David Harris
6cb4a9e905
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-12-15 19:27:10 -08:00
David Harris
a138ef37b1
Switched to using riscv-arch-test rv32e_m suite. Need to rename it from rv32e_unratified (PR pending)
2023-12-15 19:26:50 -08:00
David Harris
d6830a1faa
Merge pull request #534 from stineje/main
...
Fix some minor issues but main push is for Issue #507 resolution
2023-12-15 19:23:27 -08:00
