Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #538 from ross144/main

Browse Source 
Got Verilator compiling! and Questa still simulates
This commit is contained in:
David Harris 2023-12-20 13:18:08 -08:00 committed by GitHub
commit 2236e2c93c
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
138 changed files with 470 additions and 89 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
sim/wave.do
View File

@ -662,8 +662,11 @@ add wave -noupdate -group wfi /testbench/dut/core/priv/priv/pmd/STATUS_TW
add wave -noupdate -group wfi /testbench/dut/core/priv/priv/pmd/PrivilegeModeW
add wave -noupdate -group wfi /testbench/dut/core/priv/priv/pmd/wfi/WFICount
add wave -noupdate -group wfi /testbench/dut/core/priv/priv/pmd/WFITimeoutM
add wave -noupdate -expand -group testbench /testbench/DCacheFlushStart
add wave -noupdate -expand -group testbench /testbench/TestComplete
add wave -noupdate -expand -group testbench /testbench/CurrState
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 4} {6586 ns} 1} {{Cursor 4} {372450 ns} 0} {{Cursor 3} {403021 ns} 1}
WaveRestoreCursors {{Cursor 4} {6586 ns} 1} {{Cursor 4} {1405857 ns} 0} {{Cursor 3} {403021 ns} 1}
quietly wave cursor active 2
configure wave -namecolwidth 250
configure wave -valuecolwidth 194
@ -679,4 +682,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {372177 ns} {372771 ns}
WaveRestoreZoom {0 ns} {16302587 ns}

8
src/mmu/hptw.sv
View File

@ -102,7 +102,8 @@ module hptw import cvw::*; #(parameter cvw_t P) (
logic HPTWLoadAccessFaultDelay, HPTWStoreAmoAccessFaultDelay, HPTWInstrAccessFaultDelay;
logic HPTWAccessFaultDelay;
logic TakeHPTWFault, TakeHPTWFaultDelay;
logic [P.XLEN-1:0] ReadDataNoXM;
// map hptw access faults onto either the original LSU load/store fault or instruction access fault
assign LSUAccessFaultM = LSULoadAccessFaultM | LSUStoreAmoAccessFaultM;
assign HPTWLoadAccessFault = LSUAccessFaultM & DTLBWalk & MemRWM[1] & ~MemRWM[0];
@ -154,7 +155,8 @@ module hptw import cvw::*; #(parameter cvw_t P) (
logic [P.XLEN-1:0] AccessedPTE;
assign AccessedPTE = {PTE[P.XLEN-1:8], (SetDirty | PTE[7]), 1'b1, PTE[5:0]}; // set accessed bit, conditionally set dirty bit
mux2 #(P.XLEN) NextPTEMux(ReadDataM, AccessedPTE, UpdatePTE, NextPTE); // NextPTE = ReadDataM when ADUE = 0 because UpdatePTE = 0
assign ReadDataNoXM = (ReadDataM[0] === 'x) ? '0 : ReadDataM; // If the PTE.V bit is x because it was read from uninitialized memory set to 0 to avoid x propagation and hanging the simulation.
mux2 #(P.XLEN) NextPTEMux(ReadDataNoXM, AccessedPTE, UpdatePTE, NextPTE); // NextPTE = ReadDataNoXM when ADUE = 0 because UpdatePTE = 0
flopenr #(P.PA_BITS) HPTWAdrWriteReg(clk, reset, SaveHPTWAdr, HPTWReadAdr, HPTWWriteAdr);
assign SaveHPTWAdr = WalkerState == L0_ADR;
@ -190,7 +192,7 @@ module hptw import cvw::*; #(parameter cvw_t P) (
assign UpdatePTE = (WalkerState == LEAF) & HPTWUpdateDA; // UpdatePTE will always be 0 if ADUE = 0 because HPTWUpdateDA will be 0
end else begin // block: hptwwrites
assign NextPTE = ReadDataM;
assign NextPTE = ReadDataNoXM;
assign HPTWAdr = HPTWReadAdr;
assign HPTWUpdateDA = '0;
assign UpdatePTE = '0;

124
testbench/testbench.sv
View File

@ -37,7 +37,7 @@ module testbench;
parameter DEBUG=0;
parameter TEST="none";
parameter PrintHPMCounters=0;
parameter BPRED_LOGGER=1;
parameter BPRED_LOGGER=0;
parameter I_CACHE_ADDR_LOGGER=0;
parameter D_CACHE_ADDR_LOGGER=0;
@ -85,7 +85,7 @@ module testbench;
logic riscofTest;
logic Validate;
logic SelectTest;
logic TestComplete;
// pick tests based on modes supported
initial begin
@ -176,6 +176,7 @@ module testbench;
STATE_LOAD_MEMORIES,
STATE_RESET_TEST,
STATE_RUN_TEST,
STATE_COPY_RAM,
STATE_CHECK_TEST,
STATE_CHECK_TEST_WAIT,
STATE_VALIDATE,
@ -186,10 +187,10 @@ module testbench;
logic LoadMem;
logic ResetCntEn;
logic ResetCntRst;
logic CopyRAM;
string signame, memfilename, pathname;
integer begin_signature_addr;
integer begin_signature_addr, end_signature_addr, signature_size;
assign ResetThreshold = 3'd5;
@ -218,8 +219,9 @@ module testbench;
STATE_LOAD_MEMORIES: NextState = STATE_RESET_TEST;
STATE_RESET_TEST: if(ResetCount < ResetThreshold) NextState = STATE_RESET_TEST;
else NextState = STATE_RUN_TEST;
STATE_RUN_TEST: if(DCacheFlushStart) NextState = STATE_CHECK_TEST;
STATE_RUN_TEST: if(TestComplete) NextState = STATE_COPY_RAM;
else NextState = STATE_RUN_TEST;
STATE_COPY_RAM: NextState = STATE_CHECK_TEST;
STATE_CHECK_TEST: if (DCacheFlushDone) NextState = STATE_VALIDATE;
else NextState = STATE_CHECK_TEST_WAIT;
STATE_CHECK_TEST_WAIT: if(DCacheFlushDone) NextState = STATE_VALIDATE;
@ -240,6 +242,8 @@ module testbench;
assign ResetCntEn = CurrState == STATE_RESET_TEST;
assign Validate = CurrState == STATE_VALIDATE;
assign SelectTest = CurrState == STATE_INIT_TEST;
assign CopyRAM = TestComplete & CurrState == STATE_RUN_TEST;
assign DCacheFlushStart = CurrState == STATE_COPY_RAM;
// fsm reset counter
counter #(3) RstCounter(clk, ResetCntRst, ResetCntEn, ResetCount);
@ -249,6 +253,8 @@ module testbench;
////////////////////////////////////////////////////////////////////////////////
logic [P.XLEN-1:0] testadr;
assign begin_signature_addr = ProgramAddrLabelArray["begin_signature"];
assign end_signature_addr = ProgramAddrLabelArray["sig_end_canary"];
assign signature_size = end_signature_addr - begin_signature_addr;
always @(posedge clk) begin
if(SelectTest) begin
if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"};
@ -317,69 +323,15 @@ module testbench;
end
////////////////////////////////////////////////////////////////////////////////
// Some memories are not reset, but should be zeros or set to some initial value for simulation
////////////////////////////////////////////////////////////////////////////////
/* -----\/----- EXCLUDED -----\/-----
integer adrindex;
always @(posedge clk) begin
if (ResetMem) // program memory is sometimes reset
if (P.UNCORE_RAM_SUPPORTED)
for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1)
dut.uncore.uncore.ram.ram.memory.RAM[adrindex] = '0;
if(reset) begin // branch predictor must always be reset
if (P.BPRED_SUPPORTED) begin
// local history only
if (P.BPRED_TYPE == `BP_LOCAL_AHEAD | P.BPRED_TYPE == `BP_LOCAL_REPAIR)
for(adrindex = 0; adrindex < 2**P.BPRED_NUM_LHR; adrindex++)
dut.core.ifu.bpred.bpred.Predictor.DirPredictor.BHT.mem[adrindex] = 0;
for(adrindex = 0; adrindex < 2**P.BTB_SIZE; adrindex++)
dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0;
for(adrindex = 0; adrindex < 2**P.BPRED_SIZE; adrindex++)
dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0;
end
end
end
-----/\----- EXCLUDED -----/\----- */
// still not working in this format
/* -----\/----- EXCLUDED -----\/-----
integer adrindex;
if (P.UNCORE_RAM_SUPPORTED) begin
always @(posedge clk) begin
if (ResetMem) // program memory is sometimes reset
for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1)
dut.uncore.uncore.ram.ram.memory.RAM[adrindex] = '0;
end
end
genvar adrindex2;
if (P.BPRED_SUPPORTED & (P.BPRED_TYPE == `BP_LOCAL_AHEAD | P.BPRED_TYPE == `BP_LOCAL_REPAIR)) begin
for(adrindex2 = 0; adrindex2 < 2**P.BPRED_NUM_LHR; adrindex2++)
always @(posedge clk) begin
dut.core.ifu.bpred.bpred.Predictor.DirPredictor.BHT.mem[adrindex2] = 0;
end
end
if (P.BPRED_SUPPORTED) begin
always @(posedge clk)
dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[0] = 0;
for(adrindex2 = 0; adrindex2 < 2**P.BTB_SIZE; adrindex2++)
always @(posedge clk) begin
dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex2] = 0;
end
for(adrindex2 = 0; adrindex2 < 2**P.BPRED_SIZE; adrindex2++)
always @(posedge clk) begin
dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex2] = 0;
end
end
-----/\----- EXCLUDED -----/\----- */
////////////////////////////////////////////////////////////////////////////////
// load memories with program image
////////////////////////////////////////////////////////////////////////////////
integer ShadowIndex;
integer LogXLEN;
integer StartIndex;
integer EndIndex;
integer BaseIndex;
if (P.SDC_SUPPORTED) begin
always @(posedge clk) begin
if (LoadMem) begin
@ -398,11 +350,20 @@ module testbench;
$readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
end
end
end else if (P.BUS_SUPPORTED) begin
end else if (P.BUS_SUPPORTED) begin : bus_supported
always @(posedge clk) begin
if (LoadMem) begin
$readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
end
if (CopyRAM) begin
LogXLEN = (1 + P.XLEN/32); // 2 for rv32 and 3 for rv64
StartIndex = begin_signature_addr >> LogXLEN;
EndIndex = (end_signature_addr >> LogXLEN) + 8;
BaseIndex = P.UNCORE_RAM_BASE >> LogXLEN;
for(ShadowIndex = StartIndex; ShadowIndex <= EndIndex; ShadowIndex++) begin
testbench.DCacheFlushFSM.ShadowRAM[ShadowIndex] = dut.uncore.uncore.ram.ram.memory.RAM[ShadowIndex - BaseIndex];
end
end
end
end
if (P.DTIM_SUPPORTED) begin
@ -411,6 +372,15 @@ module testbench;
$readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
$display("Read memfile %s", memfilename);
end
if (CopyRAM) begin
LogXLEN = (1 + P.XLEN/32); // 2 for rv32 and 3 for rv64
StartIndex = begin_signature_addr >> LogXLEN;
EndIndex = (end_signature_addr >> LogXLEN) + 8;
BaseIndex = P.UNCORE_RAM_BASE >> LogXLEN;
for(ShadowIndex = StartIndex; ShadowIndex <= EndIndex; ShadowIndex++) begin
testbench.DCacheFlushFSM.ShadowRAM[ShadowIndex] = dut.core.lsu.dtim.dtim.ram.RAM[ShadowIndex - BaseIndex];
end
end
end
end
@ -502,14 +472,15 @@ module testbench;
logic ecf; // remove this once we don't rely on old Imperas tests with Ecalls
if (P.ZICSR_SUPPORTED) assign ecf = dut.core.priv.priv.EcallFaultM;
else assign ecf = 0;
assign DCacheFlushStart = ecf &
assign TestComplete = ecf &
(dut.core.ieu.dp.regf.rf[3] == 1 |
(dut.core.ieu.dp.regf.we3 &
dut.core.ieu.dp.regf.a3 == 3 &
dut.core.ieu.dp.regf.wd3 == 1)) |
((InstrM == 32'h6f | InstrM == 32'hfc32a423 | InstrM == 32'hfc32a823) & dut.core.ieu.c.InstrValidM ) |
((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"]) & InstrMName == "SW" );
((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"]) & InstrMName == "SW" );
//assign DCacheFlushStart = TestComplete;
DCacheFlushFSM #(P) DCacheFlushFSM(.clk(clk), .reset(reset), .start(DCacheFlushStart), .done(DCacheFlushDone));
task automatic CheckSignature;
@ -567,14 +538,18 @@ module testbench;
logic [P.XLEN-1:0] sig;
// **************************************
// ***** BUG BUG BUG make sure RT undoes this.
if (P.DTIM_SUPPORTED) sig = testbench.dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i];
else if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i];
//if (P.DTIM_SUPPORTED) sig = testbench.dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i];
//else if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i];
if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i];
//if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i];
//$display("signature[%h] = %h sig = %h", i, signature[i], sig);
if (signature[i] !== sig & (signature[i] !== testbench.DCacheFlushFSM.ShadowRAM[testadr+i])) begin
//if (signature[i] !== sig & (signature[i] !== testbench.DCacheFlushFSM.ShadowRAM[testadr+i])) begin
if (signature[i] !== testbench.DCacheFlushFSM.ShadowRAM[testadr+i]) begin
errors = errors+1;
$display(" Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h",
TestName, i, (testadr+i)*(P.XLEN/8), testbench.DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]);
//$display(" Error on test %s result %d: adr = %h sim (DTIM_SUPPORTED) = %h, signature = %h",
// TestName, i, (testadr+i)*(P.XLEN/8), testbench.DCacheFlushFSM.ShadowRAM[testadr+i], signature[i]);
$stop; //***debug
end
i = i + 1;
@ -604,14 +579,15 @@ task automatic updateProgramAddrLabelArray;
inout integer ProgramAddrLabelArray [string];
// Gets the memory location of begin_signature
integer ProgramLabelMapFP, ProgramAddrMapFP;
ProgramLabelMapFP = $fopen(ProgramLabelMapFile, "r");
ProgramAddrMapFP = $fopen(ProgramAddrMapFile, "r");
if (ProgramLabelMapFP & ProgramAddrMapFP) begin // check we found both files
// *** RT: I'm a bit confused by the required initialization here.
ProgramAddrLabelArray["begin_signature"] = 0;
ProgramAddrLabelArray["tohost"] = 0;
ProgramAddrLabelArray["sig_end_canary"] = 0;
while (!$feof(ProgramLabelMapFP)) begin
string label, adrstr;
integer returncode;
@ -620,6 +596,10 @@ task automatic updateProgramAddrLabelArray;
if (ProgramAddrLabelArray.exists(label)) ProgramAddrLabelArray[label] = adrstr.atohex();
end
end
if(ProgramAddrLabelArray["begin"] == 0) $display("Couldn't find begin_signature in %s", ProgramLabelMapFile);
if(ProgramAddrLabelArray["sig_end_canary"] == 0) $display("Couldn't find sig_end_canary in %s", ProgramLabelMapFile);
$fclose(ProgramLabelMapFP);
$fclose(ProgramAddrMapFP);
/* verilator lint_on WIDTHTRUNC */

4
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D/src/WALLY-fld-01.S
View File

@ -76,6 +76,10 @@ gpr_save:
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END
// ../../wally-riscv-arch-test/riscv-test-suite/rv32i_m/D/src/WALLY-fld.S
// David_Harris@hmc.edu & Katherine Parry

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-add-01.S
View File

@ -2997,5 +2997,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-addi-01.S
View File

@ -2887,5 +2887,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-and-01.S
View File

@ -3022,5 +3022,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-andi-01.S
View File

@ -2847,5 +2847,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-auipc-01.S
View File

@ -387,5 +387,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-beq-01.S
View File

@ -3027,5 +3027,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bge-01.S
View File

@ -3012,5 +3012,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bgeu-01.S
View File

@ -3717,5 +3717,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-blt-01.S
View File

@ -3007,5 +3007,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bltu-01.S
View File

@ -3712,5 +3712,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bne-01.S
View File

@ -3007,5 +3007,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-jal-01.S
View File

@ -152,5 +152,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-jalr-01.S
View File

@ -212,5 +212,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lb-align-01.S
View File

@ -162,5 +162,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lbu-align-01.S
View File

@ -162,5 +162,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lh-align-01.S
View File

@ -152,5 +152,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lhu-align-01.S
View File

@ -157,5 +157,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lui-01.S
View File

@ -387,5 +387,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lw-align-01.S
View File

@ -157,5 +157,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-or-01.S
View File

@ -3032,5 +3032,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-ori-01.S
View File

@ -2862,5 +2862,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sb-align-01.S
View File

@ -462,5 +462,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sh-align-01.S
View File

@ -432,5 +432,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sll-01.S
View File

@ -517,5 +517,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-slli-01.S
View File

@ -522,5 +522,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-slt-01.S
View File

@ -2987,5 +2987,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-slti-01.S
View File

@ -2887,5 +2887,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sltiu-01.S
View File

@ -3562,5 +3562,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sltu-01.S
View File

@ -3692,5 +3692,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sra-01.S
View File

@ -527,5 +527,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-srai-01.S
View File

@ -512,5 +512,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-srl-01.S
View File

@ -522,5 +522,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-srli-01.S
View File

@ -517,5 +517,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sub-01.S
View File

@ -3002,5 +3002,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sw-align-01.S
View File

@ -412,5 +412,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-xor-01.S
View File

@ -2997,5 +2997,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-xori-01.S
View File

@ -2877,5 +2877,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-ADD.S
View File

@ -132,6 +132,9 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END
// ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-ADD.S

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SLT.S
View File

@ -133,6 +133,9 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END
// ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SLT.S

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SLTU.S
View File

@ -133,6 +133,9 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END
// ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SLTU.S

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SUB.S
View File

@ -133,6 +133,9 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END
// ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SUB.S

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-XOR.S
View File

@ -133,6 +133,9 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END
// ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-XOR.S

2
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-mmu-sv32-svadu-01.reference_output
View File

@ -39,7 +39,7 @@ beef0110
0000000d # Test 11.3.1.3.6(a) page fault on read when A = 0
00000bad
0000000f # Test 11.3.1.3.7(a) page fault on write when D = 0
deadbeef # Test 11.3.1.3.7(a) successful read when D = 0
12345678 # Test 11.3.1.3.7(a) successful read when D = 0
00000009 # call from going to m mode from s mode
0000000b # ecall from going to S mode from m mode
beef0770 # Test 11.3.1.3.6: check successful read/write when A=0 and MENVCFG.ADUE=1

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h
View File

@ -1428,6 +1428,9 @@ RVMODEL_DATA_BEGIN
test_1_res:
.fill 1024, 4, 0xdeadbeef
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END
#ifdef rvtest_mtrap_routine

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cbom-01.S
View File

@ -468,5 +468,8 @@ Destination3:
signature:
.fill 16, 4, 0x0bad0bad
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

4
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cboz-01.S
View File

@ -372,6 +372,8 @@ Destination2:
.fill 16, 4, 0xdeadbeef
signature:
.fill 16, 4, 0x0bad0bad
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-lrsc-01.S
View File

@ -113,4 +113,7 @@ RVMODEL_DATA_BEGIN
# signature output
wally_signature:
.fill 6, 4, -1
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

1
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32-svadu-01.S
View File

@ -88,6 +88,7 @@ test_cases:
.4byte 0x80805EA0, 0xBEEF0440, write32_test # 11.3.1.3.3
.4byte 0x8000FFA0, 0x11100393, write32_test # write executable code for "li x7, 0x111; ret" to executable region.
.4byte 0x8000FFA4, 0x00008067, write32_test # Used for 11.3.1.3.1, 11.3.1.3.2
.4byte 0x80803658, 0x12345678, write32_test # initialize memory for 11.3.1.3.7(a)
# test 11.3.1.1.3 read values back from Paddrs without translation (this also verifies the previous test)
.4byte 0x0, 0x0, goto_baremetal # satp.MODE = baremetal / no translation.

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-periph-01.S
View File

@ -917,4 +917,7 @@ RVMODEL_DATA_BEGIN
# signature output
wally_signature:
.fill 0x200, 8, 0x00000000
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-ADD.S
View File

@ -133,6 +133,9 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END
// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-ADD.S

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLT.S
View File

@ -133,6 +133,9 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END
// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLT.S

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLTU.S
View File

@ -133,6 +133,9 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END
// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLTU.S

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SUB.S
View File

@ -133,6 +133,9 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END
// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SUB.S

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-XOR.S
View File

@ -133,6 +133,9 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END
// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-XOR.S

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64ds-01.S
View File

@ -360,5 +360,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64ds-rwp1.S
View File

@ -385,5 +385,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64dsm-01.S
View File

@ -360,5 +360,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64dsm-rwp1.S
View File

@ -385,5 +385,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64es-01.S
View File

@ -360,5 +360,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64es-rwp1.S
View File

@ -385,5 +385,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64esm-01.S
View File

@ -360,5 +360,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64esm-rwp1.S
View File

@ -385,5 +385,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64im-01.S
View File

@ -1275,5 +1275,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64im-rwp1.S
View File

@ -965,5 +965,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64im-rwp2.S
View File

@ -300,5 +300,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64ks1i-01.S
View File

@ -505,5 +505,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64ks2-01.S
View File

@ -1180,5 +1180,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/andn-01.S
View File

@ -2707,5 +2707,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/clmul-01.S
View File

@ -2707,5 +2707,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/clmulh-01.S
View File

@ -2712,5 +2712,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/orn-01.S
View File

@ -2712,5 +2712,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/pack-01.S
View File

@ -2702,5 +2702,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/packh-01.S
View File

@ -2707,5 +2707,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/packu-01.S
View File

@ -2692,5 +2692,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/packuw-01.S
View File

@ -2707,5 +2707,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/packw-01.S
View File

@ -2707,5 +2707,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rev.b-01.S
View File

@ -2157,5 +2157,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rev8-01.S
View File

@ -2157,5 +2157,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rev8.w-01.S
View File

@ -2157,5 +2157,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rol-01.S
View File

@ -2712,5 +2712,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rolw-01.S
View File

@ -2707,5 +2707,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/ror-01.S
View File

@ -2707,5 +2707,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rori-01.S
View File

@ -1527,5 +1527,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/roriw-01.S
View File

@ -1512,5 +1512,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rorw-01.S
View File

@ -2707,5 +2707,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig0-01.S
View File

@ -1275,5 +1275,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig0-rwp1.S
View File

@ -965,5 +965,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig0-rwp2.S
View File

@ -300,5 +300,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig1-01.S
View File

@ -1275,5 +1275,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig1-rwp1.S
View File

@ -965,5 +965,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig1-rwp2.S
View File

@ -300,5 +300,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum0-01.S
View File

@ -1275,5 +1275,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum0-rwp1.S
View File

@ -965,5 +965,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum0-rwp2.S
View File

@ -300,5 +300,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum1-01.S
View File

@ -1275,5 +1275,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum1-rwp1.S
View File

@ -965,5 +965,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

Some files were not shown because too many files have changed in this diff Show More