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https://github.com/openhwgroup/cvw
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Merge pull request #534 from stineje/main
Fix some minor issues but main push is for Issue #507 resolution
This commit is contained in:
David Harris
GitHub
commit
d6830a1faa
@ -116,7 +116,7 @@ sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include
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# Wally needs Verilator 5.0 or later.
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# Verilator needs to be built from scratch to get the latest version
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# apt-get install verilator installs version 4.028 as of 6/8/23
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sudo apt-get install -y perl g++ ccache help2man libgoogle-perftools-dev numactl perl-doc zlibc zlib1g
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sudo apt-get install -y perl g++ ccache help2man libgoogle-perftools-dev numactl perl-doc zlib1g
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sudo apt-get install -y libfl2 libfl-dev # Ubuntu only (ignore if gives error)
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cd $RISCV
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git clone https://github.com/verilator/verilator # Only first time
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@ -127,7 +127,7 @@ git pull # Make sure git repository is up-to-date
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git checkout master # Use development branch (e.g. recent bug fixes)
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autoconf # Create ./configure script
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./configure # Configure and create Makefile
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make -j NUM_THREADS # Build Verilator itself (if error, try just 'make')
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make -j ${NUM_THREADS} # Build Verilator itself (if error, try just 'make')
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sudo make install
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# Sail (https://github.com/riscv/sail-riscv)
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@ -296,6 +296,12 @@ write_file -format ddc -hierarchy -o $filename
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set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_design ".sdf"]
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write_sdf $filename
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# Write SPEF file in case need more precision power exploration for TSMC28psyn
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if {$tech != "tsmc28psyn"} {
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set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".spef"]
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redirect $filename { write_parasitics }
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}
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# QoR
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set filename [format "%s%s" $outputDir "/reports/qor.rep"]
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redirect $filename { report_qor }
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@ -145,11 +145,9 @@ module testbenchfp;
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initial begin
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// Information displayed for user on what is simulating
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//$display("\nThe start of simulation...");
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//$display("This simulation for TEST is %s", TEST);
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//$display("This simulation for TEST is of the operand size of %s", TEST_SIZE);
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// $display("FPDUR %d %d DIVN %d LOGR %d RK %d RADIX %d DURLEN %d", FPDUR, DIVN, LOGR, RK, RADIX, DURLEN);
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// $display("\nThe start of simulation...");
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// $display("This simulation for TEST is %s", TEST);
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// $display("This simulation for TEST is of the operand size of %s", TEST_SIZE);
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if (P.Q_SUPPORTED & (TEST_SIZE == "QP" | TEST_SIZE == "all")) begin // if Quad percision is supported
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if (TEST === "cvtint" | TEST === "all") begin // if testing integer conversion
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@ -967,14 +965,6 @@ module testbenchfp;
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// Testfloat outputs 800... for both the largest integer values for both positive and negitive numbers but
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// the riscv spec specifies 2^31-1 for positive values out of range and NaNs ie 7fff...
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// Note: Went through and determined that this is not needed with new module additions
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// Just needs to check flags against TestFloat (left just in case (remove after check one more time))
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// else if ((UnitVal === `CVTINTUNIT) &
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// ~(((WriteIntVal&~OpCtrlVal[0]&AnsFlg[4]&Xs&(Res[P.XLEN-1:0] === (P.XLEN)'(0))) |
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// (WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~Xs|XNaN)&OpCtrlVal[1]&(Res[P.XLEN-1:0] === {1'b0, {P.XLEN-1{1'b1}}})) |
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// (WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~Xs|XNaN)&~OpCtrlVal[1]&(Res[P.XLEN-1:0] === {{P.XLEN-32{1'b0}}, 1'b0, {31{1'b1}}})) |
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// (~(WriteIntVal&~OpCtrlVal[0]&AnsFlg[4]&Xs&~XNaN)&(Res === Ans | NaNGood | NaNGood === 1'bx))) & (ResFlg === AnsFlg | AnsFlg === 5'bx))) begin
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else if ((UnitVal === `CVTINTUNIT) &
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~((ResFlg === AnsFlg | AnsFlg === 5'bx))) begin
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errors += 1;
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@ -1034,7 +1024,6 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
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);
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localparam Q_LEN = 32'd128;
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//`include "parameter-defs.vh"
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logic XEn;
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logic YEn;
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@ -1113,7 +1102,6 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
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if (OpCtrl[0])
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case (Fmt)
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2'b11: begin // quad
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#20;
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X = TestVector[8+2*(P.Q_LEN)-1:8+(P.Q_LEN)];
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Ans = TestVector[8+(P.Q_LEN-1):8];
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if (~clk) #5;
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@ -1121,7 +1109,6 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
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DivStart = 1'b0;
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end
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2'b01: if (P.D_SUPPORTED) begin // double
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#20;
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X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]};
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Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
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if (~clk) #5;
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@ -1129,7 +1116,6 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
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DivStart = 1'b0;
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end
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2'b00: if (P.S_SUPPORTED) begin // single
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#20;
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X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+1*(P.S_LEN)]};
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Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
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if (~clk) #5;
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@ -1137,7 +1123,6 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
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DivStart = 1'b0;
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end
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2'b10: begin // half
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#20;
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X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]};
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Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
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if (~clk) #5;
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@ -1148,7 +1133,6 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
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else
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case (Fmt)
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2'b11: begin // quad
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#20;
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X = TestVector[8+3*(P.Q_LEN)-1:8+2*(P.Q_LEN)];
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Y = TestVector[8+2*(P.Q_LEN)-1:8+(P.Q_LEN)];
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Ans = TestVector[8+(P.Q_LEN-1):8];
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@ -1157,7 +1141,6 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
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DivStart = 1'b0;
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end
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2'b01: if (P.D_SUPPORTED) begin // double
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#20;
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X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+3*(P.D_LEN)-1:8+2*(P.D_LEN)]};
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Y = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]};
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Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
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@ -1166,7 +1149,6 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
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DivStart = 1'b0;
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end
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2'b00: if (P.S_SUPPORTED) begin // single
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#20;
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X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+3*(P.S_LEN)-1:8+2*(P.S_LEN)]};
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Y = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+1*(P.S_LEN)]};
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Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
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@ -1175,7 +1157,6 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
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DivStart = 1'b0;
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end
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2'b10: begin // half
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#20;
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X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+3*(P.H_LEN)-1:8+2*(P.H_LEN)]};
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Y = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]};
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Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
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@ -1403,11 +1384,11 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
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assign XEn = ~((Unit == `CVTINTUNIT)&OpCtrl[2]);
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assign YEn = ~((Unit == `CVTINTUNIT)|(Unit == `CVTFPUNIT)|((Unit == `DIVUNIT)&OpCtrl[0]));
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assign ZEn = (Unit == `FMAUNIT);
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// Will fix with better activation - for now, this works (jes)
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assign FPUActive = 1'b1;
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unpack #(P) unpack(.X, .Y, .Z, .Fmt(ModFmt), .FPUActive, .Xs, .Ys, .Zs, .Xe, .Ye, .Ze,
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.Xm, .Ym, .Zm, .XNaN, .YNaN, .ZNaN, .XSNaN, .YSNaN, .ZSNaN,
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.XSubnorm, .XZero, .YZero, .ZZero, .XInf, .YInf, .ZInf,
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.XEn, .YEn, .ZEn, .XExpMax, .XPostBox);
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endmodule
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