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https://github.com/openhwgroup/cvw
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Merge branch 'fix'
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f52ad13a65
@ -42,7 +42,7 @@ module ram1p1rwbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44, PRE
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output logic [WIDTH-1:0] dout
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);
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bit [WIDTH-1:0] RAM[DEPTH-1:0];
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logic [WIDTH-1:0] RAM[DEPTH-1:0];
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// ***************************************************************************
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// TRUE SRAM macro
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@ -102,7 +102,8 @@ module hptw import cvw::*; #(parameter cvw_t P) (
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logic HPTWLoadAccessFaultDelay, HPTWStoreAmoAccessFaultDelay, HPTWInstrAccessFaultDelay;
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logic HPTWAccessFaultDelay;
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logic TakeHPTWFault, TakeHPTWFaultDelay;
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logic [P.XLEN-1:0] ReadDataNoXM;
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// map hptw access faults onto either the original LSU load/store fault or instruction access fault
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assign LSUAccessFaultM = LSULoadAccessFaultM | LSUStoreAmoAccessFaultM;
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assign HPTWLoadAccessFault = LSUAccessFaultM & DTLBWalk & MemRWM[1] & ~MemRWM[0];
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@ -154,7 +155,8 @@ module hptw import cvw::*; #(parameter cvw_t P) (
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logic [P.XLEN-1:0] AccessedPTE;
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assign AccessedPTE = {PTE[P.XLEN-1:8], (SetDirty | PTE[7]), 1'b1, PTE[5:0]}; // set accessed bit, conditionally set dirty bit
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mux2 #(P.XLEN) NextPTEMux(ReadDataM, AccessedPTE, UpdatePTE, NextPTE); // NextPTE = ReadDataM when ADUE = 0 because UpdatePTE = 0
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assign ReadDataNoXM = (ReadDataM === 'x) ? '0 : ReadDataM; // Hack to ensure the TLBs are never written with x's because they will propagate and hang the simulation.
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mux2 #(P.XLEN) NextPTEMux(ReadDataNoXM, AccessedPTE, UpdatePTE, NextPTE); // NextPTE = ReadDataNoXM when ADUE = 0 because UpdatePTE = 0
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flopenr #(P.PA_BITS) HPTWAdrWriteReg(clk, reset, SaveHPTWAdr, HPTWReadAdr, HPTWWriteAdr);
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assign SaveHPTWAdr = WalkerState == L0_ADR;
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@ -190,7 +192,7 @@ module hptw import cvw::*; #(parameter cvw_t P) (
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assign UpdatePTE = (WalkerState == LEAF) & HPTWUpdateDA; // UpdatePTE will always be 0 if ADUE = 0 because HPTWUpdateDA will be 0
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end else begin // block: hptwwrites
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assign NextPTE = ReadDataM;
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assign NextPTE = ReadDataNoXM;
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assign HPTWAdr = HPTWReadAdr;
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assign HPTWUpdateDA = '0;
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assign UpdatePTE = '0;
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