David Harris
87aa0724a2
IFU cleanup
2022-01-27 17:18:55 +00:00
David Harris
218ff3e25d
IFU cleanup
2022-01-27 16:41:57 +00:00
David Harris
1c22077841
Optimized out second adder from IFU for PC+2
2022-01-27 16:06:24 +00:00
David Harris
62e5c7fd13
Comments in LSU code about restructuring
2022-01-27 15:53:59 +00:00
Ross Thompson
75c33bc6c9
BPPredWrongM needs to be 0 when there is no branch predictor. BPPredWRongM is only used when there is an icacheflush.
2022-01-27 07:59:59 -06:00
Ross Thompson
c3a78553be
Removed mux in PCNextF logic. Minor IFU improvements.
2022-01-26 22:33:26 -06:00
Ross Thompson
23c4ba2777
1. Modified the cache so it can handle the reset delay internally. This removes the mux from the IFU.
...
2. Removed the write address delay from simpleram.sv
3. Fixed rv32tim and rv32ic mode to handle missalignment correctly.
4. Added imperas32i and imperas32c to rv32tim mode.
2022-01-26 18:23:39 -06:00
Ross Thompson
2c982dca03
IFU simplifications.
2022-01-26 13:54:59 -06:00
Ross Thompson
728e46a794
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-25 19:21:04 -06:00
David Harris
22c84dcd80
simpleram simplification
2022-01-25 19:46:13 +00:00
David Harris
8bf73d0eb3
simpleram simplification
2022-01-25 19:40:07 +00:00
David Harris
f07123ff0f
simpleram simplification
2022-01-25 18:26:31 +00:00
David Harris
7ac44cb3fc
simpleram address simplification
2022-01-25 18:17:33 +00:00
David Harris
5eb71a3bbe
simpleram address simplification
2022-01-25 18:00:50 +00:00
David Harris
d9888c91a6
simpleram clk and reset simplification
2022-01-25 17:34:15 +00:00
David Harris
5cb879129e
Start of IFU cleanup
2022-01-25 17:31:53 +00:00
Ross Thompson
4d4d9ac8cf
Added spill support back into the IROM IFU.
2022-01-21 15:50:54 -06:00
Ross Thompson
4ecc2d029a
Changed the IROM and DTIM memories to behave like edge-triggered srams.
2022-01-21 15:42:54 -06:00
Ross Thompson
ec44774c77
Factored out InstrValidNotFlushedM from each csr*.sv to csr.sv
2022-01-20 16:39:54 -06:00
David Harris
ca1f7ce5d3
Renamed wallypipelinedhart to wallypipelinedcore
2022-01-20 16:02:08 +00:00
Ross Thompson
05ebadacad
Added PCNextF and PostSpillInstrRawF to ila.
2022-01-19 14:05:14 -06:00
Ross Thompson
5cf686429d
Merged in the debug ila updates.
2022-01-18 17:29:21 -06:00
Ross Thompson
2508b9d35a
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-18 17:19:59 -06:00
Ross Thompson
fdc17f5017
Updated CSR modules to prevent writting the registers when flushing. This only effects architecture writes not side effect writes.
2022-01-18 17:19:33 -06:00
David Harris
de7b9c127e
Added E extension, and downloaded riscv-dv and embench-iot to addins
2022-01-17 14:42:59 +00:00
David Harris
8b62130070
lsu cleanup down to 346 lines
2022-01-15 01:19:44 +00:00
David Harris
b967bcede2
LSU Cleanup
2022-01-15 01:11:17 +00:00
David Harris
f7f3882cb8
Moved Dcache into bus block
2022-01-15 00:39:07 +00:00
David Harris
d9e8d16bbe
Renamed LSUStall to LSUStallM
2022-01-15 00:24:16 +00:00
David Harris
b0263012e8
LSU cleanup
2022-01-15 00:11:30 +00:00
David Harris
4c5962095e
LSU cleanup
2022-01-15 00:03:03 +00:00
David Harris
37bf5347cf
LSU cleanup
2022-01-14 23:55:27 +00:00
Ross Thompson
dd1ebb75f0
Fixed spillthreshold warning.
2022-01-14 17:23:39 -06:00
Ross Thompson
9d2a79f180
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-14 17:16:53 -06:00
David Harris
380e990def
moved fp to tests
2022-01-14 23:05:59 +00:00
David Harris
291deb5c39
LSU partitioning
2022-01-14 23:02:28 +00:00
Ross Thompson
db519a0dca
Cleanup IFU comments.
2022-01-14 15:06:30 -06:00
Ross Thompson
a70e12ad75
Optimization in the ifu. Please note this optimization is not strictly correct,
...
but is possible. See comments in the ifu source code for details.
2022-01-14 12:16:48 -06:00
Ross Thompson
a549079672
More ifu cleanup.
2022-01-14 11:19:12 -06:00
Ross Thompson
ce937a35a8
Added tim only test to regression-wally. Minor cleanup to ifu.
2022-01-14 11:13:06 -06:00
Ross Thompson
5726b5b640
Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.
2022-01-13 22:21:43 -06:00
Ross Thompson
9f7e3f147b
Partial local dtim in lsu configuration.
2022-01-13 17:50:31 -06:00
Ross Thompson
0b06fa12ef
Merge branch 'testDivInterruptInterlock' into main
2022-01-13 11:21:48 -06:00
Ross Thompson
93cb24476f
Fixed interger divide so it can be interrupted.
2022-01-13 11:16:50 -06:00
Ross Thompson
4bcabd1a55
Removed unused inputs to hptw.
2022-01-13 11:04:48 -06:00
Ross Thompson
654a33bf92
Fixed bug in the lsu's write back data. If an AMO was uncached it would not be corrected executed because the write data to the bus would not include the amoalu.
2022-01-12 17:41:39 -06:00
Ross Thompson
861450c4d6
Fixed support to allow spills and no icache.
2022-01-12 17:25:16 -06:00
Ross Thompson
000d713cb5
Better solution to the integer divider interrupt interaction.
2022-01-12 14:22:18 -06:00
Ross Thompson
26fb09c868
Added additional fsm to ILA.
2022-01-12 14:17:16 -06:00
Ross Thompson
6eb2f37ce4
Possible fix for the TrapM DTLBMiss suppression.
2022-01-12 14:17:16 -06:00
Ross Thompson
6b483e621d
If a trap occurs concurrent with a I/DTLB miss the interlock fsm incorrectly goes into the states to handle the TLB miss.
...
This commit fixes this bug by keeping the interlock fsm in the T0_READY state on TrapM.
2022-01-12 14:17:16 -06:00
Ross Thompson
48c036a923
Oups. My hack for DivE interrupt prevention was wrong.
2022-01-12 14:17:16 -06:00
Ross Thompson
796316495d
Hack "fix" to prevent interrupt from occuring during an integer divide.
...
This is not the desired solution but will allow continued debuging of linux.
2022-01-12 14:17:16 -06:00
Ross Thompson
55456e465c
Added icache access and icache miss to performance counters.
2022-01-09 22:56:56 -06:00
Ross Thompson
b6ae6fea27
Fixed bug with interlock fsm. The interlock fsm should suppress bus and cache requests by the cpu
...
only at the start of a request. Pending interrupt was used to start one of these suppressions;
however because of the way the cache's fsm was separated from the bus fsm, the cache now made requests
to the bus fsm. On a miss with write back, the inital fetch is handled correctly. However if an
interrupt becam pending then the the next request (eviction) made by the cache was also suppressed.
This keeps the d cache fsm stuck in the STATE_MISS_EVICT_DIRTY state as it think it has made a request
to the bus fsm, but the pending interrupt ignored the request.
The solution is to modify how cpu requests are suppressed. Instead of relying on pending interrupt
it is better to use interrupt which will be disabled if the dcache is currently processing the evict.
2022-01-07 17:55:34 -06:00
David Harris
3d2671a8b0
Reformatted MIT license to 95 characters
2022-01-07 12:58:40 +00:00
David Harris
913a78323c
moved proposed-sdc
2022-01-07 12:44:21 +00:00
David Harris
6c0cd5ef20
piplined directory cleanup
2022-01-07 12:43:50 +00:00
David Harris
8481c93e1b
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-07 05:39:16 +00:00
Ross Thompson
de3bbd3fe0
Also fixed undetected bug with amo concurrent with tlb miss. It was possible for the amoalu to apply a function to the hptw readdata.
...
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-06 23:28:02 -06:00
David Harris
261882bf78
Used .* in wrapper
2022-01-07 05:23:42 +00:00
Ross Thompson
fa0080ca70
Modified the mmu to not mux the lower 12 bits of the physical address and instead directly
...
assign from the input non translated virtual address. Since the lower bits never change there is
no reason to place these lower bits on a longer critical path.
The cache and lsu were previously using the lower bits from the virtual address rather than
the physical address. This change will allow us to keep the shorter critical path and
reduce the complexity of the lsu, ifu, and cache drawings.
2022-01-06 23:19:09 -06:00
David Harris
2df92af488
Capitalized LSU and IFU, changed MulDiv to MDU
2022-01-07 04:30:00 +00:00
David Harris
27c1d73cb1
Code cleanup
2022-01-07 04:07:04 +00:00
Ross Thompson
5402b55c44
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-06 17:19:20 -06:00
Ross Thompson
0438975e27
Minor optimization to cache replacement.
2022-01-06 17:19:14 -06:00
David Harris
6fafabbfad
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-06 23:04:33 +00:00
David Harris
ae64b859c3
Fixed multiplier nan boxing bug
2022-01-06 23:03:29 +00:00
Katherine Parry
631d05dcdc
some FPU test fixes
2022-01-06 23:03:20 +00:00
Ross Thompson
e0740034f0
Clean up of cachefsm.
2022-01-06 16:32:49 -06:00
David Harris
3bfe23bc75
More FP unpacking fix
2022-01-06 22:22:22 +00:00
David Harris
770780e394
Floating point test cleanup
2022-01-06 21:45:16 +00:00
David Harris
a5a89e58a8
Fixed unpacking bug; regression runs again
2022-01-06 18:22:30 +00:00
David Harris
eff9cec415
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-06 18:10:32 +00:00
David Harris
aca26de498
FPU debug and configurable logic cleanup
2022-01-06 18:10:25 +00:00
Ross Thompson
f604a0d79e
cleaned up cacheway and sram1rw.sv. also noticed possible bug in sram1rw.sv.
2022-01-05 22:56:18 -06:00
Ross Thompson
a4afc1bc54
More name cleanup in cache.
2022-01-05 22:37:53 -06:00
Ross Thompson
e74e8c2e86
Changed names of address in caches.
...
Removed old cache files.
2022-01-05 22:19:36 -06:00
Ross Thompson
1ab3a17ff7
Updates to support fpga.
2022-01-05 18:07:23 -06:00
Ross Thompson
9ea34e390a
Fixed xilinx synth error with $error in extend.sv
2022-01-05 17:48:08 -06:00
Ross Thompson
de32930e63
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-05 16:57:29 -06:00
Ross Thompson
da585b30f9
Slower but correct implementation of flush.
2022-01-05 16:57:22 -06:00
David Harris
90dd961ea5
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-05 22:10:33 +00:00
David Harris
07932ad0aa
Replaced exe2memfile with SiFive elf2hex
2022-01-05 22:10:26 +00:00
Ross Thompson
7086a0ed08
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-05 14:15:27 -06:00
Ross Thompson
cc51a27a34
Fixed bug with flush dirty not cleared in the correct cache line.
2022-01-05 14:14:01 -06:00
David Harris
d17a305538
Finished removing generate statements
2022-01-05 16:41:17 +00:00
David Harris
6d4714651c
Removed more generate statements
2022-01-05 16:25:08 +00:00
David Harris
da5ead23bf
Removed more generate statements
2022-01-05 16:01:03 +00:00
David Harris
d66f7c841b
Removed generate statements
2022-01-05 14:35:25 +00:00
Ross Thompson
98be8201b2
Renamed most signals inside cache.sv so they are agnostic to i or d.
2022-01-04 23:52:42 -06:00
Ross Thompson
fffaf654e6
the i and d caches now share common verilog.
2022-01-04 23:40:37 -06:00
Ross Thompson
13dbf3cc0f
parameterized the caches with the goal of using common rtl for both i and d caches.
2022-01-04 22:40:51 -06:00
Ross Thompson
888a60d8d6
Switched block for line in caches.
2022-01-04 22:08:18 -06:00
Ross Thompson
cb301a78ad
Fixed bug where last line of dcache was not written back to memory on dcache flush.
2022-01-04 21:55:48 -06:00
Ross Thompson
ecc7bf5237
Fixed dcache flush.
2022-01-04 18:40:58 -06:00
David Harris
d1a7416028
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-04 19:47:51 +00:00
David Harris
115287adc8
Renamed wally-pipelined to pipelined
2022-01-04 19:47:41 +00:00
