Ross Thompson
|
5264577dcf
|
Possible fix for icache deadlock interaction with hptw.
|
2021-12-17 14:38:25 -06:00 |
|
Ross Thompson
|
9f798250ea
|
Oups missed files in the last commit.
|
2021-12-15 10:25:08 -06:00 |
|
Ross Thompson
|
f061a26411
|
Cleaned up fpga synthesis script.
|
2021-12-13 18:26:54 -06:00 |
|
Ross Thompson
|
7d00649b61
|
Formating changes to cache fsms.
|
2021-12-13 17:16:13 -06:00 |
|
Ross Thompson
|
5361f69639
|
Fixed some typos in the dcache ptw interaction documentation.
|
2021-12-13 15:47:20 -06:00 |
|
Ross Thompson
|
547093b705
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2021-12-12 17:21:51 -06:00 |
|
Ross Thompson
|
bb79f70a63
|
Modified FPGA to add additional signals to ILA. Created advanced trigger for ILA using vivado's tsm language.
|
2021-12-12 17:21:44 -06:00 |
|
Ross Thompson
|
cd59809e42
|
Fixed numerous errors in the preformance counter updates.
Fixed dcache reporting of access and misses.
Added performance counter tracking to coremark.
|
2021-12-09 11:44:12 -06:00 |
|
Ross Thompson
|
e43aa6ead4
|
Merge branch 'main' into fpga
|
2021-11-29 10:06:53 -06:00 |
|
Ross Thompson
|
2f85ac7f38
|
Fixed a very complex interaction between interrupts, the icache, dcache, and hptw.
If an interrupt occurred at the start of an ITLB miss or DTLB miss the page table
walk should be aborted before starting.
|
2021-11-20 22:35:47 -06:00 |
|
Ross Thompson
|
8aad95366d
|
Fixed the 4 way set associative pseudo LRU replacement policy.
|
2021-10-29 12:46:02 -05:00 |
|
Ross Thompson
|
f61fcd25a9
|
Possible fix for the incorrect behavior of the pseudo LRU replacement policy for 4 ways set associative caches.
|
2021-10-29 11:03:37 -05:00 |
|
Ross Thompson
|
54c714d222
|
Applied batch from fpga branch which fixes the dcache fence bug. The should cause the dcache to flush all dirty cache lines to main memory. The bug caused the dirty reset to clear each way for a particular line.
|
2021-10-28 11:07:18 -05:00 |
|
Ross Thompson
|
d98baf90a3
|
Replaced async reset flip flops with sync reset flip flops in cache and bpread.
|
2021-10-27 09:57:11 -05:00 |
|
David Harris
|
1a6fb2fad9
|
Forgot to save cacheway merge
|
2021-10-26 08:38:13 -07:00 |
|
David Harris
|
79c1395967
|
merging changes
|
2021-10-26 08:34:36 -07:00 |
|
David Harris
|
44de52a05a
|
Synchronous reset in non-flop blocks
|
2021-10-26 08:30:35 -07:00 |
|
Ross Thompson
|
09b3549efd
|
Fixed another critical path in the caches.
|
2021-10-25 22:05:11 -05:00 |
|
Ross Thompson
|
cb7015a690
|
Fixed the timing issue in the cache replacement polcy.
|
2021-10-25 18:00:23 -05:00 |
|
Ross Thompson
|
6c92d3267f
|
Fixed bug with the changes to sram1rw.
|
2021-10-25 16:11:41 -05:00 |
|
Ross Thompson
|
694b3fbb6f
|
Possible fix for critical path timing in caches.
|
2021-10-25 15:33:33 -05:00 |
|
Ross Thompson
|
f7583d0e0d
|
Updated uncore to use sdc.
Fixed bug with fence instruction not correctly clearing dirty bits in d cache.
|
2021-10-25 14:07:44 -05:00 |
|
Ross Thompson
|
ebef47b1c9
|
Modified the cache's sram model so if it used to synthesize flip flops it terminates the read critical path at the address's input rather than the output read data.
|
2021-10-24 21:21:49 -05:00 |
|
Ross Thompson
|
87aaec3b6c
|
Partial cleanup of unused signals in caches and bpred.
|
2021-10-24 15:04:20 -05:00 |
|
David Harris
|
106982e493
|
more lsu/ifu lint cleanup
|
2021-10-23 12:10:13 -07:00 |
|
David Harris
|
8b1dc81d34
|
more lsu/ifu lint cleanup
|
2021-10-23 12:00:32 -07:00 |
|
David Harris
|
5235e61d9e
|
Lint cleanup
|
2021-10-23 09:06:21 -07:00 |
|
David Harris
|
bf3eb7b814
|
update scripts for handling src/*/* subdirectories
|
2021-10-23 08:54:29 -07:00 |
|
David Harris
|
ff409d4fe7
|
Lint cleanup
|
2021-10-23 08:39:21 -07:00 |
|
David Harris
|
8b854bb1c2
|
Cleaned up LINT erors
|
2021-10-23 06:28:49 -07:00 |
|
Ross Thompson
|
09dc3e1143
|
Merge branch 'main' into fpga
|
2021-10-20 16:24:55 -05:00 |
|
Ross Thompson
|
f4e64c2eaf
|
Added debug signals to dcache.
|
2021-10-20 15:52:05 -05:00 |
|
David Harris
|
df0b65e483
|
replaced flopenl with flopenr when clearing to 0
|
2021-10-18 16:53:18 -07:00 |
|
Ross Thompson
|
d8d414665c
|
fixed issues with dc shell not liking modules with parameters without default values.
|
2021-10-18 17:24:15 -05:00 |
|
Ross Thompson
|
d09b381183
|
Fixed the amo on dcache miss cpu stall issue.
|
2021-09-17 22:15:03 -05:00 |
|
Ross Thompson
|
99d675b872
|
Finished adding the d cache flush. Required ensuring the write data, address, and size are
correct when transmitting to AHBLite interface.
|
2021-09-17 13:03:04 -05:00 |
|
Ross Thompson
|
b92070a67a
|
Updated Dcache to fully support flush. This appears to work.
Updated PCNextF so it points to the correct PC after icache invalidate.
Build root crashes with PCW mismatch and invalid register writes.
|
2021-09-17 10:25:21 -05:00 |
|
Ross Thompson
|
d4398c23fb
|
Added states and all control and data path logic to support d cache flush. This is currently untested; however the existing regresss test passes.
|
2021-09-16 18:32:29 -05:00 |
|
Ross Thompson
|
55cbd957f0
|
Added counters to walk through d cache flush.
|
2021-09-16 17:12:51 -05:00 |
|
Ross Thompson
|
4ca0c0ea7d
|
Added flush controls to cachway.
|
2021-09-16 16:56:48 -05:00 |
|
Ross Thompson
|
eb7b5f1d63
|
Added invalidate to icache.
|
2021-09-16 16:15:54 -05:00 |
|
Ross Thompson
|
3ff8d0095d
|
Fixed dcache to prevent latches in FPGA synthesized design.
|
2021-09-11 12:03:48 -05:00 |
|
Ross Thompson
|
29efd1d222
|
Third attempt at fixing the write enables for the icache cacheway.
|
2021-09-09 15:08:10 -05:00 |
|
Ross Thompson
|
230c794edd
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
Refixed some bit width issues in the icache.
|
2021-09-09 12:44:02 -05:00 |
|
Ross Thompson
|
90f2821bea
|
fixed some lint bugs.
|
2021-09-09 12:38:57 -05:00 |
|
David Harris
|
cb624fe679
|
Lint cleaning, riscv-arch-test testing
|
2021-09-09 11:05:12 -04:00 |
|
Ross Thompson
|
150a73d6cf
|
Set associate icache working, but way 0 is never written.
|
2021-09-07 12:46:16 -05:00 |
|
Ross Thompson
|
00f50184d8
|
Changed name of memory in icache.
|
2021-09-06 20:54:52 -05:00 |
|
Ross Thompson
|
5c2deab4e4
|
Partial multiway set associative icache.
|
2021-08-30 10:49:24 -05:00 |
|
Ross Thompson
|
4b0344898b
|
Fixed bugs I introduced to the icache.
|
2021-08-27 15:00:40 -05:00 |
|