Ross Thompson 99d675b872 Finished adding the d cache flush. Required ensuring the write data, address, and size are ... correct when transmitting to AHBLite interface.		2021-09-17 13:03:04 -05:00
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cachereplacementpolicy.sv	Lint cleaning, riscv-arch-test testing	2021-09-09 11:05:12 -04:00
cacheway.sv	Updated Dcache to fully support flush. This appears to work.	2021-09-17 10:25:21 -05:00
dcache_ptw_interaction_README.txt	Modified icache to no longer need StallF in the PCMux logic. Instead this is handled in the icachefsm.	2021-08-27 11:03:36 -05:00
dcache.sv	Finished adding the d cache flush. Required ensuring the write data, address, and size are	2021-09-17 13:03:04 -05:00
dcachefsm.sv	Updated Dcache to fully support flush. This appears to work.	2021-09-17 10:25:21 -05:00
icache.sv	Updated Dcache to fully support flush. This appears to work.	2021-09-17 10:25:21 -05:00
icachefsm.sv	Set associate icache working, but way 0 is never written.	2021-09-07 12:46:16 -05:00
sram1rw.sv	change sram1rw to have a small delay so that we don't have signals changing on clock edges	2021-07-19 11:30:07 -04:00