Ross Thompson f61fcd25a9 Possible fix for the incorrect behavior of the pseudo LRU replacement policy for 4 ways set associative caches.		2021-10-29 11:03:37 -05:00
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cachereplacementpolicy.sv	Possible fix for the incorrect behavior of the pseudo LRU replacement policy for 4 ways set associative caches.	2021-10-29 11:03:37 -05:00
cacheway.sv	Replaced async reset flip flops with sync reset flip flops in cache and bpread.	2021-10-27 09:57:11 -05:00
dcache_ptw_interaction_README.txt	Modified icache to no longer need StallF in the PCMux logic. Instead this is handled in the icachefsm.	2021-08-27 11:03:36 -05:00
dcache.sv	Applied batch from fpga branch which fixes the dcache fence bug. The should cause the dcache to flush all dirty cache lines to main memory. The bug caused the dirty reset to clear each way for a particular line.	2021-10-28 11:07:18 -05:00
dcachefsm.sv	Replaced async reset flip flops with sync reset flip flops in cache and bpread.	2021-10-27 09:57:11 -05:00
icache.sv	Partial cleanup of unused signals in caches and bpred.	2021-10-24 15:04:20 -05:00
icachefsm.sv	Replaced async reset flip flops with sync reset flip flops in cache and bpread.	2021-10-27 09:57:11 -05:00
sram1rw.sv	Fixed bug with the changes to sram1rw.	2021-10-25 16:11:41 -05:00