Jordan Carlin
23f037e76e
Add misaligned cjal and cjalr tests
2024-09-29 22:33:11 -07:00
Jordan Carlin
330eda243c
Remove wally32i and wally64i tests since they are covered elsewhere now
2024-09-29 10:26:08 -07:00
Jordan Carlin
ef442808a9
Remove old imperas tests
2024-09-29 10:18:04 -07:00
David Harris
26f3c2a607
Added lockstep support for RV32. Not all wally privileged tests pass yet
2024-08-29 10:44:37 -07:00
David Harris
d4a8377406
Merge pull request #862 from jordancarlin/verilator_fixes
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Remove Verilator hack
2024-08-08 20:50:50 -07:00
David Harris
bc70f0b933
Merge pull request #869 from jordancarlin/installation
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Installation and setup overhaul
2024-08-08 15:39:23 -07:00
David Harris
fa98ae8c30
Depricate conditional generation based on A_SUPPORTED, which is now computed from ZALRSC_SUPPORTED and ZAAMO_SUPPORTED
2024-08-08 05:27:35 -07:00
Jordan Carlin
76eef03fe4
Merge branch 'main' of https://github.com/openhwgroup/cvw into installation
2024-08-07 20:22:55 -07:00
Huda-10xe
0303314f4e
Adding RVVI Functional Coverage Support
2024-08-07 14:31:16 +05:00
Jacob Pease
af2344d2d5
Merge branch 'main' of github.com:openhwgroup/cvw into spiboot
2024-08-06 17:09:39 -05:00
Jordan Carlin
42a9bbf28d
Merge branch 'main' of https://github.com/openhwgroup/cvw into installation
2024-07-25 21:21:57 -07:00
Jacob Pease
336a413f31
Added ability to split boot.memfile into boot.mem and data.mem.
2024-07-25 11:19:15 -05:00
Rose Thompson
d0a5b278b7
Factored out the rvvi testbench code into rvvitbwrapper.
2024-07-24 13:10:57 -05:00
Rose Thompson
b1a711ae0f
Converted fpga's rvvi from a config option to a testbench/fpga top level parameter and is envoked by passing --rvvi to wsim.
2024-07-24 12:47:50 -05:00
Jordan Carlin
47452ddaaa
Remove hardcoded /opt/riscv
2024-07-23 23:29:45 -07:00
Rose Thompson
6c212ebf0e
Changes are confirmed to work on the FPGA.
2024-07-23 17:39:38 -05:00
Rose Thompson
7223b15134
Merge branch 'rvvi'
2024-07-22 12:01:01 -05:00
Rose Thompson
9471dcd296
Refactored the fpga and testbench so the RVVI can be synthesized cleanly and simulated without any major code changes.
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Adds three new configuration parameters to control enabling the RVVI packetizer and how much latency should exist between packets and the initial startup delay.
2024-07-19 17:08:47 -05:00
Rose Thompson
276cb558f0
Merge pull request #880 from davidharrishmc/dev
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wsim elf handling and RV64GCK lockstep support
2024-07-14 11:40:30 -05:00
David Harris
26d4fbcc19
Switched ImperasDV to RV64GCK model to support crypto (issue #872 )
2024-07-13 21:42:14 -07:00
Rose Thompson
f83e6cf771
Fixed issue #874 .
2024-07-08 14:48:52 -05:00
David Harris
9279b2d56a
Added imperas configuration for Lee
2024-07-05 09:13:18 -07:00
David Harris
775930ae4f
Fixes to memfile generation for rv32. Updated new misa.B in imperas.ic, but need new version of ImperasDV to test
2024-07-04 07:36:56 -07:00
David Harris
8645441d00
Testbench automatically creates memfile, label, addr files if they are out of date or missing
2024-07-03 16:52:16 -07:00
David Harris
e72c8b8e09
Watchdog timeout on buildroot boot is a halting criteria
2024-07-02 14:22:51 -07:00
Jordan Carlin
5634577a24
Remove verilator hack
2024-06-28 17:28:43 -07:00
Jordan Carlin
221f710baf
Use QUESTA as flag for
2024-06-26 21:18:40 -07:00
Jordan Carlin
b76941d278
Use VCS built-in default macro instead of defining SIM_VCS
2024-06-21 15:17:59 -07:00
Ross Thompson
1c6ebb86a3
Added some debug code to count frames sent to the ethernet mac and frames sent to the phy.
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Removed the external reset of the phy and now it always reliably starts in the same way. The first 0x117 frames are always captured.
2024-06-20 12:54:12 -07:00
David Harris
25780f53ce
Fixed Verilator testbench issue from FunctionName by rolling back to old if. PC=0 detection is disabled for now.
2024-06-20 00:57:58 -07:00
Ross Thompson
d368f2e77e
Removed *** from testbench.
2024-06-19 13:51:37 -07:00
David Harris
4a4bbdfc43
More code cleanup
2024-06-14 09:50:07 -07:00
David Harris
b1c9450b4a
Code cleanup: RAM, fdivsqrt
2024-06-14 03:35:05 -07:00
Ross Thompson
563980443a
Merge branch 'main' into rvvi
2024-06-10 18:10:23 -07:00
Rose Thompson
92ee56c1a1
Yay. Finally found the bug which prevented wally.do from having functional coverage using riscvISACOV.
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testbench.sv was missing the trace2cov instance.
2024-05-27 17:25:20 -05:00
Rose Thompson
dc09e1c0c5
Modified names so they don't conflict with FPGA's axi signals.
2024-05-24 16:38:47 -05:00
Rose Thompson
73261e7f89
More cleanup. Close to the simpliest it can be.
2024-05-24 16:34:33 -05:00
Rose Thompson
bd2ec879d2
Removed unused axi signals from packetizer.
2024-05-24 16:31:27 -05:00
Rose Thompson
263be86119
Packetizer cleanup.
2024-05-24 16:27:09 -05:00
Rose Thompson
1f7d732dca
Moved the rvvisynth code to testbench since I only want this for simulation and fpga.
2024-05-24 16:10:58 -05:00
Rose Thompson
6e3ccbb9c1
Almost have it working for both buildroot and single elfs.
2024-05-17 17:34:29 -05:00
Rose Thompson
224b2e4dc4
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-05-17 17:10:28 -05:00
Rose Thompson
038aae388b
Yay. Finally found the issue with the integrated testbench.sv and imperasDV.
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The function which loads the elf file rvviRefInit must be called during an initial block
using a valid file name. Because of how the testbench was organized the elffile was not defined
until several cycles later so the call to rvviRefInit did not have a valid elf. Waiting several
cycles does not work. rvviRefInit requires being called in an initial block so it is not possible
to run back to back imperasDV simulations in the same run.
2024-05-17 16:45:01 -05:00
Rose Thompson
62eaca0e6e
Almost working ImperasDV with testbench.sv and wally.do. For some reason IDV is saying the instructions are mismatching.
2024-05-16 17:01:25 -05:00
Rose Thompson
8391b8b821
Progress towards unified regression.
2024-05-16 15:29:12 -05:00
Rose Thompson
08601d7270
Added functionallity to testbench.sv for single elf files.
2024-05-16 13:59:15 -05:00
Jordan Carlin
ef778da98d
Eliminate more logical operators and replace with bitwise
2024-05-15 10:50:23 -07:00
Rose Thompson
ceb31fec68
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-05-10 08:54:23 -05:00
Rose Thompson
b027fa44ef
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-05-10 08:53:00 -05:00
Rose Thompson
4bd5d334df
Modified testbench so it instantiates the function logger if DEBUG is greater than 0 rather than just 1.
2024-05-10 08:51:59 -05:00
