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315 Commits

Author SHA1 Message Date
Domenico Ottolia
fdbd238a87 Add machine-mode timer interrupts to mcause tests 2021-04-29 16:39:18 -04:00
Domenico Ottolia
c9cb2f51d1 Same but don't break sim-wally this time 2021-04-29 15:33:27 -04:00
Domenico Ottolia
fdd4deec2f Add more exceptions to medeleg tests 2021-04-29 15:32:13 -04:00
ushakya22
f139f248dc Working MIE timer tests 2021-04-29 15:19:43 -04:00
Domenico Ottolia
99a927be47 Add medeleg tests 2021-04-29 15:02:36 -04:00
Noah Boorstin
9275f141f9 same but do that right this time 2021-04-28 14:27:28 -04:00
Noah Boorstin
fce3d6a8b1 busybear: respect branch predictor disable config 2021-04-27 15:52:18 -04:00
Ross Thompson
d191bc6cc1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-26 14:28:09 -05:00
Ross Thompson
14a69c1d06 Added the ability to exclude branch predictor. 2021-04-26 14:27:42 -05:00
Noah Boorstin
922c8e450f ok but do that better 2021-04-26 14:38:05 -04:00
Noah Boorstin
24bbb674d3 linux: start using internal branch predictor signal 2021-04-26 14:34:38 -04:00
Noah Boorstin
9cbc769083 minor busybear fixes 2021-04-26 13:24:39 -04:00
Ross Thompson
44d28dbd1c Icache integrated! 
Merge branch 'icache-almost-working' into main
 2021-04-26 11:48:58 -05:00
bbracker
f921886451 merge cleanup; mem init is broken 2021-04-26 08:00:17 -04:00
bbracker
7947858481 it says I need to merge in order to pull 2021-04-26 07:46:24 -04:00
bbracker
8d77012995 progress on bus and lrsc 2021-04-26 07:43:16 -04:00
Ross Thompson
9e40fb072c Merge branch 'tests' into icache-almost-working 2021-04-25 21:25:36 -05:00
bbracker
46a1616079 thomas fixed it before I did 2021-04-24 09:38:52 -04:00
bbracker
5687ab1c96 do script refactor 2021-04-24 09:32:09 -04:00
Thomas Fleming
dc3ffc9244 Add address translation to busybear testbench 2021-04-23 20:12:20 -04:00
Noah Boorstin
50df9d11e1 busybear 2021-04-23 17:32:37 -04:00
Shriya Nadgauda
2a5c243b0b adding pipeline testing 2021-04-23 14:19:17 -04:00
Ross Thompson
c9bdaceddb Fixed icache for 32 bit. 
Merge branch 'cache' into main
 2021-04-22 16:45:29 -05:00
Thomas Fleming
f9e071baf8 Temporarily disable rv64 mmu test 
Will restore once cache revamp is pushed
 2021-04-22 13:19:18 -04:00
Noah Boorstin
0afd5ae5f6 buildroot: add workaround for weird initial MSTATUS state 2021-04-21 16:03:42 -04:00
Domenico Ottolia
82320033d5 Add tests for stval and mtval 2021-04-21 02:31:32 -04:00
Domenico Ottolia
fed42ffe19 Add tests for scause, and improve tests for sepc. Also make improvements to privileged test generator run.sh file 2021-04-21 01:12:55 -04:00
Domenico Ottolia
d5f86fadac Add tests for sepc register 2021-04-20 23:50:53 -04:00
Ross Thompson
649589ee2c Broken icache. Design is done. Time to debug. 2021-04-20 19:55:49 -05:00
Noah Boorstin
c7a09d2359 yay buildroot passes a decent amount of tests now 
gets through the first 15k instructions, that's good enough for now
also slight change to string parsing in busybear testbench
 2021-04-19 03:26:08 -04:00
Jarred Allen
59b340dac9 Merge branch 'main' into cache 2021-04-19 00:05:23 -04:00
Noah Boorstin
10c7ac7f73 slowly more buildroot progress 2021-04-18 18:18:07 -04:00
Noah Boorstin
d0a137ce0c neat verilog thing 2021-04-18 17:48:51 -04:00
Noah Boorstin
5902637632 buildroot: sim is now running! 
yes it only gets through 5 instructions right now. Yes that's my fault.
 2021-04-17 14:44:32 -04:00
Noah Boorstin
541fb22dc9 start to add buildroot testbench 
This still uses testbench-busybear.sv
I think it might be time to finally rename nearly 'busybear' thing to 'linux'
 2021-04-16 23:27:29 -04:00
bbracker
11cf251378 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-15 21:09:27 -04:00
bbracker
195cead01c working GPIO interrupt demo 2021-04-15 21:09:15 -04:00
Domenico Ottolia
b1cd107a00 Add tests for scause and ucause 2021-04-15 19:41:25 -04:00
Domenico Ottolia
8c4cfa5f69 Add 32 bit privileged tests 2021-04-15 16:55:39 -04:00
Jarred Allen
7b4b1a31ef Merge branch 'main' into cache 2021-04-15 13:47:19 -04:00
Thomas Fleming
d281ecd067 Remove imem from testbenches 2021-04-14 20:20:34 -04:00
Jarred Allen
757b64e487 Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/src/cache/dmapped.sv
	wally-pipelined/src/cache/line.sv
	wally-pipelined/src/ifu/icache.sv
 2021-04-14 18:24:32 -04:00
bbracker
ccff1e6c99 rv64 interrupt servicing 2021-04-14 10:19:42 -04:00
Noah Boorstin
3e0ed5a2b1 busybear: use (slightly) less terrible verilog 2021-04-14 00:18:44 -04:00
Noah Boorstin
18a4d5fc8d busybear testbench updates 
start speculative checking on CSR* satp, *
add some slight delays in some CSR checkings to make them deterministic

I realize this verilog is incredibly un-idiomatic. But I still don't
know of anything better. If you figure it out, please let me know
 2021-04-14 00:00:27 -04:00
Jarred Allen
357aed75ee A few more cache fixes 2021-04-13 01:07:40 -04:00
Jarred Allen
6ce4d44ae1 Merge from branch 'main' 2021-04-08 17:19:34 -04:00
bbracker
0c85b1c201 integrated peripheral testing into existing workflow 2021-04-08 15:31:39 -04:00
bbracker
c8c87bd0d8 merge testbench 2021-04-08 14:28:01 -04:00
Noah Boorstin
5f1cd43033 try to remove git-lfs stuff 2021-04-08 13:23:11 -04:00
Domenico Ottolia
1bdfac6a77 Cause an Illegal Instruction Exception when attempting to write readonly CSRs 2021-04-08 05:12:54 -04:00
Thomas Fleming
e807f5d771 Implement support for superpages 2021-04-08 02:44:59 -04:00
Ross Thompson
7f12c7af90 Switch to use RV64IC for the benchmarks. 
Still not working correctly with the icache.

instr
addr   correct   got
 2021-04-07 19:12:43 -05:00
Domenico Ottolia
9b82fbff5a Add privileged tests to testbench 2021-04-07 02:22:08 -04:00
Domenico Ottolia
bbdd4e1467 Add passing mtval and mepc tests 2021-04-07 02:21:05 -04:00
Ross Thompson
d901cfc848 Merge branch 'icache_bp_bug' into tests 
Not sure this merge is right.
 2021-04-06 21:46:40 -05:00
Ross Thompson
0a20e33971 Steps to getting branch predictor benchmarks running. 2021-04-06 21:20:51 -05:00
Noah Boorstin
c820910b29 add busybear boot files with git-lfs 2021-04-05 19:38:43 -04:00
Noah Boorstin
ce22a1de04 busybear: reenable 'ruthless' CSR checking 2021-04-05 12:53:30 -04:00
bbracker
ce7b2314ef Yee hoo first draft of PLIC plus self-checking tests 2021-04-04 06:40:53 -04:00
Thomas Fleming
8f31e00f6a Merge branch 'mmu' into main 
Conflicts:
	wally-pipelined/src/wally/wallypipelinedhart.sv
 2021-04-03 22:12:52 -04:00
Thomas Fleming
ac89947e98 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-03 22:09:50 -04:00
Noah Boorstin
2f503ee6b9 busybear: temporary stop after 800k instrs 2021-04-03 21:37:57 -04:00
Katherine Parry
08b31f7b2a Integrated FPU 2021-04-03 20:52:26 +00:00
James E. Stine
82cd900b65 Put back imperas testbench until figure out why m_supported is running for rv64ic 2021-04-02 08:19:25 -05:00
James E. Stine
9026357350 Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal. 2021-04-02 06:27:37 -05:00
Thomas Fleming
06032936bd Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-01 16:24:06 -04:00
Thomas Fleming
3f3d8f414d Merge branch 'mmu' of github.com:davidharrishmc/riscv-wally into mmu 2021-04-01 16:23:19 -04:00
Thomas Fleming
f9bf2fbc01 Implement sfence.vma and fix tlb writing 2021-04-01 15:55:05 -04:00
Noah Boorstin
4e62c7d5f5 busybear: temporarially stop checking CSRs 2021-03-31 14:14:32 -04:00
Noah Boorstin
679daeedf5 busybear: clean up questa warnings 2021-03-31 14:04:57 -04:00
Noah Boorstin
ddc56d8cd7 busybear: clean up questa warnings 2021-03-31 14:02:15 -04:00
Ross Thompson
1e83810450 Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally. 2021-03-30 23:18:20 -05:00
Thomas Fleming
e3d548d452 Merge remote-tracking branch 'origin/main' into main 
Bring icache and MMU code together

Conflicts:
	wally-pipelined/src/ifu/ifu.sv
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 22:24:47 -04:00
Thomas Fleming
4b2765f8e2 Complete basic page table walker 2021-03-30 22:19:27 -04:00
Thomas Fleming
7f7cc73dd3 Update virtual memory tests and move to separate folder 2021-03-30 22:18:29 -04:00
Domenico Ottolia
d0a78b15b7 Add one more test to WALLY-CAUSE, and update privileged testgen 2021-03-30 19:44:58 -04:00
Domenico Ottolia
8c7e247b58 Add mcause tests to testbench 2021-03-30 17:17:59 -04:00
ushakya22
ba01d57767 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-30 15:25:07 -04:00
Ross Thompson
a3925505bf fixed some bugs with the RAS. 2021-03-30 13:57:40 -05:00
Jarred Allen
6cda818f09 Merge branch 'cache2' into cache 
Conflicts:
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 13:32:33 -04:00
Jarred Allen
dd0b3fde59 Comment out failing tests 2021-03-30 13:07:26 -04:00
Jarred Allen
335178a1d3 Merge branch 'cache' into main 2021-03-30 12:56:19 -04:00
Jarred Allen
85164c7a87 Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/regression/wave-dos/ahb-waves.do
	wally-pipelined/src/ifu/ifu.sv
	wally-pipelined/testbench/testbench-busybear.sv
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 12:55:01 -04:00
David Harris
9f0a58e193 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-26 13:04:52 -04:00
David Harris
aa0d0d50d8 Added fp test to testbench 2021-03-26 13:03:23 -04:00
Noah Boorstin
606295db2f Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/testbench/testbench-busybear.sv
 2021-03-26 12:26:30 -04:00
Shreya Sanghai
edaf89e3d1 Merge branch 'PPA' into main 
Conflicts:
	wally-pipelined/testbench/testbench-privileged.sv
 2021-03-25 20:35:21 -04:00
Shreya Sanghai
d3e914f64b removed minor bugs 2021-03-25 20:29:50 -04:00
ShreyaSanghai
da4086db79 Removed PCW and InstrW from ifu 2021-03-26 01:53:19 +05:30
Jarred Allen
73d4dd8c15 Begin work on compressed instructions 2021-03-25 14:43:10 -04:00
Noah Boorstin
9eb1786fb1 busybear: quick fix to mem reading 
also stop ignoring mcause at the start
 2021-03-25 14:29:11 -04:00
Domenico Ottolia
fb00d0f209 Fix bugs with privileged tests 2021-03-25 14:06:05 -04:00
Noah Boorstin
ed37e933e5 busybear: stop NOPing out atomics 
and bump regression to check for 800k instrs, up from 200k
 2021-03-25 13:29:56 -04:00
Jarred Allen
e8e4e1bee2 rv64i linear control flow now working 2021-03-25 13:02:26 -04:00
Jarred Allen
9cbdb44728 Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/src/ifu/ifu.sv
 2021-03-25 00:51:12 -04:00
Teo Ene
1e691e120b Fix typo from last commit 2021-03-24 17:09:58 -05:00
Teo Ene
6a7b69ff2d Updated coremark_bare testbench for IM 2021-03-24 17:04:43 -05:00
Ross Thompson
a768c0406c Updated the function radix to have a new name FunctionName and it now pervents false transisions from the current function name when the PCD is flushed. 2021-03-24 13:03:43 -05:00
Domenico Ottolia
3909158619 re-organize privileged tests to be in rv64p to rv32p folders 2021-03-24 13:51:25 -04:00